From patchwork Tue Dec 12 11:51:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 177277 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7666402vqy; Tue, 12 Dec 2023 03:52:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IG4JPY91wXa223NZq4Qxt7B3nZx4Iik4YGtKvNMMbAH2awBIxz+qNUVT2mCfTTInlvSN1/B X-Received: by 2002:a92:c54a:0:b0:35e:6ae2:a4d8 with SMTP id a10-20020a92c54a000000b0035e6ae2a4d8mr8877323ilj.51.1702381960329; Tue, 12 Dec 2023 03:52:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702381960; cv=none; d=google.com; s=arc-20160816; b=cGMD7aVQmGf6unSLuaaI1S/d27cRcy4Be8aQEHvvFvywJC5XO2CjtcZ1CqT0O39TQD Xtg8Cn82TZ71XnNGD4XoHKNriGqxbNMA6ZCKfqBVf66HWDpOK3ClyYEbMXUw5Qkrvgqm idZFQWU5rfx96S3nbRwUx2xUA7lgsn5BoHbS1wr0AXvEF+5Ylkwmc9pQTpLj8GbzHugD EWMGcAbDAr3n3cxlglhRH4gzU9xi5dXmzxDFZQYRfE1+esKSq9FLWtd6DaQZc67ZMKY/ CtWGx5/SxEiD/+L0YTgxkb9iUQcTyUfam2TLzw2E0xP/eYfn9oIqmL5UViWvPLaBlks4 uakw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FFW+RKQFRS3hNZWC4B1zbsHCDFZ2KKuoWG+X51zxpU8=; fh=+g5tGayWdOm7NVf+9R7F5Bp+AAhjebsKXKT3IUU1ti0=; b=potx4Gpwn5NC4Ejjh2fKFuk/6R2gNdxOtbSjTnYCN6iGEhSgLRolYJiSA2U3i70NQh g6gHVDo6LCKH7V1fQm0Wq6COHo7BZfQstfVMrp3b43DbsMK0Gm329z2XFg64dC9IXNWL y7HzPkzEkn+4DJ/1sTsREABMxOJkPKQB7dehnznasXj87E7n48E7evnNO0GYZ3lvJ6fh RVeP9SUesMh26U71cCoVuTUnS17LtVgfblFuxUDIpScPtJ1/oU4vxsx2u4mRDBHm30fd ybMJjvuPkOxZEolvZbZkUTfPtXOPvCptwFt88ivnEKb973Hlssz3rDlf4FVbKR++W/gw BWFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Xix5qZOU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id g32-20020a635220000000b005bf77518dc6si7573588pgb.286.2023.12.12.03.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 03:52:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Xix5qZOU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 09EFE80ABFE6; Tue, 12 Dec 2023 03:52:39 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346363AbjLLLw2 (ORCPT + 99 others); Tue, 12 Dec 2023 06:52:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232372AbjLLLw0 (ORCPT ); Tue, 12 Dec 2023 06:52:26 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AA20C7; Tue, 12 Dec 2023 03:52:32 -0800 (PST) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BC7hick030299; Tue, 12 Dec 2023 11:52:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=FFW+RKQFRS3hNZWC4B1zbsHCDFZ2KKuoWG+X51zxpU8=; b=Xi x5qZOUSoGtL+dW1YOqKouzoIEM6hZ8nmQEYKtD8/7q4Gg0MM7cTvYuZvBrO+wVJI kBIxHUVkuzGH/GwrxSkxVScbNF0fkcnt7cooHcXErUiE/omj/GMAC4cwBttq2uBf 6ddzMrYpR5x5pdkvSUmiWmyG4Qqpa3WvwSFVyXOD+iTcTqBv/3HH5Y4ArETT8aqy RTRYfut8G70XyGeJl30mo1YFnU4afJPbrf8zUBSY8UGFaMhmLKs2CWIcAl8Ss7WH kgT9GmTGACEE0iSrh6aZl814QDWdo0L6pXfm8/fzGYZeYUITy4+Qn9EWsBqP0IAI aEV0YMv0pd88BCEmH+pQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uxkc80j70-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 11:52:15 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BCBqEr5010833 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 11:52:14 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 12 Dec 2023 03:52:09 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 1/5] net: mdio: ipq4019: move eth_ldo_rdy before MDIO bus register Date: Tue, 12 Dec 2023 19:51:46 +0800 Message-ID: <20231212115151.20016-2-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212115151.20016-1-quic_luoj@quicinc.com> References: <20231212115151.20016-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rFBmyHAOqszINrNtsIIpl7aytIWCU1RF X-Proofpoint-ORIG-GUID: rFBmyHAOqszINrNtsIIpl7aytIWCU1RF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 bulkscore=0 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 mlxscore=0 phishscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312120094 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 12 Dec 2023 03:52:39 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785076866771181582 X-GMAIL-MSGID: 1785076866771181582 The ethernet LDO provides the clock for the ethernet PHY that is connected with PCS, each LDO enables the clock output to each PCS, after the clock output enablement, the PHY GPIO reset can take effect. For the PHY taking the MDIO bus level GPIO reset, the ethernet LDO should be enabled before the MDIO bus register. For example, the qca8084 PHY takes the MDIO bus level GPIO reset for quad PHYs, there is another reason for qca8084 PHY using MDIO bus level GPIO reset instead of PHY level GPIO reset as below. The work sequence of qca8084: 1. enable ethernet LDO. 2. GPIO reset on quad PHYs. 3. register clock provider based on MDIO device of qca8084. 4. PHY probe function called for initializing common clocks. 5. PHY capabilities acquirement. If qca8084 takes PHY level GPIO reset in the step 4, the clock provider of qca8084 can't be registered correctly, since the clock parent(reading the current qca8084 hardware registers in step 3) of the registered clocks is deserted after GPIO reset. There are two PCS(UNIPHY) supported in SOC side on ipq5332, and three PCS(UNIPHY) supported on ipq9574. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 51 +++++++++++++++++++++------------ 1 file changed, 32 insertions(+), 19 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index abd8b508ec16..5273864fabb3 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -37,9 +37,12 @@ #define IPQ_PHY_SET_DELAY_US 100000 +/* Maximum SOC PCS(uniphy) number on IPQ platform */ +#define ETH_LDO_RDY_CNT 3 + struct ipq4019_mdio_data { - void __iomem *membase; - void __iomem *eth_ldo_rdy; + void __iomem *membase; + void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; struct clk *mdio_clk; }; @@ -206,19 +209,8 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, static int ipq_mdio_reset(struct mii_bus *bus) { struct ipq4019_mdio_data *priv = bus->priv; - u32 val; int ret; - /* To indicate CMN_PLL that ethernet_ldo has been ready if platform resource 1 - * is specified in the device tree. - */ - if (priv->eth_ldo_rdy) { - val = readl(priv->eth_ldo_rdy); - val |= BIT(0); - writel(val, priv->eth_ldo_rdy); - fsleep(IPQ_PHY_SET_DELAY_US); - } - /* Configure MDIO clock source frequency if clock is specified in the device tree */ ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE); if (ret) @@ -236,7 +228,7 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) struct ipq4019_mdio_data *priv; struct mii_bus *bus; struct resource *res; - int ret; + int ret, index; bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv)); if (!bus) @@ -252,11 +244,32 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) if (IS_ERR(priv->mdio_clk)) return PTR_ERR(priv->mdio_clk); - /* The platform resource is provided on the chipset IPQ5018 */ - /* This resource is optional */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (res) - priv->eth_ldo_rdy = devm_ioremap_resource(&pdev->dev, res); + /* These platform resources are provided on the chipset IPQ5018 or + * IPQ5332. + */ + /* This resource are optional */ + for (index = 0; index < ETH_LDO_RDY_CNT; index++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, index + 1); + if (res) { + priv->eth_ldo_rdy[index] = devm_ioremap(&pdev->dev, + res->start, + resource_size(res)); + + /* The ethernet LDO enable is necessary to reset PHY + * by GPIO, some PHY(such as qca8084) GPIO reset uses + * the MDIO level reset, so this function should be + * called before the MDIO bus register. + */ + if (priv->eth_ldo_rdy[index]) { + u32 val; + + val = readl(priv->eth_ldo_rdy[index]); + val |= BIT(0); + writel(val, priv->eth_ldo_rdy[index]); + fsleep(IPQ_PHY_SET_DELAY_US); + } + } + } bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read_c22; From patchwork Tue Dec 12 11:51:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 177278 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7666428vqy; Tue, 12 Dec 2023 03:52:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IE76AQvWj+pMyzgNL+3eT7HFpRJw580IMoVGrajshs8kXEk2jDjr10qymI8esNncVIlEMNF X-Received: by 2002:a17:90a:fb4e:b0:28a:c3a4:e660 with SMTP id iq14-20020a17090afb4e00b0028ac3a4e660mr713389pjb.41.1702381964802; Tue, 12 Dec 2023 03:52:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702381964; cv=none; d=google.com; s=arc-20160816; b=i3cYM9IttuDAhFwmDG/9YUTXWie5bIFw7PnfJkpHAdOtKpzOP/zEezNiOWjcOWJ8Oe rGwk87teDg65pVAM8GNsRZ5N8ez45U+9mr2J2Gx1gGiKIoQa1XB+mS75hHk3DKLJbDwa M8fbgj71fk/Nz7zzZJDJTpCLwQLp504y38EUM+Ms0c8b7VGh4+MrRESC11VKW/0LxA6B spdQ7c22zSp3BnjaBFhLPvEAgmjSCIP8L1N88S7sQhy0JlswyZC7NJYs5AkHinVFFFLr b68HsTnUWYU0r11qLwU5GE07KCA62PfRArgkHkP/lla9CJosLo29naZnNmcLnEpR/JC8 fmPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FHdl/TT3won4UjUmJ6S5WbkkqP4hoRaNfjOceJqqX8M=; fh=+g5tGayWdOm7NVf+9R7F5Bp+AAhjebsKXKT3IUU1ti0=; b=LVREVVyFEoQBinqpR07DKb3hhxnTCcq9YpjlWeEERMuicvEsEm8J8Pwx5FfGiqHbii 1lsQFeSjr/3h+mQajqW+CqSSt2lpdmiaqf9/f2iMLU5ws/uYSYosfXn/jC7NZErvSj1f bIVJ4lbCzZ8PKfcRqwzwj+OosaRtsoDjmbBEkekYYsM4eQxzdhvtVPtqQ+AYwP/baI/R IGl/0PVjKoXtSpb80x7ezNjBN6ZKq+Gzdv9nE4sPEHGhEUW1Ub7RxlNGILmo2RaJIdk6 QdxAsWcpERxvY9e4SOW1x201XHeqdplK20//XSpLk3ZxJfXxAZIIwUdEgf5VJglEimn1 4tfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=kc8Rt631; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id c37-20020a634e25000000b005c682e0ced3si7740712pgb.97.2023.12.12.03.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 03:52:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=kc8Rt631; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 83FDA804C234; Tue, 12 Dec 2023 03:52:43 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346375AbjLLLwb (ORCPT + 99 others); Tue, 12 Dec 2023 06:52:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346388AbjLLLw3 (ORCPT ); Tue, 12 Dec 2023 06:52:29 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3B3ED5; Tue, 12 Dec 2023 03:52:34 -0800 (PST) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BCBnek2025206; Tue, 12 Dec 2023 11:52:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=FHdl/TT3won4UjUmJ6S5WbkkqP4hoRaNfjOceJqqX8M=; b=kc 8Rt631FGOar3EabxtCIYtKL/rE5rLjCV0pivIhYtrKsULhUuDvJVnYMRCYh5S+AX QOLjmXx21Rvwg/Qf2slOwuO5sVG6u5nuCAmW/4TYXxEFdYvQx79a4SKXweNg3Y4l Nv5D+7l3cMNjbnr2BxiUVzSqn1ALwGlKnvcoHqJpTfZ+rWM9ff4NQNf/yn284Ue7 P6DV98tVm9OWXMXYDvc0pM1vJJ5QCAn9HiWm9vEFvBFM9PlTyr7/RFlAUBR6ZUBl UUq0c7ik5nG/0KCxt3VLc1mXpxkWn5e/fn3PxGZqGAhvgTb3pyW64tAuHC4aW2vX zXTrpdEAp7NWOfxlh2gQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uxepkh5ax-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 11:52:19 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BCBqIGi000446 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 11:52:18 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 12 Dec 2023 03:52:14 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 2/5] net: mdio: ipq4019: enable the SoC uniphy clocks for ipq5332 platform Date: Tue, 12 Dec 2023 19:51:47 +0800 Message-ID: <20231212115151.20016-3-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212115151.20016-1-quic_luoj@quicinc.com> References: <20231212115151.20016-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xNv-xfvERv4zNJNaDem4EyIwDkrRvFH3 X-Proofpoint-ORIG-GUID: xNv-xfvERv4zNJNaDem4EyIwDkrRvFH3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 malwarescore=0 adultscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312120095 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 12 Dec 2023 03:52:43 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785076871117384799 X-GMAIL-MSGID: 1785076871117384799 On the platform ipq5332, the related SoC uniphy GCC clocks need to be enabled for making the MDIO slave devices accessible. These UNIPHY clocks are from the SoC platform GCC clock provider, which are enabled for the connected PHY devices working. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 75 ++++++++++++++++++++++++++++----- 1 file changed, 64 insertions(+), 11 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 5273864fabb3..582e41ab0990 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -35,15 +35,36 @@ /* MDIO clock source frequency is fixed to 100M */ #define IPQ_MDIO_CLK_RATE 100000000 +/* SoC UNIPHY fixed clock */ +#define IPQ_UNIPHY_AHB_CLK_RATE 100000000 +#define IPQ_UNIPHY_SYS_CLK_RATE 24000000 + #define IPQ_PHY_SET_DELAY_US 100000 /* Maximum SOC PCS(uniphy) number on IPQ platform */ #define ETH_LDO_RDY_CNT 3 +enum mdio_clk_id { + MDIO_CLK_MDIO_AHB, + MDIO_CLK_UNIPHY0_AHB, + MDIO_CLK_UNIPHY0_SYS, + MDIO_CLK_UNIPHY1_AHB, + MDIO_CLK_UNIPHY1_SYS, + MDIO_CLK_CNT +}; + struct ipq4019_mdio_data { void __iomem *membase; void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; - struct clk *mdio_clk; + struct clk *clk[MDIO_CLK_CNT]; +}; + +static const char *const mdio_clk_name[] = { + "gcc_mdio_ahb_clk", + "gcc_uniphy0_ahb_clk", + "gcc_uniphy0_sys_clk", + "gcc_uniphy1_ahb_clk", + "gcc_uniphy1_sys_clk" }; static int ipq4019_mdio_wait_busy(struct mii_bus *bus) @@ -209,14 +230,43 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, static int ipq_mdio_reset(struct mii_bus *bus) { struct ipq4019_mdio_data *priv = bus->priv; - int ret; + int ret, index; + unsigned long rate; + + /* For the platform ipq5332, there are two SoC uniphies available + * for connecting with ethernet PHY, the SoC uniphy gcc clock + * should be enabled for resetting the connected device such + * as qca8386 switch, qca8081 PHY or other PHYs effectively. + * + * Configure MDIO/UNIPHY clock source frequency if clock instance + * is specified in the device tree. + */ + for (index = MDIO_CLK_MDIO_AHB; index < MDIO_CLK_CNT; index++) { + switch (index) { + case MDIO_CLK_MDIO_AHB: + rate = IPQ_MDIO_CLK_RATE; + break; + case MDIO_CLK_UNIPHY0_AHB: + case MDIO_CLK_UNIPHY1_AHB: + rate = IPQ_UNIPHY_AHB_CLK_RATE; + break; + case MDIO_CLK_UNIPHY0_SYS: + case MDIO_CLK_UNIPHY1_SYS: + rate = IPQ_UNIPHY_SYS_CLK_RATE; + break; + default: + break; + } - /* Configure MDIO clock source frequency if clock is specified in the device tree */ - ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE); - if (ret) - return ret; + ret = clk_set_rate(priv->clk[index], rate); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[index]); + if (ret) + return ret; + } - ret = clk_prepare_enable(priv->mdio_clk); if (ret == 0) mdelay(10); @@ -240,10 +290,6 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) if (IS_ERR(priv->membase)) return PTR_ERR(priv->membase); - priv->mdio_clk = devm_clk_get_optional(&pdev->dev, "gcc_mdio_ahb_clk"); - if (IS_ERR(priv->mdio_clk)) - return PTR_ERR(priv->mdio_clk); - /* These platform resources are provided on the chipset IPQ5018 or * IPQ5332. */ @@ -271,6 +317,13 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) } } + for (index = 0; index < MDIO_CLK_CNT; index++) { + priv->clk[index] = devm_clk_get_optional(&pdev->dev, + mdio_clk_name[index]); + if (IS_ERR(priv->clk[index])) + return PTR_ERR(priv->clk[index]); + } + bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read_c22; bus->write = ipq4019_mdio_write_c22; From patchwork Tue Dec 12 11:51:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 177280 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7666494vqy; Tue, 12 Dec 2023 03:52:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IFPLbVbZrjrcnmhpfJlKMJ+MBzk02KGRadfTAXg5hMl8vtgZKBwKMgB84OZLGFFJUlHFLXU X-Received: by 2002:a05:6808:1910:b0:3b9:df4a:978b with SMTP id bf16-20020a056808191000b003b9df4a978bmr7840804oib.82.1702381975124; Tue, 12 Dec 2023 03:52:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702381975; cv=none; d=google.com; s=arc-20160816; b=LIPcXieSJOBsTzIx/Y4DPyDEGePe7FB6WtOqubov/g9cRnD4lRqJWhi69L8wjUvuJ3 7eqUg5k6CUBNIG0cAR8BouTJA9KDi1I/ExtaaD2rD0lfwOApDIpygRwvLkE9bsBKunWs IURPg/CgZz3VFbyRpFIjtYodzsxeAkpbcvWSzqHMTTRTZvSrxehgCXNIf3frN/zCmHk5 WwOuttN/RvfnZeOE0zF+dsDeswA71YcMSLv5cGC+uGE6qNf+i28HtSSTIqO6fuyrlWKr 87AcmHkha/84xvsUy/N/Lg9W2B5TnSqlrktrmmPmK2XYIBinJmkF30OqvGTwcfw8qKOn De+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=m4nJgTCxtS3Z9eeaD6Mti1C/kz7EN1wZJ9K0j7cQ9OA=; fh=+g5tGayWdOm7NVf+9R7F5Bp+AAhjebsKXKT3IUU1ti0=; b=M7HI+5Uc/8+OmDWK9CPHdhT4EBOxdCALkM5jREgOxda/m/yafQPxoZCbz61jmrj+lK 9GHnkQ4i8C3+MCxbgcYo8RoYGckS1q0Kg179UadcTkOYRAoLQLxCsTPtfu24WwOKjM1j OP6VY5HUW6La6b3leKwCpaydJzq6TiEF9Xre10VfJERHBTPSI2zmwHXzIxXmr1aQqG9K 2pEN9X9UN4HisuOoyarScaKEp3cyPOJRmFHPqW42Dz/MI6YCPePA73AyNQ3zOzs676nd eWcOrWrTojRh+8CYrHu+HF4HGEfjFbhRBn6GK5rEfpQN7TVsCL7OVKVpwbxgVp8HX4jG 5oDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=C04ubFVQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id i13-20020a6551cd000000b005ca186affedsi2795798pgq.372.2023.12.12.03.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 03:52:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=C04ubFVQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 82D2A8021385; Tue, 12 Dec 2023 03:52:52 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346412AbjLLLwg (ORCPT + 99 others); Tue, 12 Dec 2023 06:52:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346385AbjLLLw3 (ORCPT ); Tue, 12 Dec 2023 06:52:29 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54928ED; Tue, 12 Dec 2023 03:52:35 -0800 (PST) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BCA5ZZv017172; Tue, 12 Dec 2023 11:52:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=m4nJgTCxtS3Z9eeaD6Mti1C/kz7EN1wZJ9K0j7cQ9OA=; b=C0 4ubFVQiIVMyBlZs64Sof7NmLPe7wsBAYCNBiU49F1KBV+AKv6JrGcoaVYi26KfhX wu/e7vbAGKHc7v0kRTjE2VYXysHAokN/xaXtLIYFOl9qGiRgXcSBA9ThCLoLeuRp SV4azCQQfeNjCNvenJ3Hi9KJ9qNPlvQE5Hk04AVKP24S1ijd7MVsdO3Wm1Rby7uw sVs9b4xge4/rRgmGPaXxYq4Ten6UavrmPemvbxtkcAZG8B5fu7ORxoUWwPxx8fTr XWdriJOS5KtEcRZgTNRQ2zp1xQKLxnk0ZcegMLHIpY7nNS7H1e0t8KAHgabSXaa2 OvbvsnzqX5IMeQC+EDXA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uxnf706vw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 11:52:25 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BCBqOQw017127 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 11:52:24 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 12 Dec 2023 03:52:18 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 3/5] net: mdio: ipq4019: configure CMN PLL clock for ipq5332 Date: Tue, 12 Dec 2023 19:51:48 +0800 Message-ID: <20231212115151.20016-4-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212115151.20016-1-quic_luoj@quicinc.com> References: <20231212115151.20016-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hUbbc-LDvDjm3DVwlOECWuGjlKuy36_8 X-Proofpoint-GUID: hUbbc-LDvDjm3DVwlOECWuGjlKuy36_8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 spamscore=0 phishscore=0 clxscore=1015 adultscore=0 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312120095 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 12 Dec 2023 03:52:52 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785076882140397286 X-GMAIL-MSGID: 1785076882140397286 The reference clock of CMN PLL block is selectable, the internal 48MHZ is used by default. The output clock of CMN PLL block is for providing the clock source of ethernet device(such as qca8084), there are 1 * 25MHZ and 3 * 50MHZ output clocks available for the ethernet devices. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 137 +++++++++++++++++++++++++++++++- 1 file changed, 136 insertions(+), 1 deletion(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 582e41ab0990..8d3c6bae379f 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -44,6 +44,25 @@ /* Maximum SOC PCS(uniphy) number on IPQ platform */ #define ETH_LDO_RDY_CNT 3 +#define CMN_PLL_REFERENCE_SOURCE_SEL 0x28 +#define CMN_PLL_REFCLK_SOURCE_DIV GENMASK(9, 8) + +#define CMN_PLL_REFERENCE_CLOCK 0x784 +#define CMN_PLL_REFCLK_EXTERNAL BIT(9) +#define CMN_PLL_REFCLK_DIV GENMASK(8, 4) +#define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) + +#define CMN_PLL_POWER_ON_AND_RESET 0x780 +#define CMN_ANA_EN_SW_RSTN BIT(6) + +#define CMN_REFCLK_INTERNAL_48MHZ 0 +#define CMN_REFCLK_EXTERNAL_25MHZ 1 +#define CMN_REFCLK_EXTERNAL_31250KHZ 2 +#define CMN_REFCLK_EXTERNAL_40MHZ 3 +#define CMN_REFCLK_EXTERNAL_48MHZ 4 +#define CMN_REFCLK_EXTERNAL_50MHZ 5 +#define CMN_REFCLK_INTERNAL_96MHZ 6 + enum mdio_clk_id { MDIO_CLK_MDIO_AHB, MDIO_CLK_UNIPHY0_AHB, @@ -55,6 +74,7 @@ enum mdio_clk_id { struct ipq4019_mdio_data { void __iomem *membase; + void __iomem *cmn_membase; void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; struct clk *clk[MDIO_CLK_CNT]; }; @@ -227,12 +247,116 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, return 0; } +/* For the CMN PLL block, the reference clock can be configured according to + * the device tree property "cmn-reference-clock", the internal 48MHZ is used + * by default on the ipq533 platform. + * + * The output clock of CMN PLL block is provided to the ethernet devices, + * threre are 4 CMN PLL output clocks (1*25MHZ + 3*50MHZ) enabled by default. + * + * Such as the output 50M clock for the qca8084 ethernet PHY. + */ +static int ipq_cmn_clock_config(struct mii_bus *bus) +{ + int ret; + u32 reg_val, src_sel, ref_clk; + struct ipq4019_mdio_data *priv; + + priv = bus->priv; + if (priv->cmn_membase) { + reg_val = readl(priv->cmn_membase + CMN_PLL_REFERENCE_CLOCK); + + /* Select reference clock source */ + ret = of_property_read_u32(bus->parent->of_node, + "cmn-reference-clock", + &ref_clk); + if (!ret) { + switch (ref_clk) { + case CMN_REFCLK_INTERNAL_48MHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7); + break; + case CMN_REFCLK_EXTERNAL_25MHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3)); + break; + case CMN_REFCLK_EXTERNAL_31250KHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 4)); + break; + case CMN_REFCLK_EXTERNAL_40MHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 6)); + break; + case CMN_REFCLK_EXTERNAL_48MHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7)); + break; + case CMN_REFCLK_EXTERNAL_50MHZ: + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | + CMN_PLL_REFCLK_INDEX); + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8)); + break; + case CMN_REFCLK_INTERNAL_96MHZ: + src_sel = readl(priv->cmn_membase + + CMN_PLL_REFERENCE_SOURCE_SEL); + src_sel &= ~CMN_PLL_REFCLK_SOURCE_DIV; + src_sel |= FIELD_PREP(CMN_PLL_REFCLK_SOURCE_DIV, 0); + writel(src_sel, priv->cmn_membase + + CMN_PLL_REFERENCE_SOURCE_SEL); + + reg_val &= ~CMN_PLL_REFCLK_DIV; + reg_val |= FIELD_PREP(CMN_PLL_REFCLK_DIV, 2); + break; + default: + return -EINVAL; + } + } else if (ret == -EINVAL) { + /* If the cmn-reference-clock is not specified, + * the internal 48MHZ is selected by default. + */ + reg_val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7); + } else { + return ret; + } + + writel(reg_val, priv->cmn_membase + CMN_PLL_REFERENCE_CLOCK); + + /* assert CMN PLL */ + reg_val = readl(priv->cmn_membase + CMN_PLL_POWER_ON_AND_RESET); + reg_val &= ~CMN_ANA_EN_SW_RSTN; + writel(reg_val, priv->cmn_membase); + fsleep(IPQ_PHY_SET_DELAY_US); + + /* deassert CMN PLL */ + reg_val |= CMN_ANA_EN_SW_RSTN; + writel(reg_val, priv->cmn_membase + CMN_PLL_POWER_ON_AND_RESET); + fsleep(IPQ_PHY_SET_DELAY_US); + } + + return 0; +} + static int ipq_mdio_reset(struct mii_bus *bus) { struct ipq4019_mdio_data *priv = bus->priv; int ret, index; unsigned long rate; + ret = ipq_cmn_clock_config(bus); + if (ret) + return ret; + /* For the platform ipq5332, there are two SoC uniphies available * for connecting with ethernet PHY, the SoC uniphy gcc clock * should be enabled for resetting the connected device such @@ -296,7 +420,7 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) /* This resource are optional */ for (index = 0; index < ETH_LDO_RDY_CNT; index++) { res = platform_get_resource(pdev, IORESOURCE_MEM, index + 1); - if (res) { + if (res && strcmp(res->name, "cmn_blk")) { priv->eth_ldo_rdy[index] = devm_ioremap(&pdev->dev, res->start, resource_size(res)); @@ -317,6 +441,17 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) } } + /* The CMN block resource is for providing clock source to ethernet, + * which can be optionally configured on the platform ipq9574 and + * ipq5332. + */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cmn_blk"); + if (res) { + priv->cmn_membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->cmn_membase)) + return PTR_ERR(priv->cmn_membase); + } + for (index = 0; index < MDIO_CLK_CNT; index++) { priv->clk[index] = devm_clk_get_optional(&pdev->dev, mdio_clk_name[index]); From patchwork Tue Dec 12 11:51:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 177279 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7666470vqy; Tue, 12 Dec 2023 03:52:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IGG5Do77A0OyJdYB67OWHOsHL3MR+NE5hBPSSp0GH0FD25K34M1N8PjqrmjtLA4ITsavX9I X-Received: by 2002:aa7:830f:0:b0:6ce:f7cb:8e53 with SMTP id bk15-20020aa7830f000000b006cef7cb8e53mr1901631pfb.19.1702381972674; Tue, 12 Dec 2023 03:52:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702381972; cv=none; d=google.com; s=arc-20160816; b=W9GpxAkzsg9xk0nMGmaomJn8Rz+OtMZiZRE340wGD9vny0akT3eCfIssWEyH/6wo34 y+o3UVpichsjNFdl4Y3ihS5e5jY3WbSUbWHkm9WUgKQxD8+kvclTbkEgZ0S2AmeKRfAr Gi5imIbAs8u/ehNt79hC5JUirOW24Xs95aZdOdNqu83ui56MyV63TjW7VV/hd6hGgwhz VNNdMCv4d6PUg2vQgZ7NE3zQM/ps960wzTUi1CniO3xpUZjiA47eVdcCowoHkQK6PCTG BzfyU5vOzAOyPSnXfJamtxqoPAzPkkwV847OdeJTJGr5z+6uYhJZwfDG2gLOiReIObds ViQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=R5O8Y95EQq1XCnPLI8nSW8LERHti2kL41mtzxDGyskg=; fh=+g5tGayWdOm7NVf+9R7F5Bp+AAhjebsKXKT3IUU1ti0=; b=UD4mBA0YPYTW3C3sa+UBkrHvWeR0gozaYDKQnroLm9Pwulj5BrreqSUyXx5af6wmId nm38aiE6p+VE36iuqhlosXMY+ahYqVJ40Gzq1qRMcKwFFT0rjWrbuUto3lGXf/AKL9+0 53eJWP97/xqQ+hui6rHEegAyMNiyzbFafxHS5S/L1U/661aNL+h4o7EBIVS7JeaCN2ny p/lO6afPtjIETlFnCq9SBZdWx+fZ/MqAswKtjDGx73nznSDSCeLYzOrSHVRXCitc9t2l rs9KwFjE25PWfOGCHlkcVkWMDxEFxa3YRqvWw9Y2vWfFj5UY84ORKl+gq0rukZzRydPD JXCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=WYwLB8dA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from pete.vger.email (pete.vger.email. [2620:137:e000::3:6]) by mx.google.com with ESMTPS id b4-20020a056a000cc400b006ce789c5378si7575864pfv.373.2023.12.12.03.52.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 03:52:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=WYwLB8dA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id C80B280D0C5B; Tue, 12 Dec 2023 03:52:48 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232388AbjLLLwi (ORCPT + 99 others); Tue, 12 Dec 2023 06:52:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346403AbjLLLwd (ORCPT ); Tue, 12 Dec 2023 06:52:33 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3A95D5; Tue, 12 Dec 2023 03:52:39 -0800 (PST) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BCB7xHK018958; Tue, 12 Dec 2023 11:52:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=R5O8Y95EQq1XCnPLI8nSW8LERHti2kL41mtzxDGyskg=; b=WY wLB8dAK/mZxCcPtpCKRWCPBg0YJh2zh7nKrhEfymZvuhYUpHCjnHaAf1zqlzvl0d dimA5IxShDPheYe+y4H5XtimpZYp4aNlePqk8HdwQXSD7eLuIVAPq44Lh6kMdxgk DpdlHEjR3AZMWOnCV4JXwwiAE/MEizwaUWynyYUK2yFDrjLo7fdOsLEFWDDyWxWZ nNw7n1MeJCx6uobm32xoR/ifsfVrs1U28gQh3eVJMQqX3H8Hj62CzLBMjYaMBin0 TgS56Ta07FqASEe9D4gVj8MFy/4nw/j6R4fgb1PK7rgT/lVwBuWse746FuuAzArX WjkYcApo39PfDjvOqIiA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ux65328d3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 11:52:29 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BCBqSbk011434 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 11:52:28 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 12 Dec 2023 03:52:24 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 4/5] net: mdio: ipq4019: support MDIO clock frequency divider Date: Tue, 12 Dec 2023 19:51:49 +0800 Message-ID: <20231212115151.20016-5-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212115151.20016-1-quic_luoj@quicinc.com> References: <20231212115151.20016-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Oc6fbOybxjCZGKEvFscy1tVagLdlQVuT X-Proofpoint-GUID: Oc6fbOybxjCZGKEvFscy1tVagLdlQVuT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312120095 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 12 Dec 2023 03:52:48 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785076879611379722 X-GMAIL-MSGID: 1785076879611379722 The MDIO clock frequency can be divided according to the MDIO control register value. The MDIO system clock is fixed to 100MHZ, the working frequency is 100MHZ/(divider + 1), the divider value is from the bit[7:0] of control register 0x40. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 45 +++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 8d3c6bae379f..2c724d3cd513 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -29,6 +29,9 @@ /* 0 = Clause 22, 1 = Clause 45 */ #define MDIO_MODE_C45 BIT(8) +/* MDC frequency is SYS_CLK/(MDIO_CLK_DIV + 1), SYS_CLK is 100MHz */ +#define MDIO_CLK_DIV_MASK GENMASK(7, 0) + #define IPQ4019_MDIO_TIMEOUT 10000 #define IPQ4019_MDIO_SLEEP 10 @@ -77,6 +80,7 @@ struct ipq4019_mdio_data { void __iomem *cmn_membase; void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; struct clk *clk[MDIO_CLK_CNT]; + int clk_div; }; static const char *const mdio_clk_name[] = { @@ -110,6 +114,7 @@ static int ipq4019_mdio_read_c45(struct mii_bus *bus, int mii_id, int mmd, data = readl(priv->membase + MDIO_MODE_REG); data |= MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -151,6 +156,7 @@ static int ipq4019_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) data = readl(priv->membase + MDIO_MODE_REG); data &= ~MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -183,6 +189,7 @@ static int ipq4019_mdio_write_c45(struct mii_bus *bus, int mii_id, int mmd, data = readl(priv->membase + MDIO_MODE_REG); data |= MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -226,6 +233,7 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, data = readl(priv->membase + MDIO_MODE_REG); data &= ~MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -397,6 +405,39 @@ static int ipq_mdio_reset(struct mii_bus *bus) return ret; } +static int ipq_mdio_clk_set(struct platform_device *pdev, int *clk_div) +{ + int freq; + + /* Keep the MDIO clock divider as the hardware default value 0xff if + * the MDIO property "clock-frequency" is not specified. + */ + if (of_property_read_u32(pdev->dev.of_node, "clock-frequency", &freq)) { + *clk_div = 0xff; + return 0; + } + + /* MDC frequency is SYS_CLK/(MDIO_CLK_DIV + 1), SYS_CLK is fixed + * to 100MHz, the MDIO_CLK_DIV can be only configured the valid + * values, other values cause malfunction. + */ + switch (freq) { + case 12500000: + case 6250000: + case 3125000: + case 1562500: + case 781250: + case 390625: + *clk_div = DIV_ROUND_UP(IPQ_MDIO_CLK_RATE, freq) - 1; + break; + default: + dev_err(&pdev->dev, "Invalid clock frequency %dHZ\n", freq); + return -EINVAL; + } + + return 0; +} + static int ipq4019_mdio_probe(struct platform_device *pdev) { struct ipq4019_mdio_data *priv; @@ -459,6 +500,10 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) return PTR_ERR(priv->clk[index]); } + ret = ipq_mdio_clk_set(pdev, &priv->clk_div); + if (ret) + return ret; + bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read_c22; bus->write = ipq4019_mdio_write_c22; From patchwork Tue Dec 12 11:51:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 177281 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp7666547vqy; Tue, 12 Dec 2023 03:53:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IGSQy7mtxG19eVa+kSy2hUHHcYmPg4t2pBPhhJeRhqYmirySFHz1ZniR44CIUmtHMUP4YhQ X-Received: by 2002:a92:c24a:0:b0:35d:59a2:2c7 with SMTP id k10-20020a92c24a000000b0035d59a202c7mr8581299ilo.103.1702381981348; Tue, 12 Dec 2023 03:53:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702381981; cv=none; d=google.com; s=arc-20160816; b=oFFD9NX2+JgGis5RNBx/fPicV1IhSQ3kDcseSnuCY0/QkIiI1PCI2DXYaBOe6rwqTS MuZfcbtgvYusYb3WPCtkLySC7bxEPHFS/TzXcTLQyLC1V3uNtG6X4UWGelP0SQAzKvdd l7X7I8aXYQ9JD4CLgsXbECXQID7+0j8z/F8c3HJhPCi0jOAnerqOZoPZCh/CvstYNMQO FSsu7EyOMgCSBKt30qlUpGnTOWQzPIx26/pMChcYKtME3mEd0XQg7RKlxJ6rkJamu90w t4+wYE6hgF0DSKut3Vl/e5kq715y9HU4SKhT4QvF+ql3YRT/P8S+AVM3cbgMIsCnvQhb IPFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EN/C3ZfjbBY3sr95sU9YA7yvahWNKAK+LBenwOFH5L8=; fh=+g5tGayWdOm7NVf+9R7F5Bp+AAhjebsKXKT3IUU1ti0=; b=RZrko5o0J7UD6LBo8g5ZjqInUhDMdvoD9iI2TRa9oPpu5gtSHsoe9edr05V9ND8A5I pdZR1cpOhlJ9MJqpsjoX+AePlAO1NeoM2JgmhGWr2N5Nc5sANRLzqsKUNXiwvdrU83kf 8CdJdqRA/IBMqQafvGlV8XKdhiZCHrI8w6jZQhi1RGFCF979Mw247BaNjiWf92TkIMqV nwwyqUm7NAZC1BYzvgd7lAbiBln+7f+Oq5cM0QKcXhHXrFGVY8byoMxluzNzla+GiZI1 tTuxeqkHqcSXFz9wWRGDTviqsYKcCg2ixt/MkXSrTm1Heqtw5PKCX3uIBIUgBI00iyTK Ktew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=j7yAaofQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id k7-20020a63d847000000b005bd70a177a3si7332660pgj.876.2023.12.12.03.53.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 03:53:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=j7yAaofQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 19FA280532DB; Tue, 12 Dec 2023 03:52:57 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346398AbjLLLwq (ORCPT + 99 others); Tue, 12 Dec 2023 06:52:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346442AbjLLLwn (ORCPT ); Tue, 12 Dec 2023 06:52:43 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5884FF; Tue, 12 Dec 2023 03:52:44 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BC4FhaG012775; Tue, 12 Dec 2023 11:52:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=EN/C3ZfjbBY3sr95sU9YA7yvahWNKAK+LBenwOFH5L8=; b=j7 yAaofQ4h3oAAQ4iqnPGAWG0Vc3AX0KXD0L3TC5XA3GHvO1YJ7N65/LChyeHAsZ+p BqahkTXRx23vIN96n+eXAKV5ThX4gRFP7sAtOtxjMPq+tztjPD+LGeAmcbWpDOdk a3DLJ6fSiKp1szu8gpFITuZ6oTaa57wyNCA4IxG3POY7s8xYgXjmLn97dAnhkvnp G/fN/3AsusJoUzX7puN+HWtpkR/BkfG8un75ZmzvTmJrq//BTmUO/nhnGG3ZU81J 1O4zBNmxV+gE2aEdTFTFmj4nSuq90Mrvl+F7BKZ/+lKBxU1eIPhItWRIrcHSxE3x F2uBxHluuP+mfTpGcMXw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uxgbb0xet-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 11:52:34 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BCBqXYd006589 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 11:52:33 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 12 Dec 2023 03:52:28 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v2 5/5] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform Date: Tue, 12 Dec 2023 19:51:50 +0800 Message-ID: <20231212115151.20016-6-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212115151.20016-1-quic_luoj@quicinc.com> References: <20231212115151.20016-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Uho5eMoJ3xNgMA2Nt1m5SEBgAYPjeNR6 X-Proofpoint-ORIG-GUID: Uho5eMoJ3xNgMA2Nt1m5SEBgAYPjeNR6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312120095 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 12 Dec 2023 03:52:57 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785076888512484308 X-GMAIL-MSGID: 1785076888512484308 Update the yaml file for the new DTS properties. 1. cmn-reference-clock for the CMN PLL source clock select. 2. clock-frequency for MDIO clock frequency config. 3. add uniphy AHB & SYS GCC clocks. 4. add reset-gpios for MDIO bus level reset. Signed-off-by: Luo Jie --- .../bindings/net/qcom,ipq4019-mdio.yaml | 157 +++++++++++++++++- 1 file changed, 153 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml index 3407e909e8a7..9546a6ad7841 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml @@ -20,6 +20,8 @@ properties: - enum: - qcom,ipq6018-mdio - qcom,ipq8074-mdio + - qcom,ipq9574-mdio + - qcom,ipq5332-mdio - const: qcom,ipq4019-mdio "#address-cells": @@ -30,19 +32,71 @@ properties: reg: minItems: 1 - maxItems: 2 + maxItems: 5 description: - the first Address and length of the register set for the MDIO controller. - the second Address and length of the register for ethernet LDO, this second - address range is only required by the platform IPQ50xx. + the first Address and length of the register set for the MDIO controller, + the optional second, third and fourth address and length of the register + for ethernet LDO, these three address range are required by the platform + IPQ50xx/IPQ5332/IPQ9574, the last address and length is for the CMN clock + to select the reference clock. + + reg-names: + minItems: 1 + maxItems: 5 clocks: + minItems: 1 items: - description: MDIO clock source frequency fixed to 100MHZ + - description: UNIPHY0 AHB clock source frequency fixed to 100MHZ + - description: UNIPHY1 AHB clock source frequency fixed to 100MHZ + - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ + - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ clock-names: + minItems: 1 items: - const: gcc_mdio_ahb_clk + - const: gcc_uniphy0_ahb_clk + - const: gcc_uniphy1_ahb_clk + - const: gcc_uniphy0_sys_clk + - const: gcc_uniphy1_sys_clk + + cmn-reference-clock: + oneOf: + - items: + - enum: + - 0 # CMN PLL reference internal 48MHZ + - 1 # CMN PLL reference external 25MHZ + - 2 # CMN PLL reference external 31250KHZ + - 3 # CMN PLL reference external 40MHZ + - 4 # CMN PLL reference external 48MHZ + - 5 # CMN PLL reference external 50MHZ + - 6 # CMN PLL reference internal 96MHZ + + clock-frequency: + oneOf: + - items: + - enum: + - 12500000 + - 6250000 + - 3125000 + - 1562500 + - 781250 + - 390625 + description: + The MDIO bus clock that must be output by the MDIO bus hardware, + only the listed frequecies above can be configured, other frequency + will cause malfunction. If absent, the default hardware value is used. + + reset-gpios: + maxItems: 1 + + reset-assert-us: + maxItems: 1 + + reset-deassert-us: + maxItems: 1 required: - compatible @@ -61,6 +115,8 @@ allOf: - qcom,ipq5018-mdio - qcom,ipq6018-mdio - qcom,ipq8074-mdio + - qcom,ipq5332-mdio + - qcom,ipq9574-mdio then: required: - clocks @@ -70,6 +126,40 @@ allOf: clocks: false clock-names: false + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-mdio + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + reg-names: + items: + - const: mdio + - const: eth_ldo1 + - const: eth_ldo2 + - const: cmn_blk + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-mdio + then: + properties: + reg-names: + items: + - const: mdio + - const: eth_ldo1 + - const: eth_ldo2 + - const: eth_ldo3 + - const: cmn_blk + unevaluatedProperties: false examples: @@ -100,3 +190,62 @@ examples: reg = <4>; }; }; + + - | + #include + #include + + mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq5332-mdio", + "qcom,ipq4019-mdio"; + cmn-reference-clock = <0>; + clock-frequency = <6250000>; + + reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + + reg = <0x90000 0x64>, + <0x7A00610 0x4>, + <0x7A10610 0x4>, + <0x9B000 0x800>; + + reg-names = "mdio", + "eth_ldo1", + "eth_ldo2", + "cmn_blk"; + + clocks = <&gcc GCC_MDIO_AHB_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>; + + clock-names = "gcc_mdio_ahb_clk", + "gcc_uniphy0_ahb_clk", + "gcc_uniphy1_ahb_clk", + "gcc_uniphy0_sys_clk", + "gcc_uniphy1_sys_clk"; + + qca8kphy0: ethernet-phy@1 { + compatible = "ethernet-phy-id004d.d180"; + reg = <1>; + }; + + qca8kphy1: ethernet-phy@2 { + compatible = "ethernet-phy-id004d.d180"; + reg = <2>; + }; + + qca8kphy2: ethernet-phy@3 { + compatible = "ethernet-phy-id004d.d180"; + reg = <3>; + }; + + qca8kphy3: ethernet-phy@4 { + compatible = "ethernet-phy-id004d.d180"; + reg = <4>; + }; + };