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Mon, 11 Dec 2023 16:53:11 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Dec 2023 16:53:07 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Dec 2023 16:53:06 +0800 From: Jianjun Wang To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Marc Zyngier CC: Ryder Lee , Jianjun Wang , , , , , , , , , Subject: [PATCH v2 1/3] PCI: mediatek: Allocate MSI address with dmam_alloc_coherent() Date: Mon, 11 Dec 2023 16:52:54 +0800 Message-ID: <20231211085256.31292-2-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211085256.31292-1-jianjun.wang@mediatek.com> References: <20231211085256.31292-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.452000-8.000000 X-TMASE-MatchedRID: YlUeb+P3LGlBHBd/Q+ztBwPZZctd3P4BIaVkFIrQFhtb6PBUqmq+UlYu mEk/UtlHxvP5MvmYpyBTc0C6OSQvz8pFJHzzp4rS58dk5sbwmyjGYnoF/CTeZVSOymiJfTYXlwW f7/4SyDtrg8FCypqvfGmevJVqJe6AHxPMjOKY7A8LbigRnpKlKZvjAepGmdoOjSE7r38ccucfAi JtYJYn7WCx0B/Tk9JmY616mIENddzqpQj72dAQYgHduAz87L4zdUVIHoasg2idNYuO1rAFqL0we Uq5YYes8jae4OD13tAV7Mc+rowcVKtX/F0pBwVJjSV5hDFby7ZnIxZyJs78kg== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.452000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 3399B1CCA37B4999E57B22197D5592ECC7DE562E04091DEA609953BF1EF284B22000:8 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 11 Dec 2023 00:53:35 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784974996627304757 X-GMAIL-MSGID: 1784975003096113812 Use dmam_alloc_coherent() to allocate the MSI address, instead of using virt_to_phys(). Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 66a8f73296fc..2fb9e44369f8 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -178,6 +178,7 @@ struct mtk_pcie_soc { * @phy: pointer to PHY control block * @slot: port slot * @irq: GIC irq + * @msg_addr: MSI message address * @irq_domain: legacy INTx IRQ domain * @inner_domain: inner IRQ domain * @msi_domain: MSI IRQ domain @@ -198,6 +199,7 @@ struct mtk_pcie_port { struct phy *phy; u32 slot; int irq; + dma_addr_t msg_addr; struct irq_domain *irq_domain; struct irq_domain *inner_domain; struct irq_domain *msi_domain; @@ -394,12 +396,10 @@ static struct pci_ops mtk_pcie_ops_v2 = { static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); - phys_addr_t addr; /* MT2712/MT7622 only support 32-bit MSI addresses */ - addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); msg->address_hi = 0; - msg->address_lo = lower_32_bits(addr); + msg->address_lo = lower_32_bits(port->msg_addr); msg->data = data->hwirq; @@ -494,6 +494,14 @@ static struct msi_domain_info mtk_msi_domain_info = { static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) { struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node); + void *msi_vaddr; + + msi_vaddr = dmam_alloc_coherent(port->pcie->dev, sizeof(dma_addr_t), &port->msg_addr, + GFP_KERNEL); + if (!msi_vaddr) { + dev_err(port->pcie->dev, "failed to alloc and map MSI address\n"); + return -ENOMEM; + } mutex_init(&port->lock); @@ -501,6 +509,7 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) &msi_domain_ops, port); if (!port->inner_domain) { dev_err(port->pcie->dev, "failed to create IRQ domain\n"); + dmam_free_coherent(port->pcie->dev, sizeof(dma_addr_t), msi_vaddr, port->msg_addr); return -ENOMEM; } @@ -508,6 +517,7 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) port->inner_domain); if (!port->msi_domain) { dev_err(port->pcie->dev, "failed to create MSI domain\n"); + dmam_free_coherent(port->pcie->dev, sizeof(dma_addr_t), msi_vaddr, port->msg_addr); irq_domain_remove(port->inner_domain); return -ENOMEM; } @@ -518,10 +528,8 @@ static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) { u32 val; - phys_addr_t msg_addr; - msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); - val = lower_32_bits(msg_addr); + val = lower_32_bits(port->msg_addr); writel(val, port->base + PCIE_IMSI_ADDR); val = readl(port->base + PCIE_INT_MASK); @@ -588,7 +596,7 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, if (IS_ENABLED(CONFIG_PCI_MSI)) { ret = mtk_pcie_allocate_msi_domains(port); if (ret) - return ret; + dev_warn(dev, "no MSI supported, only INTx available\n"); } return 0; @@ -732,7 +740,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) val &= ~INTX_MASK; writel(val, port->base + PCIE_INT_MASK); - if (IS_ENABLED(CONFIG_PCI_MSI)) + if (IS_ENABLED(CONFIG_PCI_MSI) && port->msi_domain) mtk_pcie_enable_msi(port); /* Set AHB to PCIe translation windows */ From patchwork Mon Dec 11 08:52:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 176537 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp6910453vqy; Mon, 11 Dec 2023 00:53:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IEiqyN72d8APMYtul7sAlPAe423h8jZfIFOa3lfP4NTdweBOfrlNSPK4lmKLmhNt2vS6t2w X-Received: by 2002:a17:902:bd98:b0:1d0:cda5:d05f with SMTP id q24-20020a170902bd9800b001d0cda5d05fmr1786939pls.83.1702284822090; Mon, 11 Dec 2023 00:53:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702284822; cv=none; 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[23.128.96.34]) by mx.google.com with ESMTPS id f1-20020a17090274c100b001cf5d073fa7si5820039plt.119.2023.12.11.00.53.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 00:53:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="r/uI4m4y"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 859F380A30AD; Mon, 11 Dec 2023 00:53:35 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230319AbjLKIxO (ORCPT + 99 others); Mon, 11 Dec 2023 03:53:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229654AbjLKIxN (ORCPT ); Mon, 11 Dec 2023 03:53:13 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2864CB6; Mon, 11 Dec 2023 00:53:15 -0800 (PST) X-UUID: b59a0048980211eeba30773df0976c77-20231211 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=omy/CemmEUqSfeI9bxjlTEDAt4GSH2fXIlmTOehEny0=; b=r/uI4m4y31cm/DQL/G7EaZcYapkapFR1NvY6fdVdL1hg1QxT7ISKVjH3Mwerye2NlobmkWYNxz0t5ZiWfGDMPDQjWl59FfiDXvhwAi9QdvT9Fz9iMUX88DWvmNsLQOZAGDLWcRmD8PllP4fcdpgZST1p69kWMmnuM9eoEqu2AIU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35,REQID:905a9014-0ce8-4193-b0fd-d79632fd3fef,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5d391d7,CLOUDID:40700e61-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: b59a0048980211eeba30773df0976c77-20231211 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 870822705; Mon, 11 Dec 2023 16:53:09 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Dec 2023 16:53:08 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Dec 2023 16:53:07 +0800 From: Jianjun Wang To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Matthias Brugger , AngeloGioacchino Del Regno , Marc Zyngier CC: Ryder Lee , Jianjun Wang , , , , , , , , , Subject: [PATCH v2 2/3] PCI: mediatek-gen3: Do not break probe flow when MSI init fails Date: Mon, 11 Dec 2023 16:52:55 +0800 Message-ID: <20231211085256.31292-3-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211085256.31292-1-jianjun.wang@mediatek.com> References: <20231211085256.31292-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 11 Dec 2023 00:53:35 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784975009766112382 X-GMAIL-MSGID: 1784975009766112382 Since INTx can still work, the driver probe flow should not be broken by MSI initialization failures. Additionally, moving the MSI initialization code into a single function enhances readability. Fixes: 1bdafba538be ("PCI: mediatek-gen3: Add MSI support") Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek-gen3.c | 68 ++++++++++----------- 1 file changed, 33 insertions(+), 35 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index c1ae3d19ec9a..c6a6876d233a 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -649,59 +649,51 @@ static const struct irq_domain_ops intx_domain_ops = { .map = mtk_pcie_intx_map, }; -static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie) +static int mtk_pcie_init_msi(struct mtk_gen3_pcie *pcie) { struct device *dev = pcie->dev; - struct device_node *intc_node, *node = dev->of_node; - int ret; - - raw_spin_lock_init(&pcie->irq_lock); - - /* Setup INTx */ - intc_node = of_get_child_by_name(node, "interrupt-controller"); - if (!intc_node) { - dev_err(dev, "missing interrupt-controller node\n"); - return -ENODEV; - } - - pcie->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX, - &intx_domain_ops, pcie); - if (!pcie->intx_domain) { - dev_err(dev, "failed to create INTx IRQ domain\n"); - ret = -ENODEV; - goto out_put_node; - } + struct device_node *node = dev->of_node; - /* Setup MSI */ mutex_init(&pcie->lock); pcie->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM, &mtk_msi_bottom_domain_ops, pcie); if (!pcie->msi_bottom_domain) { dev_err(dev, "failed to create MSI bottom domain\n"); - ret = -ENODEV; - goto err_msi_bottom_domain; + return -ENODEV; } - pcie->msi_domain = pci_msi_create_irq_domain(dev->fwnode, - &mtk_msi_domain_info, + pcie->msi_domain = pci_msi_create_irq_domain(dev->fwnode, &mtk_msi_domain_info, pcie->msi_bottom_domain); if (!pcie->msi_domain) { dev_err(dev, "failed to create MSI domain\n"); - ret = -ENODEV; - goto err_msi_domain; + irq_domain_remove(pcie->msi_bottom_domain); + return -ENODEV; } - of_node_put(intc_node); return 0; +} -err_msi_domain: - irq_domain_remove(pcie->msi_bottom_domain); -err_msi_bottom_domain: - irq_domain_remove(pcie->intx_domain); -out_put_node: +static int mtk_pcie_init_intx(struct mtk_gen3_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct device_node *intc_node, *node = dev->of_node; + + intc_node = of_get_child_by_name(node, "interrupt-controller"); + if (!intc_node) { + dev_err(dev, "missing interrupt-controller node\n"); + return -ENODEV; + } + + pcie->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX, + &intx_domain_ops, pcie); of_node_put(intc_node); - return ret; + if (!pcie->intx_domain) { + dev_err(dev, "failed to create INTx IRQ domain\n"); + return -ENODEV; + } + + return 0; } static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie) @@ -774,10 +766,16 @@ static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie) struct platform_device *pdev = to_platform_device(dev); int err; - err = mtk_pcie_init_irq_domains(pcie); + raw_spin_lock_init(&pcie->irq_lock); + + err = mtk_pcie_init_intx(pcie); if (err) return err; + err = mtk_pcie_init_msi(pcie); + if (err) + dev_warn(dev, "no MSI supported, only INTx available\n"); + pcie->irq = platform_get_irq(pdev, 0); if (pcie->irq < 0) return pcie->irq; From patchwork Mon Dec 11 08:52:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 176535 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp6910388vqy; Mon, 11 Dec 2023 00:53:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IGco8jtJJ08i9xiAMHdcVN24lDafLZy9ut9O00oFmCIB7vx03yM4KPdr0uLUoewJ1g+d2Kn X-Received: by 2002:a05:6a00:a85:b0:6ce:2731:c23e with SMTP id b5-20020a056a000a8500b006ce2731c23emr1712749pfl.45.1702284811185; Mon, 11 Dec 2023 00:53:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702284811; cv=none; d=google.com; s=arc-20160816; b=HAcfch/z2BE+9bfsmZmG8KOknbmTpnqmLtBuzhfQe4YFHznpou8h6IsYpv0trydlNz BY/6TMAfuqvCYcl2mPaunski64A/j3Hwxp0IcSY23j1942V+tYcGtMTRBz1ES/U6pp33 RliVvS3P0VAfvgyC/iW6Eo592pBOKc5LTs/dcyRzdJAmuhKtFtBosXdddZl7A1Ivo7go kygD5RayCVfIIiO2FIsaB+zLMQdiNQm67Cb7nbPFYVq0hXKP8Kinvjsv5YcS1ZWJg45n 9gesCx/rPsRU6m4WFiX9hRnipUWOE1LdTt530z4byzz64yO2S2Ot5dEBT1SIOc9nAO4l FXjg== ARC-Message-Signature: i=1; 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Signed-off-by: Jianjun Wang --- drivers/pci/controller/pcie-mediatek-gen3.c | 72 ++++++++++++--------- 1 file changed, 41 insertions(+), 31 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index c6a6876d233a..7cfd7ef9ad95 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -120,7 +120,6 @@ struct mtk_msi_set { * struct mtk_gen3_pcie - PCIe port information * @dev: pointer to PCIe device * @base: IO mapped register base - * @reg_base: physical register base * @mac_reset: MAC reset control * @phy_reset: PHY reset control * @phy: PHY controller block @@ -139,7 +138,6 @@ struct mtk_msi_set { struct mtk_gen3_pcie { struct device *dev; void __iomem *base; - phys_addr_t reg_base; struct reset_control *mac_reset; struct reset_control *phy_reset; struct phy *phy; @@ -309,24 +307,8 @@ static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie) { - int i; u32 val; - for (i = 0; i < PCIE_MSI_SET_NUM; i++) { - struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; - - msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG + - i * PCIE_MSI_SET_OFFSET; - msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG + - i * PCIE_MSI_SET_OFFSET; - - /* Configure the MSI capture address */ - writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); - writel_relaxed(upper_32_bits(msi_set->msg_addr), - pcie->base + PCIE_MSI_SET_ADDR_HI_BASE + - i * PCIE_MSI_SET_ADDR_HI_OFFSET); - } - val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG); val |= PCIE_MSI_SET_ENABLE; writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG); @@ -653,6 +635,29 @@ static int mtk_pcie_init_msi(struct mtk_gen3_pcie *pcie) { struct device *dev = pcie->dev; struct device_node *node = dev->of_node; + struct mtk_msi_set *msi_set; + void *msg_vaddr[PCIE_MSI_SET_NUM]; + int i, j, ret = -ENODEV; + + for (i = 0; i < PCIE_MSI_SET_NUM; i++) { + msi_set = &pcie->msi_sets[i]; + + msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG + + i * PCIE_MSI_SET_OFFSET; + + msg_vaddr[i] = dmam_alloc_coherent(dev, sizeof(dma_addr_t), + &msi_set->msg_addr, GFP_KERNEL); + if (!msg_vaddr[i]) { + dev_err(dev, "failed to alloc and map MSI address for set %d\n", i); + ret = -ENOMEM; + goto err_alloc_addr; + } + + /* Configure the MSI capture address */ + writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); + writel_relaxed(upper_32_bits(msi_set->msg_addr), pcie->base + + PCIE_MSI_SET_ADDR_HI_BASE + i * PCIE_MSI_SET_ADDR_HI_OFFSET); + } mutex_init(&pcie->lock); @@ -660,18 +665,24 @@ static int mtk_pcie_init_msi(struct mtk_gen3_pcie *pcie) &mtk_msi_bottom_domain_ops, pcie); if (!pcie->msi_bottom_domain) { dev_err(dev, "failed to create MSI bottom domain\n"); - return -ENODEV; + goto err_alloc_addr; } pcie->msi_domain = pci_msi_create_irq_domain(dev->fwnode, &mtk_msi_domain_info, pcie->msi_bottom_domain); - if (!pcie->msi_domain) { - dev_err(dev, "failed to create MSI domain\n"); - irq_domain_remove(pcie->msi_bottom_domain); - return -ENODEV; + if (pcie->msi_domain) + return 0; + + dev_err(dev, "failed to create MSI domain\n"); + irq_domain_remove(pcie->msi_bottom_domain); + +err_alloc_addr: + for (j = 0; j < i; j++) { + msi_set = &pcie->msi_sets[j]; + dmam_free_coherent(dev, sizeof(dma_addr_t), msg_vaddr[j], msi_set->msg_addr); } - return 0; + return ret; } static int mtk_pcie_init_intx(struct mtk_gen3_pcie *pcie) @@ -789,20 +800,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) { struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); - struct resource *regs; int ret; - regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); - if (!regs) - return -EINVAL; - pcie->base = devm_ioremap_resource(dev, regs); + pcie->base = devm_platform_ioremap_resource_byname(pdev, "pcie-mac"); if (IS_ERR(pcie->base)) { dev_err(dev, "failed to map register base\n"); return PTR_ERR(pcie->base); } - pcie->reg_base = regs->start; - pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy"); if (IS_ERR(pcie->phy_reset)) { ret = PTR_ERR(pcie->phy_reset); @@ -1013,6 +1018,11 @@ static void mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie) for (i = 0; i < PCIE_MSI_SET_NUM; i++) { struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; + /* Configure the MSI capture address */ + writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); + writel_relaxed(upper_32_bits(msi_set->msg_addr), pcie->base + + PCIE_MSI_SET_ADDR_HI_BASE + i * PCIE_MSI_SET_ADDR_HI_OFFSET); + writel_relaxed(msi_set->saved_irq_state, msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET); }