From patchwork Mon Dec 11 05:37:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: guanjun X-Patchwork-Id: 176477 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp6846725vqy; Sun, 10 Dec 2023 21:37:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IH3tMXgr+WeAZScuwmXZWnE0qWVsCOzjbV9G3qy96sFUULkDjh+Gu6CLs2hJv3b2t+UIjAF X-Received: by 2002:a05:6358:728e:b0:170:3ef2:de12 with SMTP id w14-20020a056358728e00b001703ef2de12mr2008719rwf.46.1702273060920; Sun, 10 Dec 2023 21:37:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702273060; cv=none; d=google.com; s=arc-20160816; b=x38A2icQugMZgrBK/jBn+u42gwsNvJ3shT/vVIUl5CRDd/0Izb0Q//xWBaht8bQ0dN SBQJfnRSDwWfRsFhbK2hLve8Oc+1OsPbgZKdr6fbanxbPLN89WL9g0ai+f31nBiUxjVF xcIPyvbYmQHCoTbncww5Y1cBmBD/iE2QDKCKdF4QIq2oqVf48GefDaSwj0C9HyOpvAwl kcvMI6+lz63s5NtmZp20kLuTJtx785i6sdXRunMch2hqspRP59SGD3qMjG3Na6Vg8Bb0 mAeV3xwF8OQArHywQqFk19hgNAlhBqI59dzm7zd81gRCnFf82+EDwtVg2kY0z48i9DeI J+nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=wuUeDzihsMlOuIze9L8RV3iAbLA1n59qid+K6LWXfA0=; fh=un7dZAZp9pSkRKfeT5a2d+I0o7/mCh6YSrYzyba6bng=; b=liJoJWl+E4zOumGdAyN23m800ll4KugqRRqviTs1GkqlJqMMdP1//uYL4L30rsesul MCZt3tReJoHLcbKFweWzh9aDJsrmkis1nXbvQTdZNu2eX1ZfuUr4ou/E19D7paw+PZqQ CBzSOjT/HqZRGYIfiTfO/6c+Zr4XB6o1+hTpSe6ztebAnrcDeuxcV2Lqss7P0I3Nvjny dDaLhQQw8BiBUpiYTAlMj0c6XsVt0+F6uW9P2aCBuYoWrSE/qYUOUgyPrQDswxUQZKxn MdD7fFucpchXHj2LsHLUya87yhDB6jqqQyiMX/O/dLYslbdRItecwksMydE0buPVjP6J HJsw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id n15-20020a170903110f00b001d0891f986asi5602978plh.525.2023.12.10.21.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Dec 2023 21:37:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 2FE0880A1D8E; Sun, 10 Dec 2023 21:37:38 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233244AbjLKFhJ (ORCPT + 99 others); Mon, 11 Dec 2023 00:37:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233080AbjLKFhE (ORCPT ); Mon, 11 Dec 2023 00:37:04 -0500 Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39BC5ED; Sun, 10 Dec 2023 21:37:10 -0800 (PST) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R111e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046051;MF=guanjun@linux.alibaba.com;NM=1;PH=DS;RN=14;SR=0;TI=SMTPD_---0VyB1LNZ_1702273027; Received: from localhost(mailfrom:guanjun@linux.alibaba.com fp:SMTPD_---0VyB1LNZ_1702273027) by smtp.aliyun-inc.com; Mon, 11 Dec 2023 13:37:07 +0800 From: 'Guanjun' To: dave.jiang@intel.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, tony.luck@intel.com, fenghua.yu@intel.com Cc: jing.lin@intel.com, ashok.raj@intel.com, sanjay.k.kumar@intel.com, megha.dey@intel.com, jacob.jun.pan@intel.com, yi.l.liu@intel.com, tglx@linutronix.de, guanjun@linux.alibaba.com Subject: [PATCH v5 2/2] dmaengine: idxd: Fix incorrect descriptions for GRPCFG register Date: Mon, 11 Dec 2023 13:37:04 +0800 Message-Id: <20231211053704.2725417-3-guanjun@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20231211053704.2725417-1-guanjun@linux.alibaba.com> References: <20231211053704.2725417-1-guanjun@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Sun, 10 Dec 2023 21:37:38 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784962677290080065 X-GMAIL-MSGID: 1784962677290080065 From: Guanjun Fix incorrect descriptions for the GRPCFG register which has three sub-registers (GRPWQCFG, GRPENGCFG and GRPFLGCFG). No functional changes Signed-off-by: Guanjun Reviewed-by: Dave Jiang Reviewed-by: Fenghua Yu Acked-by: Lijun Pan --- drivers/dma/idxd/registers.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h index 7b54a3939ea1..315c004f58e4 100644 --- a/drivers/dma/idxd/registers.h +++ b/drivers/dma/idxd/registers.h @@ -440,12 +440,14 @@ union wqcfg { /* * This macro calculates the offset into the GRPCFG register * idxd - struct idxd * - * n - wq id - * ofs - the index of the 32b dword for the config register + * n - group id + * ofs - the index of the 64b qword for the config register * - * The WQCFG register block is divided into groups per each wq. The n index - * allows us to move to the register group that's for that particular wq. - * Each register is 32bits. The ofs gives us the number of register to access. + * The GRPCFG register block is divided into three sub-registers, which + * are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index allows us to move + * to the register block that contains the three sub-registers. + * Each register block is 64bits. And the ofs gives us the offset + * within the GRPWQCFG register to access. */ #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ (n) * GRPCFG_SIZE + sizeof(u64) * (ofs))