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[8.43.85.97]) by mx.google.com with ESMTPS id i1-20020ac813c1000000b00423eedcfeddsi3530213qtj.474.2023.12.09.00.33.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Dec 2023 00:33:12 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BE54B3858412 for ; Sat, 9 Dec 2023 08:33:11 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id DE82D3858CDB for ; Sat, 9 Dec 2023 08:32:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DE82D3858CDB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DE82D3858CDB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=13.245.218.24 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702110737; cv=none; b=B4ZHYdHMeOo3hev2O/18SjoMsX5sK6cWAfXsKJEaD3qde/5gyg4KCKJkGTlOKPbpayi1PQ98Uqait2Nc8/eEj/Zew5FkR+DwsAiD3PIQQF1+mpLD7R0g2bS5pYiQuv+3m5wL6IcOKJ07lFlnqw76jrjrM0WuaeEjYPTIxtXbyt0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702110737; c=relaxed/simple; bh=Pdhr8nLJQbTVeMmxZZTOIMnsIdXYQsZIgqsNN6Vlr3Q=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=LcxlV4bo91+68O7qBJg0P3liKRH5eKnfuoI2aXYMENzl2iUnGVuO5CHzb1sLnxezPz6Yg/6I6xjR+jVCCFcY1M1ttgRD+iOVlBZmGinGD4Bi4lLdnagiAdfAsJMGgc1XaEoLABzzD1Wo1eLRoaYrpS3T5M6RXL9CDJsG2nZZwwE= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp66t1702110715tm8nsihv Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 09 Dec 2023 16:31:54 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: Pbidb3+knnHEEyc3sP7Tb+4MQGA6YCRKY3fyoVa5YdU+aHzOrOImd+cQsHC/4 /j1z4Y9sIsDy6NOgNAdolw6LJR+XoHtpG2mGHmu6+2gaaOF33J7xQYKLafeR0K/rVS/vpY1 RDkcyTVC3kGstuB2J7FXo0b5GgpoAdEoaMfoIpFQaHzrOkWDPlrS+oZ8cujvl/HV5owYMLc xIeobKEHYAENreVn2l6kQAc/htlZJFfa1BatM/WxlW8k4KSlRChBdCzEWRfEqMrotVFoLd4 Coy0teN0KbhU5R9beuDTmME6WFte6U3qtnZWlO8W/AdJzl6BNxCjW+Qu24DF8e8iqJquVCd a+t4Sv5PIueJH/13OjjxjbtzTrOHBLRow9zEnI/s1DfKFid3JVoRtkwVPgktJaYPJUZsDGw 7LNgjPDOlY2mlo6fqwQ18g== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 14559128453214869203 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Fix VLS mode movmiaslign bug Date: Sat, 9 Dec 2023 16:31:53 +0800 Message-Id: <20231209083153.1131680-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784792525927817829 X-GMAIL-MSGID: 1784792525927817829 PR112932 let me notice there is a bug of current VLS mode misalign pattern. Adapt it same as VLA mode. Commited as it is obvious fix. PR target/112932 gcc/ChangeLog: * config/riscv/vector.md (movmisalign): Fix VLSmode bugs. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/misalign-1.c: Ditto. * gcc.target/riscv/rvv/autovec/pr112932.c: New test. --- gcc/config/riscv/vector.md | 23 +------ .../gcc.target/riscv/rvv/autovec/pr112932.c | 66 +++++++++++++++++++ .../riscv/rvv/autovec/vls/misalign-1.c | 6 +- 3 files changed, 70 insertions(+), 25 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112932.c diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 31c13a6dcca..a1284fd3251 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1334,31 +1334,12 @@ [(set_attr "type" "vmov") (set_attr "mode" "")]) -(define_expand "movmisalign" - [(set (match_operand:VLS 0 "nonimmediate_operand") - (match_operand:VLS 1 "general_operand"))] - "TARGET_VECTOR" - { - /* To support misalign data movement, we should use - minimum element alignment load/store. */ - unsigned int size = GET_MODE_SIZE (GET_MODE_INNER (mode)); - poly_int64 nunits = GET_MODE_NUNITS (mode) * size; - machine_mode mode = riscv_vector::get_vector_mode (QImode, nunits).require (); - operands[0] = gen_lowpart (mode, operands[0]); - operands[1] = gen_lowpart (mode, operands[1]); - if (MEM_P (operands[0]) && !register_operand (operands[1], mode)) - operands[1] = force_reg (mode, operands[1]); - riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::UNARY_OP, operands); - DONE; - } -) - ;; According to RVV ISA: ;; If an element accessed by a vector memory instruction is not naturally aligned to the size of the element, ;; either the element is transferred successfully or an address misaligned exception is raised on that element. (define_expand "movmisalign" - [(set (match_operand:V 0 "nonimmediate_operand") - (match_operand:V 1 "general_operand"))] + [(set (match_operand:V_VLS 0 "nonimmediate_operand") + (match_operand:V_VLS 1 "general_operand"))] "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED" { emit_move_insn (operands[0], operands[1]); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112932.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112932.c new file mode 100644 index 00000000000..4ae6ec02817 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112932.c @@ -0,0 +1,66 @@ +/* { dg-do run } */ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target riscv_v } */ + +#include +int a, j, n, b, c, o, d, g, h; +int e[8]; +long f[8][6]; +void l() { + o = -27; + for (; o; o++) { + *e = 1; + if (a >= n) { + d = 0; + for (; d <= 7; d++) + e[d] = c; + } + } + j = 0; + for (; j < 8; j++) { + g = 0; + for (; g < 2; g++) { + h = 1; + for (; h < 3; h++) + f[j][g * 2 + h] = 1; + } + } + unsigned long *m = &f[1][1]; + *m = 0; +} +int main() { + l(); + assert (f[0][1] == 1); + assert (f[0][2] == 1); + assert (f[0][3] == 1); + assert (f[0][4] == 1); + assert (f[1][1] == 0); + assert (f[1][2] == 1); + assert (f[1][3] == 1); + assert (f[1][4] == 1); + assert (f[2][1] == 1); + assert (f[2][2] == 1); + assert (f[2][3] == 1); + assert (f[2][4] == 1); + assert (f[3][1] == 1); + assert (f[3][2] == 1); + assert (f[3][3] == 1); + assert (f[3][4] == 1); + assert (f[4][1] == 1); + assert (f[4][2] == 1); + assert (f[4][3] == 1); + assert (f[4][4] == 1); + assert (f[5][1] == 1); + assert (f[5][2] == 1); + assert (f[5][3] == 1); + assert (f[5][4] == 1); + assert (f[6][1] == 1); + assert (f[6][2] == 1); + assert (f[6][3] == 1); + assert (f[6][4] == 1); + assert (f[7][1] == 1); + assert (f[7][2] == 1); + assert (f[7][3] == 1); + assert (f[7][4] == 1); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c index b602ffd69bb..6e08f77921a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c @@ -21,7 +21,5 @@ foo () abort (); } -/* { dg-final { scan-assembler-times {vle8\.v} 1 } } */ -/* { dg-final { scan-assembler-times {vle8\.v} 1 } } */ -/* { dg-final { scan-assembler-not {vle16\.v} } } */ -/* { dg-final { scan-assembler-not {vle16\.v} } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 } } */ +