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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id m9-20020a170902db0900b001ce5b8081a5si2114805plx.382.2023.12.08.13.16.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 13:16:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=r4FSgYnO; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id BA25680713C7; Fri, 8 Dec 2023 13:15:20 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1574821AbjLHVPB (ORCPT + 99 others); Fri, 8 Dec 2023 16:15:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1574778AbjLHVOi (ORCPT ); Fri, 8 Dec 2023 16:14:38 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAEC11987; Fri, 8 Dec 2023 13:14:44 -0800 (PST) Date: Fri, 08 Dec 2023 21:14:41 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1702070082; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1gSKYTErsZLP4N632RCFVD1tDI+fX4Wvt9FsdBYZNDI=; b=r4FSgYnOh+b2ChBeH35iwDkcbElsHJ6BhIKgjPjQN7hpAF2mxsjg11MFaJT+KzJ1uFhZvG NFgOEzsyH1B626tgDABMp/VRpv5X5grgn8JuqWYiCJ0LRUtDjjSdJGTQXc81dtSICRSYej BuDBAKHfq21iucC59ih34eM+YztldArCRfkBFt0sJIfYvW7+jzJ63EhucZ7l8UfJESMTsW d2rqPNhP1ymOanV8P3P8B2zyanHvcRZz2I4sIv5yegnVYMUCY/Bc7KScuSfuLXR+jfrdNG 5mBEl8Hni4hnQWmEZH7S/DaeIhnNO2knN6rukr9grx71o+9ZimOo/QHEhEFW2A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1702070082; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1gSKYTErsZLP4N632RCFVD1tDI+fX4Wvt9FsdBYZNDI=; b=nNV3ZB9RkHctXkf1DgVC3hab3WjZYla1UcosCdu9f2uElztxtjfgNbBTuSKet11UR00Oyu DdhAscFEZFwKK3DA== From: "tip-bot2 for Claudiu Beznea" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Cc: Claudiu Beznea , Thomas Gleixner , Geert Uytterhoeven , x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org In-Reply-To: <20231120111820.87398-6-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-6-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Message-ID: <170207008170.398.9595361567170757306.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Fri, 08 Dec 2023 13:15:20 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783168343968771587 X-GMAIL-MSGID: 1784749935975225927 The following commit has been merged into the irq/core branch of tip: Commit-ID: 0b57d3bb1cc5da335fd4c7a4b1996e7015f4b5d5 Gitweb: https://git.kernel.org/tip/0b57d3bb1cc5da335fd4c7a4b1996e7015f4b5d5 Author: Claudiu Beznea AuthorDate: Mon, 20 Nov 2023 13:18:16 +02:00 Committer: Thomas Gleixner CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00 irqchip/renesas-rzg2l: Implement restriction when writing ISCR register The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes the operation to clear interrupts through the ISCR register as follows: [Write operation] When "Falling-edge detection", "Rising-edge detection" or "Falling/Rising-edge detection" is set in IITSR: - In case ISTAT is 1 0: IRQn interrupt detection status is cleared. 1: Invalid to write. - In case ISTAT is 0 Invalid to write. When "Low-level detection" is set in IITSR.: Invalid to write. Take the interrupt type into account when clearing interrupts through the ISCR register to avoid writing the ISCR when the interrupt type is level. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-6-claudiu.beznea.uj@bp.renesas.com --- drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 0a77927..d450417 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -78,11 +78,17 @@ static void rzg2l_irq_eoi(struct irq_data *d) unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 bit = BIT(hw_irq); - u32 reg; + u32 iitsr, iscr; - reg = readl_relaxed(priv->base + ISCR); - if (reg & bit) - writel_relaxed(reg & ~bit, priv->base + ISCR); + iscr = readl_relaxed(priv->base + ISCR); + iitsr = readl_relaxed(priv->base + IITSR); + + /* + * ISCR can only be cleared if the type is falling-edge, rising-edge or + * falling/rising-edge. + */ + if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) + writel_relaxed(iscr & ~bit, priv->base + ISCR); } static void rzg2l_tint_eoi(struct irq_data *d)