From patchwork Fri Dec 8 09:42:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 175699 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp5345232vqy; Fri, 8 Dec 2023 01:42:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IEB9CNbSi/IveVno/YmOrXDKQPitWwOd4N6yTwBgqG1nEGFowfIRkTXRALyMnA7QP/Rfl+2 X-Received: by 2002:a05:6a20:2449:b0:18a:f462:5d3c with SMTP id t9-20020a056a20244900b0018af4625d3cmr5102260pzc.12.1702028564621; Fri, 08 Dec 2023 01:42:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702028564; cv=none; d=google.com; s=arc-20160816; b=X/B0bM8lBlmi8CdO0qR6y1+UdqqpF44lPOJR8Otz4XOXaytk/3aK8Qd3OUzkA9D8ZP W6gkZPDoFPYQdz7xmVCeI7/Vn0mR20apHg75MmjCBXxcwJtEU271dGF6MY7ZOI8pohLU lZNQICxwmlziz4+Uvyat1G0L4qHvK4sSNGsV8npnUbtZy+oeymZ1QtYxWd0fCRR/uXpZ L41Bnsxral3+dSpLg/KZaGLVpGBi897sAyQLVhvSNi0Uo4bxL823HWJ05d2YGrZ1nvIo 6mLyKoVJQyGSGV0N5U25MIQC0rWpUBTITciqE3LzcawNWhxjW3wc8AeQqQTGDCK3o829 PUAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=t7d5tY/8c6rDcp6d+W2GH7KHCFZw04gekr1ZWYxbLpc=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=IMpqc8BTKtF9Y5GqpjQ+0lTclOF3mK4Drq2vnXO6bgUcwmR6QN/lqFly74WxydcM0h 1hGW01hSsNCUtKTpMhgU12C9KMuOZBQGInfeolhbFMeB+afuMsG9MaWmCIPxy+MRPDm1 BhDs3Mw//ZKkEAVKuYUP7B7ML1hRchln1jaNJUUXhLlALyxQ75qmNUvSe8LRbCYjyYew biM8v9JDYxUvQqQrVA+BZKl/OG9WLGvyMyaUexUsE597j0k46lkwM/Zc/e0U0yTbcngb 8wG/8/2M6VMZH7FGsMHOHjNURCrfZNV2n/JEv1Ksd39c0gmE0gXpQ85d6EE/iBqH2DPa 1hdA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id e5-20020a654785000000b005c1cd597808si1290529pgs.692.2023.12.08.01.42.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 01:42:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 685708794398; Fri, 8 Dec 2023 01:42:34 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233259AbjLHJmQ convert rfc822-to-8bit (ORCPT + 99 others); Fri, 8 Dec 2023 04:42:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231863AbjLHJmO (ORCPT ); Fri, 8 Dec 2023 04:42:14 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B16B8E; Fri, 8 Dec 2023 01:42:15 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 216B48022; Fri, 8 Dec 2023 17:42:12 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 8 Dec 2023 17:42:12 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 8 Dec 2023 17:42:10 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v9 1/4] dt-bindings: pwm: Add bindings for OpenCores PWM Controller Date: Fri, 8 Dec 2023 17:42:06 +0800 Message-ID: <20231208094209.1910934-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231208094209.1910934-1-william.qiu@starfivetech.com> References: <20231208094209.1910934-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Fri, 08 Dec 2023 01:42:34 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784706304280811552 X-GMAIL-MSGID: 1784706304280811552 Add bindings for OpenCores PWM Controller. Signed-off-by: William Qiu Reviewed-by: Hal Feng Reviewed-by: Conor Dooley --- .../bindings/pwm/opencores,pwm.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml new file mode 100644 index 000000000000..0b85dd861dfd --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OpenCores PWM controller + +maintainers: + - William Qiu + +description: + The OpenCores PTC ip core contains a PWM controller. When operating in PWM + mode, the PTC core generates binary signal with user-programmable low and + high periods. All PTC counters and registers are 32-bit. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + items: + - enum: + - starfive,jh7100-pwm + - starfive,jh7110-pwm + - const: opencores,pwm-v1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm@12490000 { + compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg = <0x12490000 0x10000>; + clocks = <&clkgen 181>; + resets = <&rstgen 109>; + #pwm-cells = <3>; + }; From patchwork Fri Dec 8 09:42:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 175698 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp5345209vqy; Fri, 8 Dec 2023 01:42:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IHunDSjqgIS1wW07oAM/ghxnQ13C4YqeRom4DR18EtBBAATj89CWGPlsYgI/enQjRSMKTS8 X-Received: by 2002:aa7:9830:0:b0:6ce:6cb5:fe81 with SMTP id q16-20020aa79830000000b006ce6cb5fe81mr4174914pfl.33.1702028559947; Fri, 08 Dec 2023 01:42:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702028559; cv=none; d=google.com; s=arc-20160816; b=IqFgYIfQCXpJNzoWSNihkIflKPy3lEMbGwXkvhqw9ZESWpm8yMWouY3NqOeyvBcQJf FWc2xPLQPYWkmLXphVOSzXPD9pHuo0GXNGJldQxr2RaordsqOxDzgNbZZ0X03wJT8Z03 QFms4BW4E6knmzan52/VQ+Cl7q+AZ8x2BKL+wD/su+RqlfpyUyOSeqBeS40YutIV3Qca s/uUntX8TcK2dwS8oTOjbl8UxwVqa1EyHUkJ8DpB2DuHgdyNdRDvqfmX1wUlQMmfftNW b/5IsM0N/RIjIqfMU0ZrHC+CUdN0GnGJpzRW1qSYNJr+SldK9Nj9/cEjXgPvLDbw8biy yAmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=wAuqgUcfvb+dtBRs0CiWf7feScFRKDZm1bzTTDp6+Xs=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=D7bmk2Pl0vmdHkMEeWsE4GIVAEVaeYXVQTLN/IMkinpmaWpRfOOzHBV5hHCkYgrdX/ MDQetoZpXzjLqMm9pWRMIIGzK7M/erGezqjlK5p2pw4TLV8QYHPCreUT0Ljmx7p517C/ qTljeUGp8oetAvvgPaeOBEmuT9SC6ByMMpMrg0LxlKE1fXjOrTytQw+oSII/o7sHGo5a DwuTVJY4/+SMNcVH9uT0Z948EPhbMVYaycsF0Zwnqa17O73JlHXi6U1hEdmWz/doR9oJ PQ+11l27zTPPOO86Glkr1Z/4xcG548XabHdmuVDiWT2Wwz3kPKhLQuT54glR58Rfx/Zv mAaA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id a17-20020a656411000000b005c692162984si1222763pgv.666.2023.12.08.01.42.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 01:42:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 1774D810FBD4; Fri, 8 Dec 2023 01:42:32 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235826AbjLHJmT convert rfc822-to-8bit (ORCPT + 99 others); Fri, 8 Dec 2023 04:42:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232968AbjLHJmO (ORCPT ); Fri, 8 Dec 2023 04:42:14 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B7A3171D; Fri, 8 Dec 2023 01:42:19 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 0A55424DCA6; Fri, 8 Dec 2023 17:42:13 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 8 Dec 2023 17:42:12 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 8 Dec 2023 17:42:11 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v9 2/4] pwm: opencores: Add PWM driver support Date: Fri, 8 Dec 2023 17:42:07 +0800 Message-ID: <20231208094209.1910934-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231208094209.1910934-1-william.qiu@starfivetech.com> References: <20231208094209.1910934-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Fri, 08 Dec 2023 01:42:32 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784706299244668311 X-GMAIL-MSGID: 1784706299244668311 Add driver for OpenCores PWM Controller. And add compatibility code which based on StarFive SoC. Co-developed-by: Hal Feng Signed-off-by: Hal Feng Signed-off-by: William Qiu --- MAINTAINERS | 7 ++ drivers/pwm/Kconfig | 12 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ocores.c | 229 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 249 insertions(+) create mode 100644 drivers/pwm/pwm-ocores.c diff --git a/MAINTAINERS b/MAINTAINERS index 788be9ab5b73..7a11a22da09e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16204,6 +16204,13 @@ F: Documentation/i2c/busses/i2c-ocores.rst F: drivers/i2c/busses/i2c-ocores.c F: include/linux/platform_data/i2c-ocores.h +OPENCORES PWM DRIVER +M: William Qiu +M: Hal Feng +S: Supported +F: Documentation/devicetree/bindings/pwm/opencores,pwm.yaml +F: drivers/pwm/pwm-ocores.c + OPENRISC ARCHITECTURE M: Jonas Bonn M: Stefan Kristiansson diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 4b956d661755..d87e1bb350ba 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -444,6 +444,18 @@ config PWM_NTXEC controller found in certain e-book readers designed by the original design manufacturer Netronix. +config PWM_OCORES + tristate "OpenCores PWM support" + depends on HAS_IOMEM && OF + depends on COMMON_CLK && RESET_CONTROLLER + depends on ARCH_STARFIVE || COMPILE_TEST + help + If you say yes to this option, support will be included for the + OpenCores PWM. For details see https://opencores.org/projects/ptc. + + To compile this driver as a module, choose M here: the module + will be called pwm-ocores. + config PWM_OMAP_DMTIMER tristate "OMAP Dual-Mode Timer PWM support" depends on OF diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c5ec9e168ee7..517c4f643058 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o obj-$(CONFIG_PWM_MXS) += pwm-mxs.o obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o +obj-$(CONFIG_PWM_OCORES) += pwm-ocores.o obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c new file mode 100644 index 000000000000..996ca3805901 --- /dev/null +++ b/drivers/pwm/pwm-ocores.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OpenCores PWM Driver + * + * https://opencores.org/projects/ptc + * + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd. + * + * Limitations: + * - The hardware only do inverted polarity. + * - The hardware minimum period / duty_cycle is (1 / pwm_apb clock frequency) ns. + * - The hardware maximum period / duty_cycle is (U32_MAX / pwm_apb clock frequency) ns. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* OCPWM_CTRL register bits*/ +#define REG_OCPWM_EN BIT(0) +#define REG_OCPWM_ECLK BIT(1) +#define REG_OCPWM_NEC BIT(2) +#define REG_OCPWM_OE BIT(3) +#define REG_OCPWM_SIGNLE BIT(4) +#define REG_OCPWM_INTE BIT(5) +#define REG_OCPWM_INT BIT(6) +#define REG_OCPWM_CNTRRST BIT(7) +#define REG_OCPWM_CAPTE BIT(8) + +struct ocores_pwm_device { + struct pwm_chip chip; + struct clk *clk; + struct reset_control *rst; + const struct ocores_pwm_data *data; + void __iomem *regs; + u32 clk_rate; /* PWM APB clock frequency */ +}; + +struct ocores_pwm_data { + void __iomem *(*get_ch_base)(void __iomem *base, unsigned int channel); +}; + +static inline u32 ocores_readl(struct ocores_pwm_device *ddata, + unsigned int channel, + unsigned int offset) +{ + void __iomem *base = ddata->data->get_ch_base ? + ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs; + + return readl(base + offset); +} + +static inline void ocores_writel(struct ocores_pwm_device *ddata, + unsigned int channel, + unsigned int offset, u32 val) +{ + void __iomem *base = ddata->data->get_ch_base ? + ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs; + + writel(val, base + offset); +} + +static inline struct ocores_pwm_device *chip_to_ocores(struct pwm_chip *chip) +{ + return container_of(chip, struct ocores_pwm_device, chip); +} + +static void __iomem *starfive_jh71x0_get_ch_base(void __iomem *base, + unsigned int channel) +{ + unsigned int offset = (channel > 3 ? 1 << 15 : 0) + (channel & 3) * 0x10; + + return base + offset; +} + +static int ocores_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct ocores_pwm_device *ddata = chip_to_ocores(chip); + u32 period_data, duty_data, ctrl_data; + + period_data = ocores_readl(ddata, pwm->hwpwm, 0x8); + duty_data = ocores_readl(ddata, pwm->hwpwm, 0x4); + ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC); + + state->period = DIV_ROUND_UP_ULL((u64)period_data * NSEC_PER_SEC, ddata->clk_rate); + state->duty_cycle = DIV_ROUND_UP_ULL((u64)duty_data * NSEC_PER_SEC, ddata->clk_rate); + state->polarity = PWM_POLARITY_INVERSED; + state->enabled = (ctrl_data & REG_OCPWM_EN) ? true : false; + + return 0; +} + +static int ocores_pwm_apply(struct pwm_chip *chip, + struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ocores_pwm_device *ddata = chip_to_ocores(chip); + u32 ctrl_data = 0; + u64 period_data, duty_data; + + if (state->polarity != PWM_POLARITY_INVERSED) + return -EINVAL; + + ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC); + ocores_writel(ddata, pwm->hwpwm, 0xC, 0); + + period_data = DIV_ROUND_DOWN_ULL(state->period * ddata->clk_rate, NSEC_PER_SEC); + if (period_data <= U32_MAX) + ocores_writel(ddata, pwm->hwpwm, 0x8, (u32)period_data); + else + return -EINVAL; + + duty_data = DIV_ROUND_DOWN_ULL(state->duty_cycle * ddata->clk_rate, NSEC_PER_SEC); + if (duty_data <= U32_MAX) + ocores_writel(ddata, pwm->hwpwm, 0x4, (u32)duty_data); + else + return -EINVAL; + + ocores_writel(ddata, pwm->hwpwm, 0xC, 0); + + if (state->enabled) { + ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC); + ocores_writel(ddata, pwm->hwpwm, 0xC, ctrl_data | REG_OCPWM_EN | REG_OCPWM_OE); + } + + return 0; +} + +static const struct pwm_ops ocores_pwm_ops = { + .get_state = ocores_pwm_get_state, + .apply = ocores_pwm_apply, +}; + +static const struct ocores_pwm_data jh7100_pwm_data = { + .get_ch_base = starfive_jh71x0_get_ch_base, +}; + +static const struct ocores_pwm_data jh7110_pwm_data = { + .get_ch_base = starfive_jh71x0_get_ch_base, +}; + +static const struct of_device_id ocores_pwm_of_match[] = { + { .compatible = "opencores,pwm-v1" }, + { .compatible = "starfive,jh7100-pwm", .data = &jh7100_pwm_data}, + { .compatible = "starfive,jh7110-pwm", .data = &jh7110_pwm_data}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ocores_pwm_of_match); + +static void ocores_reset_control_assert(void *data) +{ + reset_control_assert(data); +} + +static int ocores_pwm_probe(struct platform_device *pdev) +{ + const struct of_device_id *id; + struct device *dev = &pdev->dev; + struct ocores_pwm_device *ddata; + struct pwm_chip *chip; + int ret; + + id = of_match_device(ocores_pwm_of_match, dev); + if (!id) + return -EINVAL; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->data = id->data; + chip = &ddata->chip; + chip->dev = dev; + chip->ops = &ocores_pwm_ops; + chip->npwm = 8; + chip->of_pwm_n_cells = 3; + + ddata->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ddata->regs)) + return dev_err_probe(dev, PTR_ERR(ddata->regs), + "Unable to map IO resources\n"); + + ddata->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(ddata->clk)) + return dev_err_probe(dev, PTR_ERR(ddata->clk), + "Unable to get pwm's clock\n"); + + ddata->rst = devm_reset_control_get_optional_exclusive(dev, NULL); + reset_control_deassert(ddata->rst); + + ret = devm_add_action_or_reset(dev, ocores_reset_control_assert, ddata->rst); + if (ret) + return ret; + + ddata->clk_rate = clk_get_rate(ddata->clk); + if (ddata->clk_rate <= 0) + return dev_err_probe(dev, ddata->clk_rate, + "Unable to get clock's rate\n"); + + ret = devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Could not register PWM chip\n"); + + platform_set_drvdata(pdev, ddata); + + return ret; +} + +static struct platform_driver ocores_pwm_driver = { + .probe = ocores_pwm_probe, + .driver = { + .name = "ocores-pwm", + .of_match_table = ocores_pwm_of_match, + }, +}; +module_platform_driver(ocores_pwm_driver); + +MODULE_AUTHOR("Jieqin Chen"); +MODULE_AUTHOR("Hal Feng "); +MODULE_DESCRIPTION("OpenCores PWM PTC driver"); +MODULE_LICENSE("GPL");