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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00025F97.EURPRD83.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8930 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784638078442688978 X-GMAIL-MSGID: 1784638078442688978 From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vst1q intrinsic for the arm port. This patch adds the _x2 variants of the vst1q intrinsic. ACLE documents: https://developer.arm.com/documentation/ihi0053/latest/ ISA documents: https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New. (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New. (vst1q_f16_x2, vst1q_f32_x2): New. (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New. (vst1q_bf16_x2): New. * config/arm/arm_neon_builtins.def (vst1q_x2): New entries. * config/arm/neon.md (neon_vst1_x2): Updated from neon_vst1_x2. * config/arm/iterators.md (VMEMX2): New mode iterator. (VMEMX2_q): New mode attribute. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 1 + gcc/config/arm/iterators.md | 6 + gcc/config/arm/neon.md | 6 +- .../gcc.target/arm/simd/vst1q_base_xN_1.c | 69 +++++++++++ .../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 13 ++ .../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 13 ++ .../gcc.target/arm/simd/vst1q_p64_xN_1.c | 13 ++ 8 files changed, 232 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index c9bdda39663..1c447b6d42f 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -11327,6 +11327,38 @@ vst1_s64_x2 (int64_t * __a, int64x1x2_t __b) __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s8_x2 (int8_t * __a, int8x16x2_t __b) +{ + union { int8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s16_x2 (int16_t * __a, int16x8x2_t __b) +{ + union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s32_x2 (int32_t * __a, int32x4x2_t __b) +{ + union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s64_x2 (int64_t * __a, int64x2x2_t __b) +{ + union { int64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_s8_x3 (int8_t * __a, int8x8x3_t __b) @@ -11656,6 +11688,14 @@ vst1q_p64 (poly64_t * __a, poly64x2_t __b) __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p64_x2 (poly64_t * __a, poly64x2x2_t __b) +{ + union { poly64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); +} + #pragma GCC pop_options __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -11701,6 +11741,24 @@ vst1q_f32 (float32_t * __a, float32x4_t __b) __builtin_neon_vst1v4sf ((__builtin_neon_sf *) __a, __b); } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f16_x2 (float16_t * __a, float16x8x2_t __b) +{ + union { float16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hf (__a, __bu.__o); +} +#endif + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f32_x2 (float32_t * __a, float32x4x2_t __b) +{ + union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v4sf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_u8 (uint8_t * __a, uint8x16_t __b) @@ -11729,6 +11787,38 @@ vst1q_u64 (uint64_t * __a, uint64x2_t __b) __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u8_x2 (uint8_t * __a, uint8x16x2_t __b) +{ + union { uint8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u16_x2 (uint16_t * __a, uint16x8x2_t __b) +{ + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u32_x2 (uint32_t * __a, uint32x4x2_t __b) +{ + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u64_x2 (uint64_t * __a, uint64x2x2_t __b) +{ + union { uint64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_p8 (poly8_t * __a, poly8x16_t __b) @@ -11743,6 +11833,22 @@ vst1q_p16 (poly16_t * __a, poly16x8_t __b) __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p8_x2 (poly8_t * __a, poly8x16x2_t __b) +{ + union { poly8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p16_x2 (poly16_t * __a, poly16x8x2_t __b) +{ + union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c) @@ -20419,6 +20525,14 @@ vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b) __builtin_neon_vst1v8bf (__a, __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_bf16_x2 (bfloat16_t * __a, bfloat16x8x2_t __b) +{ + union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8bf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val) diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index a4056ec24d9..696ed72678a 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -312,6 +312,7 @@ VAR14 (STORE1, vst1, v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf) VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR14 (STORE1LANE, vst1_lane, diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index a9803538101..6c5a80d9348 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -141,6 +141,9 @@ ;; Opaque structure types used in table lookups (except vtbl1/vtbx1). (define_mode_iterator VTAB [TI EI OI]) +;; Opaque structure types for x2 variants of VSTR1/VSTR1Q or VLD1/VLD1Q. +(define_mode_iterator VMEMX2 [TI OI]) + ;; Widenable modes. (define_mode_iterator VW [V8QI V4HI V2SI]) @@ -1533,6 +1536,9 @@ ;; vtbl suffix for NEON vector modes. (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) +;; Suffix for x2 variants of vld1 and vst1. +(define_mode_attr VMEMX2_q [(TI "") (OI "q")]) + ;; fp16 or bf16 marker for 16-bit float modes. (define_mode_attr fporbf [(HF "fp16") (BF "bf16")]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index dfbaf5a6dc6..ce525ccbc39 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5125,9 +5125,9 @@ if (BYTES_BIG_ENDIAN) UNSPEC_VST1))] "TARGET_NEON") -(define_insn "neon_vst1_x2" - [(set (match_operand:TI 0 "neon_struct_operand" "=Um") - (unspec:TI [(match_operand:TI 1 "s_register_operand" "w") +(define_insn "neon_vst1_x2" + [(set (match_operand:VMEMX2 0 "neon_struct_operand" "=Um") + (unspec:VMEMX2 [(match_operand:VMEMX2 1 "s_register_operand" "w") (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VST1))] "TARGET_NEON" diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c new file mode 100644 index 00000000000..4a17a80974b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c @@ -0,0 +1,69 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +void test_vst1q_u8_x2 (uint8_t * ptr, uint8x16x2_t val) +{ + vst1q_u8_x2 (ptr, val); +} + +void test_vst1q_u16_x2 (uint16_t * ptr, uint16x8x2_t val) +{ + vst1q_u16_x2 (ptr, val); +} + +void test_vst1q_u32_x2 (uint32_t * ptr, uint32x4x2_t val) +{ + vst1q_u32_x2 (ptr, val); +} + +void test_vst1q_u64_x2 (uint64_t * ptr, uint64x2x2_t val) +{ + vst1q_u64_x2 (ptr, val); +} + +void test_vst1q_s8_x2 (int8_t * ptr, int8x16x2_t val) +{ + vst1q_s8_x2 (ptr, val); +} + +void test_vst1q_s16_x2 (int16_t * ptr, int16x8x2_t val) +{ + vst1q_s16_x2 (ptr, val); +} + +void test_vst1q_s32_x2 (int32_t * ptr, int32x4x2_t val) +{ + vst1q_s32_x2 (ptr, val); +} + +void test_vst1q_s64_x2 (int64_t * ptr, int64x2x2_t val) +{ + vst1q_s64_x2 (ptr, val); +} + +void test_vst1q_f32_x2 (float32_t * ptr, float32x4x2_t val) +{ + vst1q_f32_x2 (ptr, val); +} + +void test_vst1q_p8_x2 (poly8_t * ptr, poly8x16x2_t val) +{ + vst1q_p8_x2 (ptr, val); +} + +void test_vst1q_p16_x2 (poly16_t * ptr, poly16x8x2_t val) +{ + vst1q_p16_x2 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ + +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ + +/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ + +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c new file mode 100644 index 00000000000..2a4579f0aae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_v8_2a_bf16_neon } */ + +#include "arm_neon.h" + +void test_vst1q_bf16_x2 (bfloat16_t * ptr, bfloat16x8x2_t val) +{ + vst1q_bf16_x2 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c new file mode 100644 index 00000000000..61a7e558c48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_fp16_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_neon_fp16 } */ + +#include "arm_neon.h" + +void test_vst1q_f16_x2 (float16_t * ptr, float16x8x2_t val) +{ + vst1q_f16_x2 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c new file mode 100644 index 00000000000..82f3dad293c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst1q_p64_x2 (poly64_t * ptr, poly64x2x2_t val) +{ + vst1q_p64_x2 (ptr, val); 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001A2.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB9008 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784638043708828520 X-GMAIL-MSGID: 1784638043708828520 From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vst1q intrinsic for the arm port. This patch adds the _x3 variants of the vst1q intrinsic. ACLE documents: https://developer.arm.com/documentation/ihi0053/latest/ ISA documents: https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New. (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New. (vst1q_f16_x3, vst1q_f32_x3): New. (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New. (vst1q_bf16_x3): New. * config/arm/arm_neon_builtins.def (vst1q_x3): New entries. * config/arm/neon.md (neon_vst1q_x3): New. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 1 + gcc/config/arm/neon.md | 24 ++++ .../gcc.target/arm/simd/vst1q_base_xN_1.c | 60 +++++++++ .../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 6 + .../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 6 + .../gcc.target/arm/simd/vst1q_p64_xN_1.c | 6 + 7 files changed, 217 insertions(+) diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 1c447b6d42f..5cec7dd876f 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -11359,6 +11359,38 @@ vst1q_s64_x2 (int64_t * __a, int64x2x2_t __b) __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s8_x3 (int8_t * __a, int8x16x3_t __b) +{ + union { int8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s16_x3 (int16_t * __a, int16x8x3_t __b) +{ + union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s32_x3 (int32_t * __a, int32x4x3_t __b) +{ + union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s64_x3 (int64_t * __a, int64x2x3_t __b) +{ + union { int64x2x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_s8_x3 (int8_t * __a, int8x8x3_t __b) @@ -11696,6 +11728,14 @@ vst1q_p64_x2 (poly64_t * __a, poly64x2x2_t __b) __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p64_x3 (poly64_t * __a, poly64x2x3_t __b) +{ + union { poly64x2x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); +} + #pragma GCC pop_options __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -11759,6 +11799,24 @@ vst1q_f32_x2 (float32_t * __a, float32x4x2_t __b) __builtin_neon_vst1q_x2v4sf (__a, __bu.__o); } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f16_x3 (float16_t * __a, float16x8x3_t __b) +{ + union { float16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v8hf (__a, __bu.__o); +} +#endif + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f32_x3 (float32_t * __a, float32x4x3_t __b) +{ + union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v4sf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_u8 (uint8_t * __a, uint8x16_t __b) @@ -11819,6 +11877,38 @@ vst1q_u64_x2 (uint64_t * __a, uint64x2x2_t __b) __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u8_x3 (uint8_t * __a, uint8x16x3_t __b) +{ + union { uint8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u16_x3 (uint16_t * __a, uint16x8x3_t __b) +{ + union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u32_x3 (uint32_t * __a, uint32x4x3_t __b) +{ + union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u64_x3 (uint64_t * __a, uint64x2x3_t __b) +{ + union { uint64x2x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_p8 (poly8_t * __a, poly8x16_t __b) @@ -11849,6 +11939,22 @@ vst1q_p16_x2 (poly16_t * __a, poly16x8x2_t __b) __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p8_x3 (poly8_t * __a, poly8x16x3_t __b) +{ + union { poly8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p16_x3 (poly16_t * __a, poly16x8x3_t __b) +{ + union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c) @@ -20533,6 +20639,14 @@ vst1q_bf16_x2 (bfloat16_t * __a, bfloat16x8x2_t __b) __builtin_neon_vst1q_x2v8bf (__a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_bf16_x3 (bfloat16_t * __a, bfloat16x8x3_t __b) +{ + union { bfloat16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v8bf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val) diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 696ed72678a..cc014f9b89e 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -314,6 +314,7 @@ VAR14 (STORE1, vst1, VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (STORE1, vst1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR14 (STORE1LANE, vst1_lane, v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index ce525ccbc39..010cc579f23 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5145,6 +5145,30 @@ if (BYTES_BIG_ENDIAN) [(set_attr "type" "neon_store1_3reg")] ) +(define_insn "neon_vst1q_x3" + [(set (match_operand:CI 0 "neon_struct_operand" "=Um") + (unspec:CI [(match_operand:CI 1 "s_register_operand" "w") + (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST1))] + "TARGET_NEON" +{ + int regno = REGNO (operands[1]); + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 2); + ops[3] = gen_rtx_REG (DImode, regno + 4); + output_asm_insn ("vst1.\t{%P1, %P2, %P3}, %A0", ops); + + ops[1] = gen_rtx_REG (DImode, regno + 6); + ops[2] = gen_rtx_REG (DImode, regno + 8); + ops[3] = gen_rtx_REG (DImode, regno + 10); + output_asm_insn ("vst1.\t{%P1, %P2, %P3}, %A0", ops); + return ""; +} + [(set_attr "type" "neon_store1_3reg")] +) + (define_insn "neon_vst1_x4" [(set (match_operand:OI 0 "neon_struct_operand" "=Um") (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c index 4a17a80974b..838da09fee7 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c @@ -60,10 +60,70 @@ void test_vst1q_p16_x2 (poly16_t * ptr, poly16x8x2_t val) vst1q_p16_x2 (ptr, val); } +void test_vst1q_u8_x3 (uint8_t * ptr, uint8x16x3_t val) +{ + vst1q_u8_x3 (ptr, val); +} + +void test_vst1q_u16_x3 (uint16_t * ptr, uint16x8x3_t val) +{ + vst1q_u16_x3 (ptr, val); +} + +void test_vst1q_u32_x3 (uint32_t * ptr, uint32x4x3_t val) +{ + vst1q_u32_x3 (ptr, val); +} + +void test_vst1q_u64_x3 (uint64_t * ptr, uint64x2x3_t val) +{ + vst1q_u64_x3 (ptr, val); +} + +void test_vst1q_s8_x3 (int8_t * ptr, int8x16x3_t val) +{ + vst1q_s8_x3 (ptr, val); +} + +void test_vst1q_s16_x3 (int16_t * ptr, int16x8x3_t val) +{ + vst1q_s16_x3 (ptr, val); +} + +void test_vst1q_s32_x3 (int32_t * ptr, int32x4x3_t val) +{ + vst1q_s32_x3 (ptr, val); +} + +void test_vst1q_s64_x3 (int64_t * ptr, int64x2x3_t val) +{ + vst1q_s64_x3 (ptr, val); +} + +void test_vst1q_f32_x3 (float32_t * ptr, float32x4x3_t val) +{ + vst1q_f32_x3 (ptr, val); +} + +void test_vst1q_p8_x3 (poly8_t * ptr, poly8x16x3_t val) +{ + vst1q_p8_x3 (ptr, val); +} + +void test_vst1q_p16_x3 (poly16_t * ptr, poly16x8x3_t val) +{ + vst1q_p16_x3 (ptr, val); +} + + /* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c index 2a4579f0aae..2593c31c756 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c @@ -10,4 +10,10 @@ void test_vst1q_bf16_x2 (bfloat16_t * ptr, bfloat16x8x2_t val) vst1q_bf16_x2 (ptr, val); } +void test_vst1q_bf16_x3 (bfloat16_t * ptr, bfloat16x8x3_t val) +{ + vst1q_bf16_x3 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c index 61a7e558c48..28e949b557a 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c @@ -10,4 +10,10 @@ void test_vst1q_f16_x2 (float16_t * ptr, float16x8x2_t val) vst1q_f16_x2 (ptr, val); } +void test_vst1q_f16_x3 (float16_t * ptr, float16x8x3_t val) +{ + vst1q_f16_x3 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c index 82f3dad293c..7878d936b9f 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c @@ -10,4 +10,10 @@ void test_vst1q_p64_x2 (poly64_t * ptr, poly64x2x2_t val) vst1q_p64_x2 (ptr, val); } +void test_vst1q_p64_x3 (poly64_t * ptr, poly64x2x3_t val) +{ + vst1q_p64_x3 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ From patchwork Thu Dec 7 15:36:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezra Sitorus X-Patchwork-Id: 175212 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4866998vqy; Thu, 7 Dec 2023 07:37:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IEIhsdlCxEf42S4CO25+PyKJ2snyivAjWJjZHD5e4Bz/GLuChgLXU8/trGKwYLhC7RoCp3z X-Received: by 2002:a05:620a:6d15:b0:77e:fe81:8bb1 with SMTP id ul21-20020a05620a6d1500b0077efe818bb1mr1159601qkn.17.1701963467554; Thu, 07 Dec 2023 07:37:47 -0800 (PST) ARC-Seal: i=4; a=rsa-sha256; t=1701963467; cv=pass; d=google.com; s=arc-20160816; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF00009B9D.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB9276 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784638045037406451 X-GMAIL-MSGID: 1784638045037406451 From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vst1q intrinsic for the arm port. This patch adds the _x4 variants of the vst1q intrinsic. ACLE: https://developer.arm.com/documentation/ihi0053/latest/ ISA documents: https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New. (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New. (vst1q_f16_x4, vst1q_f32_x4): New. (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New. (vst1q_bf16_x4): New. * config/arm/arm_neon_builtins.def (vst1q_x4): New entries. * config/arm/neon.md (neon_vst1q_x4): New. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 1 + gcc/config/arm/neon.md | 26 ++++ .../gcc.target/arm/simd/vst1q_base_xN_1.c | 59 +++++++++ .../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 8 +- .../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 6 + .../gcc.target/arm/simd/vst1q_p64_xN_1.c | 6 + 7 files changed, 219 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 5cec7dd876f..af1f747f262 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -11391,6 +11391,38 @@ vst1q_s64_x3 (int64_t * __a, int64x2x3_t __b) __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s8_x4 (int8_t * __a, int8x16x4_t __b) +{ + union { int8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s16_x4 (int16_t * __a, int16x8x4_t __b) +{ + union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s32_x4 (int32_t * __a, int32x4x4_t __b) +{ + union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s64_x4 (int64_t * __a, int64x2x4_t __b) +{ + union { int64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_s8_x3 (int8_t * __a, int8x8x3_t __b) @@ -11736,6 +11768,14 @@ vst1q_p64_x3 (poly64_t * __a, poly64x2x3_t __b) __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p64_x4 (poly64_t * __a, poly64x2x4_t __b) +{ + union { poly64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o); +} + #pragma GCC pop_options __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -11817,6 +11857,24 @@ vst1q_f32_x3 (float32_t * __a, float32x4x3_t __b) __builtin_neon_vst1q_x3v4sf (__a, __bu.__o); } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f16_x4 (float16_t * __a, float16x8x4_t __b) +{ + union { float16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v8hf (__a, __bu.__o); +} +#endif + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f32_x4 (float32_t * __a, float32x4x4_t __b) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v4sf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_u8 (uint8_t * __a, uint8x16_t __b) @@ -11909,6 +11967,38 @@ vst1q_u64_x3 (uint64_t * __a, uint64x2x3_t __b) __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u8_x4 (uint8_t * __a, uint8x16x4_t __b) +{ + union { uint8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u16_x4 (uint16_t * __a, uint16x8x4_t __b) +{ + union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u32_x4 (uint32_t * __a, uint32x4x4_t __b) +{ + union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u64_x4 (uint64_t * __a, uint64x2x4_t __b) +{ + union { uint64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_p8 (poly8_t * __a, poly8x16_t __b) @@ -11955,6 +12045,22 @@ vst1q_p16_x3 (poly16_t * __a, poly16x8x3_t __b) __builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p8_x4 (poly8_t * __a, poly8x16x4_t __b) +{ + union { poly8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p16_x4 (poly16_t * __a, poly16x8x4_t __b) +{ + union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c) @@ -20647,6 +20753,14 @@ vst1q_bf16_x3 (bfloat16_t * __a, bfloat16x8x3_t __b) __builtin_neon_vst1q_x3v8bf (__a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_bf16_x4 (bfloat16_t * __a, bfloat16x8x4_t __b) +{ + union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v8bf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val) diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index cc014f9b89e..55e09722748 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -316,6 +316,7 @@ VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR7 (STORE1, vst1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (STORE1, vst1q_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR14 (STORE1LANE, vst1_lane, v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf) VAR13 (LOAD1, vld2, diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 010cc579f23..e069ceb651c 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5169,6 +5169,32 @@ if (BYTES_BIG_ENDIAN) [(set_attr "type" "neon_store1_3reg")] ) +(define_insn "neon_vst1q_x4" + [(set (match_operand:XI 0 "neon_struct_operand" "=Um") + (unspec:XI [(match_operand:XI 1 "s_register_operand" "w") + (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST1))] + "TARGET_NEON" +{ + int regno = REGNO (operands[1]); + rtx ops[5]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 2); + ops[3] = gen_rtx_REG (DImode, regno + 4); + ops[4] = gen_rtx_REG (DImode, regno + 6); + output_asm_insn ("vst1.\t{%P1, %P2, %P3, %P4}, %A0", ops); + + ops[1] = gen_rtx_REG (DImode, regno + 8); + ops[2] = gen_rtx_REG (DImode, regno + 10); + ops[3] = gen_rtx_REG (DImode, regno + 12); + ops[4] = gen_rtx_REG (DImode, regno + 14); + output_asm_insn ("vst1.\t{%P1, %P2, %P3, %P4}, %A0", ops); + return ""; +} + [(set_attr "type" "neon_store1_4reg")] +) + (define_insn "neon_vst1_x4" [(set (match_operand:OI 0 "neon_struct_operand" "=Um") (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c index 838da09fee7..5a639560de6 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c @@ -115,15 +115,74 @@ void test_vst1q_p16_x3 (poly16_t * ptr, poly16x8x3_t val) vst1q_p16_x3 (ptr, val); } +void test_vst1q_u8_x4 (uint8_t * ptr, uint8x16x4_t val) +{ + vst1q_u8_x4 (ptr, val); +} + +void test_vst1q_u16_x4 (uint16_t * ptr, uint16x8x4_t val) +{ + vst1q_u16_x4 (ptr, val); +} + +void test_vst1q_u32_x4 (uint32_t * ptr, uint32x4x4_t val) +{ + vst1q_u32_x4 (ptr, val); +} + +void test_vst1q_u64_x4 (uint64_t * ptr, uint64x2x4_t val) +{ + vst1q_u64_x4 (ptr, val); +} + +void test_vst1q_s8_x4 (int8_t * ptr, int8x16x4_t val) +{ + vst1q_s8_x4 (ptr, val); +} + +void test_vst1q_s16_x4 (int16_t * ptr, int16x8x4_t val) +{ + vst1q_s16_x4 (ptr, val); +} + +void test_vst1q_s32_x4 (int32_t * ptr, int32x4x4_t val) +{ + vst1q_s32_x4 (ptr, val); +} + +void test_vst1q_s64_x4 (int64_t * ptr, int64x2x4_t val) +{ + vst1q_s64_x4 (ptr, val); +} + +void test_vst1q_f32_x4 (float32_t * ptr, float32x4x4_t val) +{ + vst1q_f32_x4 (ptr, val); +} + +void test_vst1q_p8_x4 (poly8_t * ptr, poly8x16x4_t val) +{ + vst1q_p8_x4 (ptr, val); +} + +void test_vst1q_p16_x4 (poly16_t * ptr, poly16x8x4_t val) +{ + vst1q_p16_x4 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ /* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ /* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c index 2593c31c756..84fa8509db8 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c @@ -15,5 +15,11 @@ void test_vst1q_bf16_x3 (bfloat16_t * ptr, bfloat16x8x3_t val) vst1q_bf16_x3 (ptr, val); } +void test_vst1q_bf16_x4 (bfloat16_t * ptr, bfloat16x8x4_t val) +{ + vst1q_bf16_x4 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ -/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ \ No newline at end of file +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c index 28e949b557a..5b13edf9998 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c @@ -15,5 +15,11 @@ void test_vst1q_f16_x3 (float16_t * ptr, float16x8x3_t val) vst1q_f16_x3 (ptr, val); } +void test_vst1q_f16_x4 (float16_t * ptr, float16x8x4_t val) +{ + vst1q_f16_x4 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c index 7878d936b9f..f49917d5ec8 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c @@ -15,5 +15,11 @@ void test_vst1q_p64_x3 (poly64_t * ptr, poly64x2x3_t val) vst1q_p64_x3 (ptr, val); } +void test_vst1q_p64_x4 (poly64_t * ptr, poly64x2x4_t val) +{ + vst1q_p64_x4 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */