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[23.128.96.31]) by mx.google.com with ESMTPS id i5-20020a654845000000b005b99ea783aasi375851pgs.755.2023.12.06.12.13.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 12:13:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=aAx8EBPK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id C9C6082A177F; Wed, 6 Dec 2023 12:13:41 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442873AbjLFUNa (ORCPT + 99 others); Wed, 6 Dec 2023 15:13:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379518AbjLFUN2 (ORCPT ); Wed, 6 Dec 2023 15:13:28 -0500 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A483D51; Wed, 6 Dec 2023 12:13:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701893614; x=1733429614; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Hgxkrb/i5j4fmZuDpTPgn2mgEJgH4vr5qarhtSzu56M=; b=aAx8EBPK+yTF+xSI2X4sXXzmpc/QWvLR0WJDV9tnVdyTrqg1SuR7/H9U 6ambCMdD4+fhQ+WIvp8IXYCYD6FFKDaE+vTv3KiSfFxDe1Lwd+7Im014c NFMuEOecsd/VjdgEHmq3INbCU//ODaYVHO63PKP9hC8PQuC/XkcD4k5Yx dS6bv+YphfbQh+At4mfoENCw2j2DCBfZ02bol2hDTij22vCIMgFJezy5/ zcZOYZ7+GLR1XGIMJMSgQYI155Ezi2KK9inXWbWnEJB6i+Ywh/OOHFLU/ NhkwCw6bfP9nrKCqE4Yq5+U+/TT+EtY1X0Dn/bNZlwkmw/1YoVdKisDhQ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="458445540" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="458445540" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 12:13:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="944766667" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="944766667" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga005.jf.intel.com with ESMTP; 06 Dec 2023 12:13:31 -0800 From: kan.liang@linux.intel.com To: acme@kernel.org, irogers@google.com, peterz@infradead.org, mingo@redhat.com, namhyung@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, john.g.garry@oracle.com, will@kernel.org, james.clark@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, yuhaixin.yhx@linux.alibaba.com, renyu.zj@linux.alibaba.com, tmricht@linux.ibm.com, ravi.bangoria@amd.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Kan Liang Subject: [PATCH 1/6] perf mem: Add mem_events into the supported perf_pmu Date: Wed, 6 Dec 2023 12:13:19 -0800 Message-Id: <20231206201324.184059-2-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231206201324.184059-1-kan.liang@linux.intel.com> References: <20231206201324.184059-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 06 Dec 2023 12:13:41 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784564810474829471 X-GMAIL-MSGID: 1784564810474829471 From: Kan Liang With the mem_events, perf doesn't need to read sysfs for each PMU to find the mem-events-supported PMU. The patch also makes it possible to clean up the related __weak functions later. The patch is only to add the mem_events into the perf_pmu for all ARCHs. It will be used in the later cleanup patches. Signed-off-by: Kan Liang Reviewed-by: Ian Rogers --- tools/perf/arch/arm64/util/mem-events.c | 4 ++-- tools/perf/arch/arm64/util/mem-events.h | 7 +++++++ tools/perf/arch/arm64/util/pmu.c | 6 ++++++ tools/perf/arch/s390/util/pmu.c | 3 +++ tools/perf/arch/x86/util/mem-events.c | 4 ++-- tools/perf/arch/x86/util/mem-events.h | 9 +++++++++ tools/perf/arch/x86/util/pmu.c | 7 +++++++ tools/perf/util/mem-events.c | 2 +- tools/perf/util/mem-events.h | 1 + tools/perf/util/pmu.c | 4 +++- tools/perf/util/pmu.h | 7 +++++++ 11 files changed, 48 insertions(+), 6 deletions(-) create mode 100644 tools/perf/arch/arm64/util/mem-events.h create mode 100644 tools/perf/arch/x86/util/mem-events.h diff --git a/tools/perf/arch/arm64/util/mem-events.c b/tools/perf/arch/arm64/util/mem-events.c index 3bcc5c7035c2..aaa4804922b4 100644 --- a/tools/perf/arch/arm64/util/mem-events.c +++ b/tools/perf/arch/arm64/util/mem-events.c @@ -4,7 +4,7 @@ #define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s } -static struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX] = { +struct perf_mem_event perf_mem_events_arm[PERF_MEM_EVENTS__MAX] = { E("spe-load", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/", "arm_spe_0"), E("spe-store", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/", "arm_spe_0"), E("spe-ldst", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/", "arm_spe_0"), @@ -17,7 +17,7 @@ struct perf_mem_event *perf_mem_events__ptr(int i) if (i >= PERF_MEM_EVENTS__MAX) return NULL; - return &perf_mem_events[i]; + return &perf_mem_events_arm[i]; } const char *perf_mem_events__name(int i, const char *pmu_name __maybe_unused) diff --git a/tools/perf/arch/arm64/util/mem-events.h b/tools/perf/arch/arm64/util/mem-events.h new file mode 100644 index 000000000000..5fc50be4be38 --- /dev/null +++ b/tools/perf/arch/arm64/util/mem-events.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ARM64_MEM_EVENTS_H +#define _ARM64_MEM_EVENTS_H + +extern struct perf_mem_event perf_mem_events_arm[PERF_MEM_EVENTS__MAX]; + +#endif /* _ARM64_MEM_EVENTS_H */ diff --git a/tools/perf/arch/arm64/util/pmu.c b/tools/perf/arch/arm64/util/pmu.c index 2a4eab2d160e..69673fcf4a61 100644 --- a/tools/perf/arch/arm64/util/pmu.c +++ b/tools/perf/arch/arm64/util/pmu.c @@ -8,6 +8,12 @@ #include #include +void perf_pmu__arch_init(struct perf_pmu *pmu) +{ + if (strcmp(pmu->name, "arm_spe_0")) + pmu->mem_events = perf_mem_events_arm; +} + const struct pmu_metrics_table *pmu_metrics_table__find(void) { struct perf_pmu *pmu; diff --git a/tools/perf/arch/s390/util/pmu.c b/tools/perf/arch/s390/util/pmu.c index 886c30e001fa..225d7dc2379c 100644 --- a/tools/perf/arch/s390/util/pmu.c +++ b/tools/perf/arch/s390/util/pmu.c @@ -19,4 +19,7 @@ void perf_pmu__arch_init(struct perf_pmu *pmu) !strcmp(pmu->name, S390_PMUPAI_EXT) || !strcmp(pmu->name, S390_PMUCPUM_CF)) pmu->selectable = true; + + if (pmu->is_core) + pmu->mem_events = perf_mem_events; } diff --git a/tools/perf/arch/x86/util/mem-events.c b/tools/perf/arch/x86/util/mem-events.c index 191b372f9a2d..2b81d229982c 100644 --- a/tools/perf/arch/x86/util/mem-events.c +++ b/tools/perf/arch/x86/util/mem-events.c @@ -16,13 +16,13 @@ static char mem_stores_name[100]; #define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s } -static struct perf_mem_event perf_mem_events_intel[PERF_MEM_EVENTS__MAX] = { +struct perf_mem_event perf_mem_events_intel[PERF_MEM_EVENTS__MAX] = { E("ldlat-loads", "%s/mem-loads,ldlat=%u/P", "%s/events/mem-loads"), E("ldlat-stores", "%s/mem-stores/P", "%s/events/mem-stores"), E(NULL, NULL, NULL), }; -static struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX] = { +struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX] = { E(NULL, NULL, NULL), E(NULL, NULL, NULL), E("mem-ldst", "ibs_op//", "ibs_op"), diff --git a/tools/perf/arch/x86/util/mem-events.h b/tools/perf/arch/x86/util/mem-events.h new file mode 100644 index 000000000000..3959e427f482 --- /dev/null +++ b/tools/perf/arch/x86/util/mem-events.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _X86_MEM_EVENTS_H +#define _X86_MEM_EVENTS_H + +extern struct perf_mem_event perf_mem_events_intel[PERF_MEM_EVENTS__MAX]; + +extern struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX]; + +#endif /* _X86_MEM_EVENTS_H */ diff --git a/tools/perf/arch/x86/util/pmu.c b/tools/perf/arch/x86/util/pmu.c index 469555ae9b3c..7e69f4f2e363 100644 --- a/tools/perf/arch/x86/util/pmu.c +++ b/tools/perf/arch/x86/util/pmu.c @@ -15,6 +15,7 @@ #include "../../../util/pmu.h" #include "../../../util/fncache.h" #include "../../../util/pmus.h" +#include "mem-events.h" #include "env.h" void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused) @@ -30,6 +31,12 @@ void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused) pmu->selectable = true; } #endif + + if (x86__is_amd_cpu()) { + if (strcmp(pmu->name, "ibs_op")) + pmu->mem_events = perf_mem_events_amd; + } else if (pmu->is_core) + pmu->mem_events = perf_mem_events_intel; } int perf_pmus__num_mem_pmus(void) diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 3a2e3687878c..0a8f415f5efe 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -19,7 +19,7 @@ unsigned int perf_mem_events__loads_ldlat = 30; #define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s } -static struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX] = { +struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX] = { E("ldlat-loads", "cpu/mem-loads,ldlat=%u/P", "cpu/events/mem-loads"), E("ldlat-stores", "cpu/mem-stores/P", "cpu/events/mem-stores"), E(NULL, NULL, NULL), diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h index b40ad6ea93fc..8c5694b2d0b0 100644 --- a/tools/perf/util/mem-events.h +++ b/tools/perf/util/mem-events.h @@ -34,6 +34,7 @@ enum { }; extern unsigned int perf_mem_events__loads_ldlat; +extern struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX]; int perf_mem_events__parse(const char *str); int perf_mem_events__init(void); diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 3c9609944a2f..3d4373b8ab63 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -986,8 +986,10 @@ static int pmu_max_precise(int dirfd, struct perf_pmu *pmu) } void __weak -perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused) +perf_pmu__arch_init(struct perf_pmu *pmu) { + if (pmu->is_core) + pmu->mem_events = perf_mem_events; } struct perf_pmu *perf_pmu__lookup(struct list_head *pmus, int dirfd, const char *name) diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 424c3fee0949..e35d985206db 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -10,6 +10,8 @@ #include #include "parse-events.h" #include "pmu-events/pmu-events.h" +#include "map_symbol.h" +#include "mem-events.h" struct evsel_config_term; struct perf_cpu_map; @@ -162,6 +164,11 @@ struct perf_pmu { */ bool exclude_guest; } missing_features; + + /** + * @mem_events: List of the supported mem events + */ + struct perf_mem_event *mem_events; }; /** @perf_pmu__fake: A special global PMU used for testing. */ From patchwork Wed Dec 6 20:13:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 174720 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4353811vqy; Wed, 6 Dec 2023 12:13:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IEPfEslaKbrQmx/FBH2glqLagM/Zahi9FLVC0Z9r/cID5XB4+33zZBMAb+407fnAALMbByR X-Received: by 2002:a17:902:b707:b0:1d0:b1f0:fdb with SMTP id d7-20020a170902b70700b001d0b1f00fdbmr1197763pls.46.1701893631913; Wed, 06 Dec 2023 12:13:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701893631; cv=none; d=google.com; s=arc-20160816; b=L5IJyxp8zmyAyv7myaRAKLXUj7HoDPMNwGst6lEyw1tRE42T9QCw7v05b3d3eP+ji7 6yQjj/C/TumHb3HbeWPTrbwL/wyCKLCZdy60Uv8YO7Pan2eoOoAvCw68782Ki02FrzQT qlYEjWZy04J0gL4mMiHQT1LX41w1A04WwCuj1cYep5UX1xIGxlKvDvszOtkYs80jXbgW tAh/S0x5/YCMqZdn7bOEJZF6uJg6hXEMtKYtxxy/Cxl/iOt6zVryeLT9GnKvZ3jQryPc lnnpHVLox0VY6RGaw0roDGINL7FVAYyH8ePBilkmJQfBQyDwQsIetY2i7YuYaOwaPWdW 7LFg== ARC-Message-Signature: i=1; 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[2620:137:e000::3:1]) by mx.google.com with ESMTPS id p5-20020a170902bd0500b001cfcb270ab3si292237pls.528.2023.12.06.12.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 12:13:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=KTpZ19zb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id F19DA82A177F; Wed, 6 Dec 2023 12:13:46 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442883AbjLFUNc (ORCPT + 99 others); Wed, 6 Dec 2023 15:13:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379521AbjLFUN3 (ORCPT ); Wed, 6 Dec 2023 15:13:29 -0500 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9C259A; Wed, 6 Dec 2023 12:13:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701893614; x=1733429614; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+Xl+cLE5mW6g3KrjS8RvlWu1KwekM/npOUGAg654Tdc=; b=KTpZ19zbFqu8tDl+52txRUvxFzqgJNy5dZkLv+4iYoPvSxXofB95C28T k/Mal2e9JsmXPN1oauJswFI1Hx4IzYm9pIKQEHrxYfohJ9/Wr0AkjXM/u YzDZeSYdwfuo9fOCOh/216t6Ul2w0XgFOgiFGjTlLshA2Hg8Jm6OKcNnL 6EMSAa/mTh1/ty5p+5RUqHbKcPxpRlxp7ePVTPKdjAUfVY6pOLLCoNDSL chgFbo7a1bmIZY3MWGqverGVnG2ZlsNQ9b8oOktIPg4b2MQVkZv8vDWak aRCPucCn8eSUPbNU/wgx3iobR8Ft93MjMT6XUct+cuElq3/EuZ479Hp9d g==; X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="458445552" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="458445552" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 12:13:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="944766672" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="944766672" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga005.jf.intel.com with ESMTP; 06 Dec 2023 12:13:32 -0800 From: kan.liang@linux.intel.com To: acme@kernel.org, irogers@google.com, peterz@infradead.org, mingo@redhat.com, namhyung@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, john.g.garry@oracle.com, will@kernel.org, james.clark@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, yuhaixin.yhx@linux.alibaba.com, renyu.zj@linux.alibaba.com, tmricht@linux.ibm.com, ravi.bangoria@amd.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Kan Liang Subject: [PATCH 2/6] perf mem: Clean up perf_mem_events__ptr() Date: Wed, 6 Dec 2023 12:13:20 -0800 Message-Id: <20231206201324.184059-3-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231206201324.184059-1-kan.liang@linux.intel.com> References: <20231206201324.184059-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 06 Dec 2023 12:13:47 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784564816921426172 X-GMAIL-MSGID: 1784564816921426172 From: Kan Liang The mem_events can be retrieved from the struct perf_pmu now. An ARCH specific perf_mem_events__ptr() is not required anymore. Remove all of them. The Intel hybrid has multiple mem-events-supported PMUs. But they share the same mem_events. Other ARCHs only support one mem-events-supported PMU. In the configuration, it's good enough to only configure the mem_events for one PMU. Add perf_mem_events_find_pmu() which returns the first mem-events-supported PMU. In the perf_mem_events__init(), the perf_pmus__scan() is not required anymore. It avoids checking the sysfs for every PMU on the system. Make the perf_mem_events__record_args() more generic. Remove the perf_mem_events__print_unsupport_hybrid(). Signed-off-by: Kan Liang Reviewed-by: Ian Rogers --- tools/perf/arch/arm64/util/mem-events.c | 10 +-- tools/perf/arch/x86/util/mem-events.c | 18 ++--- tools/perf/builtin-c2c.c | 28 +++++-- tools/perf/builtin-mem.c | 28 +++++-- tools/perf/util/mem-events.c | 103 ++++++++++++------------ tools/perf/util/mem-events.h | 9 ++- 6 files changed, 104 insertions(+), 92 deletions(-) diff --git a/tools/perf/arch/arm64/util/mem-events.c b/tools/perf/arch/arm64/util/mem-events.c index aaa4804922b4..2602e8688727 100644 --- a/tools/perf/arch/arm64/util/mem-events.c +++ b/tools/perf/arch/arm64/util/mem-events.c @@ -12,17 +12,9 @@ struct perf_mem_event perf_mem_events_arm[PERF_MEM_EVENTS__MAX] = { static char mem_ev_name[100]; -struct perf_mem_event *perf_mem_events__ptr(int i) -{ - if (i >= PERF_MEM_EVENTS__MAX) - return NULL; - - return &perf_mem_events_arm[i]; -} - const char *perf_mem_events__name(int i, const char *pmu_name __maybe_unused) { - struct perf_mem_event *e = perf_mem_events__ptr(i); + struct perf_mem_event *e = &perf_mem_events_arm[i]; if (i >= PERF_MEM_EVENTS__MAX) return NULL; diff --git a/tools/perf/arch/x86/util/mem-events.c b/tools/perf/arch/x86/util/mem-events.c index 2b81d229982c..5fb41d50118d 100644 --- a/tools/perf/arch/x86/util/mem-events.c +++ b/tools/perf/arch/x86/util/mem-events.c @@ -28,17 +28,6 @@ struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX] = { E("mem-ldst", "ibs_op//", "ibs_op"), }; -struct perf_mem_event *perf_mem_events__ptr(int i) -{ - if (i >= PERF_MEM_EVENTS__MAX) - return NULL; - - if (x86__is_amd_cpu()) - return &perf_mem_events_amd[i]; - - return &perf_mem_events_intel[i]; -} - bool is_mem_loads_aux_event(struct evsel *leader) { struct perf_pmu *pmu = perf_pmus__find("cpu"); @@ -54,7 +43,12 @@ bool is_mem_loads_aux_event(struct evsel *leader) const char *perf_mem_events__name(int i, const char *pmu_name) { - struct perf_mem_event *e = perf_mem_events__ptr(i); + struct perf_mem_event *e; + + if (x86__is_amd_cpu()) + e = &perf_mem_events_amd[i]; + else + e = &perf_mem_events_intel[i]; if (!e) return NULL; diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index a4cf9de7a7b5..76c760be1bcf 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -3215,12 +3215,19 @@ static int parse_record_events(const struct option *opt, const char *str, int unset __maybe_unused) { bool *event_set = (bool *) opt->value; + struct perf_pmu *pmu; + + pmu = perf_mem_events_find_pmu(); + if (!pmu) { + pr_err("failed: there is no PMU that supports perf c2c\n"); + exit(-1); + } if (!strcmp(str, "list")) { - perf_mem_events__list(); + perf_mem_events__list(pmu); exit(0); } - if (perf_mem_events__parse(str)) + if (perf_mem_events__parse(pmu, str)) exit(-1); *event_set = true; @@ -3245,6 +3252,7 @@ static int perf_c2c__record(int argc, const char **argv) bool all_user = false, all_kernel = false; bool event_set = false; struct perf_mem_event *e; + struct perf_pmu *pmu; struct option options[] = { OPT_CALLBACK('e', "event", &event_set, "event", "event selector. Use 'perf c2c record -e list' to list available events", @@ -3256,7 +3264,13 @@ static int perf_c2c__record(int argc, const char **argv) OPT_END() }; - if (perf_mem_events__init()) { + pmu = perf_mem_events_find_pmu(); + if (!pmu) { + pr_err("failed: no PMU supports the memory events\n"); + return -1; + } + + if (perf_mem_events__init(pmu)) { pr_err("failed: memory events not supported\n"); return -1; } @@ -3280,7 +3294,7 @@ static int perf_c2c__record(int argc, const char **argv) rec_argv[i++] = "record"; if (!event_set) { - e = perf_mem_events__ptr(PERF_MEM_EVENTS__LOAD_STORE); + e = perf_mem_events__ptr(pmu, PERF_MEM_EVENTS__LOAD_STORE); /* * The load and store operations are required, use the event * PERF_MEM_EVENTS__LOAD_STORE if it is supported. @@ -3289,15 +3303,15 @@ static int perf_c2c__record(int argc, const char **argv) e->record = true; rec_argv[i++] = "-W"; } else { - e = perf_mem_events__ptr(PERF_MEM_EVENTS__LOAD); + e = perf_mem_events__ptr(pmu, PERF_MEM_EVENTS__LOAD); e->record = true; - e = perf_mem_events__ptr(PERF_MEM_EVENTS__STORE); + e = perf_mem_events__ptr(pmu, PERF_MEM_EVENTS__STORE); e->record = true; } } - e = perf_mem_events__ptr(PERF_MEM_EVENTS__LOAD); + e = perf_mem_events__ptr(pmu, PERF_MEM_EVENTS__LOAD); if (e->record) rec_argv[i++] = "-W"; diff --git a/tools/perf/builtin-mem.c b/tools/perf/builtin-mem.c index 51499c20da01..8218c4721101 100644 --- a/tools/perf/builtin-mem.c +++ b/tools/perf/builtin-mem.c @@ -43,12 +43,19 @@ static int parse_record_events(const struct option *opt, const char *str, int unset __maybe_unused) { struct perf_mem *mem = *(struct perf_mem **)opt->value; + struct perf_pmu *pmu; + + pmu = perf_mem_events_find_pmu(); + if (!pmu) { + pr_err("failed: there is no PMU that supports perf mem\n"); + exit(-1); + } if (!strcmp(str, "list")) { - perf_mem_events__list(); + perf_mem_events__list(pmu); exit(0); } - if (perf_mem_events__parse(str)) + if (perf_mem_events__parse(pmu, str)) exit(-1); mem->operation = 0; @@ -72,6 +79,7 @@ static int __cmd_record(int argc, const char **argv, struct perf_mem *mem) int ret; bool all_user = false, all_kernel = false; struct perf_mem_event *e; + struct perf_pmu *pmu; struct option options[] = { OPT_CALLBACK('e', "event", &mem, "event", "event selector. use 'perf mem record -e list' to list available events", @@ -84,7 +92,13 @@ static int __cmd_record(int argc, const char **argv, struct perf_mem *mem) OPT_END() }; - if (perf_mem_events__init()) { + pmu = perf_mem_events_find_pmu(); + if (!pmu) { + pr_err("failed: no PMU supports the memory events\n"); + return -1; + } + + if (perf_mem_events__init(pmu)) { pr_err("failed: memory events not supported\n"); return -1; } @@ -113,7 +127,7 @@ static int __cmd_record(int argc, const char **argv, struct perf_mem *mem) rec_argv[i++] = "record"; - e = perf_mem_events__ptr(PERF_MEM_EVENTS__LOAD_STORE); + e = perf_mem_events__ptr(pmu, PERF_MEM_EVENTS__LOAD_STORE); /* * The load and store operations are required, use the event @@ -126,17 +140,17 @@ static int __cmd_record(int argc, const char **argv, struct perf_mem *mem) rec_argv[i++] = "-W"; } else { if (mem->operation & MEM_OPERATION_LOAD) { - e = perf_mem_events__ptr(PERF_MEM_EVENTS__LOAD); + e = perf_mem_events__ptr(pmu, PERF_MEM_EVENTS__LOAD); e->record = true; } if (mem->operation & MEM_OPERATION_STORE) { - e = perf_mem_events__ptr(PERF_MEM_EVENTS__STORE); + e = perf_mem_events__ptr(pmu, PERF_MEM_EVENTS__STORE); e->record = true; } } - e = perf_mem_events__ptr(PERF_MEM_EVENTS__LOAD); + e = perf_mem_events__ptr(pmu, PERF_MEM_EVENTS__LOAD); if (e->record) rec_argv[i++] = "-W"; diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 0a8f415f5efe..887ffdcce338 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -29,17 +29,42 @@ struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX] = { static char mem_loads_name[100]; static bool mem_loads_name__init; -struct perf_mem_event * __weak perf_mem_events__ptr(int i) +struct perf_mem_event *perf_mem_events__ptr(struct perf_pmu *pmu, int i) { - if (i >= PERF_MEM_EVENTS__MAX) + if (i >= PERF_MEM_EVENTS__MAX || !pmu) return NULL; - return &perf_mem_events[i]; + return &pmu->mem_events[i]; +} + +static struct perf_pmu *perf_pmus__scan_mem(struct perf_pmu *pmu) +{ + while ((pmu = perf_pmus__scan(pmu)) != NULL) { + if (pmu->mem_events) + return pmu; + } + return NULL; +} + +struct perf_pmu *perf_mem_events_find_pmu(void) +{ + /* + * The current perf mem doesn't support per-PMU configuration. + * The exact same configuration is applied to all the + * mem_events supported PMUs. + * Return the first mem_events supported PMU. + * + * Notes: The only case which may support multiple mem_events + * supported PMUs is Intel hybrid. The exact same mem_events + * is shared among the PMUs. Only configure the first PMU + * is good enough as well. + */ + return perf_pmus__scan_mem(NULL); } const char * __weak perf_mem_events__name(int i, const char *pmu_name __maybe_unused) { - struct perf_mem_event *e = perf_mem_events__ptr(i); + struct perf_mem_event *e = &perf_mem_events[i]; if (!e) return NULL; @@ -61,7 +86,7 @@ __weak bool is_mem_loads_aux_event(struct evsel *leader __maybe_unused) return false; } -int perf_mem_events__parse(const char *str) +int perf_mem_events__parse(struct perf_pmu *pmu, const char *str) { char *tok, *saveptr = NULL; bool found = false; @@ -79,7 +104,7 @@ int perf_mem_events__parse(const char *str) while (tok) { for (j = 0; j < PERF_MEM_EVENTS__MAX; j++) { - struct perf_mem_event *e = perf_mem_events__ptr(j); + struct perf_mem_event *e = perf_mem_events__ptr(pmu, j); if (!e->tag) continue; @@ -112,7 +137,7 @@ static bool perf_mem_event__supported(const char *mnt, struct perf_pmu *pmu, return !stat(path, &st); } -int perf_mem_events__init(void) +int perf_mem_events__init(struct perf_pmu *pmu) { const char *mnt = sysfs__mount(); bool found = false; @@ -122,8 +147,7 @@ int perf_mem_events__init(void) return -ENOENT; for (j = 0; j < PERF_MEM_EVENTS__MAX; j++) { - struct perf_mem_event *e = perf_mem_events__ptr(j); - struct perf_pmu *pmu = NULL; + struct perf_mem_event *e = perf_mem_events__ptr(pmu, j); /* * If the event entry isn't valid, skip initialization @@ -132,29 +156,20 @@ int perf_mem_events__init(void) if (!e->tag) continue; - /* - * Scan all PMUs not just core ones, since perf mem/c2c on - * platforms like AMD uses IBS OP PMU which is independent - * of core PMU. - */ - while ((pmu = perf_pmus__scan(pmu)) != NULL) { - e->supported |= perf_mem_event__supported(mnt, pmu, e); - if (e->supported) { - found = true; - break; - } - } + e->supported |= perf_mem_event__supported(mnt, pmu, e); + if (e->supported) + found = true; } return found ? 0 : -ENOENT; } -void perf_mem_events__list(void) +void perf_mem_events__list(struct perf_pmu *pmu) { int j; for (j = 0; j < PERF_MEM_EVENTS__MAX; j++) { - struct perf_mem_event *e = perf_mem_events__ptr(j); + struct perf_mem_event *e = perf_mem_events__ptr(pmu, j); fprintf(stderr, "%-*s%-*s%s", e->tag ? 13 : 0, @@ -165,50 +180,32 @@ void perf_mem_events__list(void) } } -static void perf_mem_events__print_unsupport_hybrid(struct perf_mem_event *e, - int idx) -{ - const char *mnt = sysfs__mount(); - struct perf_pmu *pmu = NULL; - - while ((pmu = perf_pmus__scan(pmu)) != NULL) { - if (!perf_mem_event__supported(mnt, pmu, e)) { - pr_err("failed: event '%s' not supported\n", - perf_mem_events__name(idx, pmu->name)); - } - } -} - int perf_mem_events__record_args(const char **rec_argv, int *argv_nr, char **rec_tmp, int *tmp_nr) { const char *mnt = sysfs__mount(); + struct perf_pmu *pmu = NULL; int i = *argv_nr, k = 0; struct perf_mem_event *e; - for (int j = 0; j < PERF_MEM_EVENTS__MAX; j++) { - e = perf_mem_events__ptr(j); - if (!e->record) - continue; - if (perf_pmus__num_mem_pmus() == 1) { - if (!e->supported) { - pr_err("failed: event '%s' not supported\n", - perf_mem_events__name(j, NULL)); - return -1; - } + while ((pmu = perf_pmus__scan_mem(pmu)) != NULL) { + for (int j = 0; j < PERF_MEM_EVENTS__MAX; j++) { + e = perf_mem_events__ptr(pmu, j); - rec_argv[i++] = "-e"; - rec_argv[i++] = perf_mem_events__name(j, NULL); - } else { - struct perf_pmu *pmu = NULL; + if (!e->record) + continue; if (!e->supported) { - perf_mem_events__print_unsupport_hybrid(e, j); + pr_err("failed: event '%s' not supported\n", + perf_mem_events__name(j, pmu->name)); return -1; } - while ((pmu = perf_pmus__scan(pmu)) != NULL) { + if (perf_pmus__num_mem_pmus() == 1) { + rec_argv[i++] = "-e"; + rec_argv[i++] = perf_mem_events__name(j, NULL); + } else { const char *s = perf_mem_events__name(j, pmu->name); if (!perf_mem_event__supported(mnt, pmu, e)) diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h index 8c5694b2d0b0..59a4303aac96 100644 --- a/tools/perf/util/mem-events.h +++ b/tools/perf/util/mem-events.h @@ -36,14 +36,15 @@ enum { extern unsigned int perf_mem_events__loads_ldlat; extern struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX]; -int perf_mem_events__parse(const char *str); -int perf_mem_events__init(void); +int perf_mem_events__parse(struct perf_pmu *pmu, const char *str); +int perf_mem_events__init(struct perf_pmu *pmu); const char *perf_mem_events__name(int i, const char *pmu_name); -struct perf_mem_event *perf_mem_events__ptr(int i); +struct perf_mem_event *perf_mem_events__ptr(struct perf_pmu *pmu, int i); +struct perf_pmu *perf_mem_events_find_pmu(void); bool is_mem_loads_aux_event(struct evsel *leader); -void perf_mem_events__list(void); +void perf_mem_events__list(struct perf_pmu *pmu); int perf_mem_events__record_args(const char **rec_argv, int *argv_nr, char **rec_tmp, int *tmp_nr); From patchwork Wed Dec 6 20:13:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 174722 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4353993vqy; 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[2620:137:e000::3:6]) by mx.google.com with ESMTPS id n8-20020a654508000000b005bdc49d22a4si423822pgq.103.2023.12.06.12.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 12:14:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=GVycMFsz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 9E6EC81CE864; Wed, 6 Dec 2023 12:13:59 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442897AbjLFUNf (ORCPT + 99 others); Wed, 6 Dec 2023 15:13:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442871AbjLFUNa (ORCPT ); Wed, 6 Dec 2023 15:13:30 -0500 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED9B318D; Wed, 6 Dec 2023 12:13:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701893614; x=1733429614; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WKjJ4oeBMvIIlcJ7g1qgViaOSriNPdYlDcj45RBSUJ4=; b=GVycMFszC/mRfaUnKgL9/OYvrVGQRHhDvdXFnONLx6U21x5aDtZEuseG hP++TDK30esfMGDU14rsS5Pd1DK+uGYavFATRFiWaaFgj0b0iC2DTlEkU Xz5s6McvdV+Q0W6hymfGRAciM04bXlJXPJy0twehsO6o1CuHdAiXa0VdH 3ktkVDd2qruLnl1Vn/8HUkvqEf633oE25JH32ot9gmy1uTur3B/0yQtiG L34QyWEM2ty1+2rRAPJBUQuenbt7U1BYY8ikwv7xCAVuCgI75WEff9pir /MZ1oJciYBNTNIIOflIXaghpxYF81sir1QRFutD/6J43gWH8eATjU+cU/ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="458445564" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="458445564" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 12:13:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="944766675" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="944766675" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga005.jf.intel.com with ESMTP; 06 Dec 2023 12:13:32 -0800 From: kan.liang@linux.intel.com To: acme@kernel.org, irogers@google.com, peterz@infradead.org, mingo@redhat.com, namhyung@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, john.g.garry@oracle.com, will@kernel.org, james.clark@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, yuhaixin.yhx@linux.alibaba.com, renyu.zj@linux.alibaba.com, tmricht@linux.ibm.com, ravi.bangoria@amd.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Kan Liang Subject: [PATCH 3/6] perf mem: Clean up perf_mem_events__name() Date: Wed, 6 Dec 2023 12:13:21 -0800 Message-Id: <20231206201324.184059-4-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231206201324.184059-1-kan.liang@linux.intel.com> References: <20231206201324.184059-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 06 Dec 2023 12:14:00 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784564836065465143 X-GMAIL-MSGID: 1784564836065465143 From: Kan Liang Introduce a generic perf_mem_events__name(). Remove the ARCH-specific one. The mem_load events may have a different format. Add ldlat and aux_event in the struct perf_mem_event to indicate the format and the extra aux event. Add perf_mem_events_intel_aux[] to support the extra mem_load_aux event. Signed-off-by: Kan Liang --- tools/perf/arch/arm64/util/mem-events.c | 26 ++------- tools/perf/arch/powerpc/util/mem-events.c | 13 ++--- tools/perf/arch/powerpc/util/mem-events.h | 7 +++ tools/perf/arch/powerpc/util/pmu.c | 11 ++++ tools/perf/arch/x86/util/mem-events.c | 70 +++++------------------ tools/perf/arch/x86/util/mem-events.h | 1 + tools/perf/arch/x86/util/pmu.c | 8 ++- tools/perf/util/mem-events.c | 56 ++++++++++++------ tools/perf/util/mem-events.h | 3 +- 9 files changed, 89 insertions(+), 106 deletions(-) create mode 100644 tools/perf/arch/powerpc/util/mem-events.h create mode 100644 tools/perf/arch/powerpc/util/pmu.c diff --git a/tools/perf/arch/arm64/util/mem-events.c b/tools/perf/arch/arm64/util/mem-events.c index 2602e8688727..eb2ef84f0fc8 100644 --- a/tools/perf/arch/arm64/util/mem-events.c +++ b/tools/perf/arch/arm64/util/mem-events.c @@ -2,28 +2,10 @@ #include "map_symbol.h" #include "mem-events.h" -#define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s } +#define E(t, n, s, l, a) { .tag = t, .name = n, .sysfs_name = s, .ldlat = l, .aux_event = a } struct perf_mem_event perf_mem_events_arm[PERF_MEM_EVENTS__MAX] = { - E("spe-load", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/", "arm_spe_0"), - E("spe-store", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/", "arm_spe_0"), - E("spe-ldst", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/", "arm_spe_0"), + E("spe-load", "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/", "arm_spe_0", true, 0), + E("spe-store", "%s/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/", "arm_spe_0", false, 0), + E("spe-ldst", "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/", "arm_spe_0", true, 0), }; - -static char mem_ev_name[100]; - -const char *perf_mem_events__name(int i, const char *pmu_name __maybe_unused) -{ - struct perf_mem_event *e = &perf_mem_events_arm[i]; - - if (i >= PERF_MEM_EVENTS__MAX) - return NULL; - - if (i == PERF_MEM_EVENTS__LOAD || i == PERF_MEM_EVENTS__LOAD_STORE) - scnprintf(mem_ev_name, sizeof(mem_ev_name), - e->name, perf_mem_events__loads_ldlat); - else /* PERF_MEM_EVENTS__STORE */ - scnprintf(mem_ev_name, sizeof(mem_ev_name), e->name); - - return mem_ev_name; -} diff --git a/tools/perf/arch/powerpc/util/mem-events.c b/tools/perf/arch/powerpc/util/mem-events.c index 78b986e5268d..b7883e38950f 100644 --- a/tools/perf/arch/powerpc/util/mem-events.c +++ b/tools/perf/arch/powerpc/util/mem-events.c @@ -2,11 +2,10 @@ #include "map_symbol.h" #include "mem-events.h" -/* PowerPC does not support 'ldlat' parameter. */ -const char *perf_mem_events__name(int i, const char *pmu_name __maybe_unused) -{ - if (i == PERF_MEM_EVENTS__LOAD) - return "cpu/mem-loads/"; +#define E(t, n, s, l, a) { .tag = t, .name = n, .sysfs_name = s, .ldlat = l, .aux_event = a } - return "cpu/mem-stores/"; -} +struct perf_mem_event perf_mem_events_power[PERF_MEM_EVENTS__MAX] = { + E("ldlat-loads", "%s/mem-loads/", "cpu/events/mem-loads", false, 0), + E("ldlat-stores", "%s/mem-stores/", "cpu/events/mem-stores", false, 0), + E(NULL, NULL, NULL, false, 0), +}; diff --git a/tools/perf/arch/powerpc/util/mem-events.h b/tools/perf/arch/powerpc/util/mem-events.h new file mode 100644 index 000000000000..6acc3d1b6873 --- /dev/null +++ b/tools/perf/arch/powerpc/util/mem-events.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _POWER_MEM_EVENTS_H +#define _POWER_MEM_EVENTS_H + +extern struct perf_mem_event perf_mem_events_power[PERF_MEM_EVENTS__MAX]; + +#endif /* _POWER_MEM_EVENTS_H */ diff --git a/tools/perf/arch/powerpc/util/pmu.c b/tools/perf/arch/powerpc/util/pmu.c new file mode 100644 index 000000000000..168173f88ddb --- /dev/null +++ b/tools/perf/arch/powerpc/util/pmu.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +#include "../../../util/pmu.h" + +void perf_pmu__arch_init(struct perf_pmu *pmu) +{ + if (pmu->is_core) + pmu->mem_events = perf_mem_events_power; +} diff --git a/tools/perf/arch/x86/util/mem-events.c b/tools/perf/arch/x86/util/mem-events.c index 5fb41d50118d..f0e66a0151a0 100644 --- a/tools/perf/arch/x86/util/mem-events.c +++ b/tools/perf/arch/x86/util/mem-events.c @@ -7,25 +7,26 @@ #include "linux/string.h" #include "env.h" -static char mem_loads_name[100]; -static bool mem_loads_name__init; -static char mem_stores_name[100]; - #define MEM_LOADS_AUX 0x8203 -#define MEM_LOADS_AUX_NAME "{%s/mem-loads-aux/,%s/mem-loads,ldlat=%u/}:P" -#define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s } +#define E(t, n, s, l, a) { .tag = t, .name = n, .sysfs_name = s, .ldlat = l, .aux_event = a } struct perf_mem_event perf_mem_events_intel[PERF_MEM_EVENTS__MAX] = { - E("ldlat-loads", "%s/mem-loads,ldlat=%u/P", "%s/events/mem-loads"), - E("ldlat-stores", "%s/mem-stores/P", "%s/events/mem-stores"), - E(NULL, NULL, NULL), + E("ldlat-loads", "%s/mem-loads,ldlat=%u/P", "%s/events/mem-loads", true, 0), + E("ldlat-stores", "%s/mem-stores/P", "%s/events/mem-stores", false, 0), + E(NULL, NULL, NULL, false, 0), +}; + +struct perf_mem_event perf_mem_events_intel_aux[PERF_MEM_EVENTS__MAX] = { + E("ldlat-loads", "{%s/mem-loads-aux/,%s/mem-loads,ldlat=%u/}:P", "%s/events/mem-loads", true, MEM_LOADS_AUX), + E("ldlat-stores", "%s/mem-stores/P", "%s/events/mem-stores", false, 0), + E(NULL, NULL, NULL, false, 0), }; struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX] = { - E(NULL, NULL, NULL), - E(NULL, NULL, NULL), - E("mem-ldst", "ibs_op//", "ibs_op"), + E(NULL, NULL, NULL, false, 0), + E(NULL, NULL, NULL, false, 0), + E("mem-ldst", "%s//", "ibs_op", false, 0), }; bool is_mem_loads_aux_event(struct evsel *leader) @@ -40,48 +41,3 @@ bool is_mem_loads_aux_event(struct evsel *leader) return leader->core.attr.config == MEM_LOADS_AUX; } - -const char *perf_mem_events__name(int i, const char *pmu_name) -{ - struct perf_mem_event *e; - - if (x86__is_amd_cpu()) - e = &perf_mem_events_amd[i]; - else - e = &perf_mem_events_intel[i]; - - if (!e) - return NULL; - - if (i == PERF_MEM_EVENTS__LOAD) { - if (mem_loads_name__init && !pmu_name) - return mem_loads_name; - - if (!pmu_name) { - mem_loads_name__init = true; - pmu_name = "cpu"; - } - - if (perf_pmus__have_event(pmu_name, "mem-loads-aux")) { - scnprintf(mem_loads_name, sizeof(mem_loads_name), - MEM_LOADS_AUX_NAME, pmu_name, pmu_name, - perf_mem_events__loads_ldlat); - } else { - scnprintf(mem_loads_name, sizeof(mem_loads_name), - e->name, pmu_name, - perf_mem_events__loads_ldlat); - } - return mem_loads_name; - } - - if (i == PERF_MEM_EVENTS__STORE) { - if (!pmu_name) - pmu_name = "cpu"; - - scnprintf(mem_stores_name, sizeof(mem_stores_name), - e->name, pmu_name); - return mem_stores_name; - } - - return e->name; -} diff --git a/tools/perf/arch/x86/util/mem-events.h b/tools/perf/arch/x86/util/mem-events.h index 3959e427f482..f55c8d3b7d59 100644 --- a/tools/perf/arch/x86/util/mem-events.h +++ b/tools/perf/arch/x86/util/mem-events.h @@ -3,6 +3,7 @@ #define _X86_MEM_EVENTS_H extern struct perf_mem_event perf_mem_events_intel[PERF_MEM_EVENTS__MAX]; +extern struct perf_mem_event perf_mem_events_intel_aux[PERF_MEM_EVENTS__MAX]; extern struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX]; diff --git a/tools/perf/arch/x86/util/pmu.c b/tools/perf/arch/x86/util/pmu.c index 7e69f4f2e363..446f8197aae4 100644 --- a/tools/perf/arch/x86/util/pmu.c +++ b/tools/perf/arch/x86/util/pmu.c @@ -35,8 +35,12 @@ void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused) if (x86__is_amd_cpu()) { if (strcmp(pmu->name, "ibs_op")) pmu->mem_events = perf_mem_events_amd; - } else if (pmu->is_core) - pmu->mem_events = perf_mem_events_intel; + } else if (pmu->is_core) { + if (perf_pmu__have_event(pmu, "mem-loads-aux")) + pmu->mem_events = perf_mem_events_intel_aux; + else + pmu->mem_events = perf_mem_events_intel; + } } int perf_pmus__num_mem_pmus(void) diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 887ffdcce338..3a60cbcd6d8e 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -17,17 +17,17 @@ unsigned int perf_mem_events__loads_ldlat = 30; -#define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s } +#define E(t, n, s, l, a) { .tag = t, .name = n, .sysfs_name = s, .ldlat = l, .aux_event = a } struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX] = { - E("ldlat-loads", "cpu/mem-loads,ldlat=%u/P", "cpu/events/mem-loads"), - E("ldlat-stores", "cpu/mem-stores/P", "cpu/events/mem-stores"), - E(NULL, NULL, NULL), + E("ldlat-loads", "%s/mem-loads/,ldlat=%u/P", "cpu/events/mem-loads", true, 0), + E("ldlat-stores", "%s/mem-stores/P", "cpu/events/mem-stores", false, 0), + E(NULL, NULL, NULL, false, 0), }; #undef E static char mem_loads_name[100]; -static bool mem_loads_name__init; +static char mem_stores_name[100]; struct perf_mem_event *perf_mem_events__ptr(struct perf_pmu *pmu, int i) { @@ -62,23 +62,45 @@ struct perf_pmu *perf_mem_events_find_pmu(void) return perf_pmus__scan_mem(NULL); } -const char * __weak perf_mem_events__name(int i, const char *pmu_name __maybe_unused) +static const char *perf_mem_events__name(int i, struct perf_pmu *pmu) { - struct perf_mem_event *e = &perf_mem_events[i]; + struct perf_mem_event *e = &pmu->mem_events[i]; if (!e) return NULL; - if (i == PERF_MEM_EVENTS__LOAD) { - if (!mem_loads_name__init) { - mem_loads_name__init = true; - scnprintf(mem_loads_name, sizeof(mem_loads_name), - e->name, perf_mem_events__loads_ldlat); + if (i == PERF_MEM_EVENTS__LOAD || i == PERF_MEM_EVENTS__LOAD_STORE) { + if (e->ldlat) { + if (!e->aux_event) { + /* ARM and Most of Intel */ + scnprintf(mem_loads_name, sizeof(mem_loads_name), + e->name, pmu->name, + perf_mem_events__loads_ldlat); + } else { + /* Intel with mem-loads-aux event */ + scnprintf(mem_loads_name, sizeof(mem_loads_name), + e->name, pmu->name, pmu->name, + perf_mem_events__loads_ldlat); + } + } else { + if (!e->aux_event) { + /* AMD and POWER */ + scnprintf(mem_loads_name, sizeof(mem_loads_name), + e->name, pmu->name); + } else + return NULL; } + return mem_loads_name; } - return e->name; + if (i == PERF_MEM_EVENTS__STORE) { + scnprintf(mem_stores_name, sizeof(mem_stores_name), + e->name, pmu->name); + return mem_stores_name; + } + + return NULL; } __weak bool is_mem_loads_aux_event(struct evsel *leader __maybe_unused) @@ -175,7 +197,7 @@ void perf_mem_events__list(struct perf_pmu *pmu) e->tag ? 13 : 0, e->tag ? : "", e->tag && verbose > 0 ? 25 : 0, - e->tag && verbose > 0 ? perf_mem_events__name(j, NULL) : "", + e->tag && verbose > 0 ? perf_mem_events__name(j, pmu) : "", e->supported ? ": available\n" : ""); } } @@ -198,15 +220,15 @@ int perf_mem_events__record_args(const char **rec_argv, int *argv_nr, if (!e->supported) { pr_err("failed: event '%s' not supported\n", - perf_mem_events__name(j, pmu->name)); + perf_mem_events__name(j, pmu)); return -1; } if (perf_pmus__num_mem_pmus() == 1) { rec_argv[i++] = "-e"; - rec_argv[i++] = perf_mem_events__name(j, NULL); + rec_argv[i++] = perf_mem_events__name(j, pmu); } else { - const char *s = perf_mem_events__name(j, pmu->name); + const char *s = perf_mem_events__name(j, pmu); if (!perf_mem_event__supported(mnt, pmu, e)) continue; diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h index 59a4303aac96..d257cf67d6d9 100644 --- a/tools/perf/util/mem-events.h +++ b/tools/perf/util/mem-events.h @@ -14,6 +14,8 @@ struct perf_mem_event { bool record; bool supported; + bool ldlat; + u32 aux_event; const char *tag; const char *name; const char *sysfs_name; @@ -39,7 +41,6 @@ extern struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX]; int perf_mem_events__parse(struct perf_pmu *pmu, const char *str); int perf_mem_events__init(struct perf_pmu *pmu); -const char *perf_mem_events__name(int i, const char *pmu_name); struct perf_mem_event *perf_mem_events__ptr(struct perf_pmu *pmu, int i); struct perf_pmu *perf_mem_events_find_pmu(void); bool is_mem_loads_aux_event(struct evsel *leader); From patchwork Wed Dec 6 20:13:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 174724 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4354038vqy; Wed, 6 Dec 2023 12:14:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IHsWEtRLN//9QSwYzmRpMDKm0QU+DCjV0csAGdvRLf+U7BDh6nnr1k/aQbuHbXvw/z9vrd/ X-Received: by 2002:a17:902:ea86:b0:1d0:7d0b:555c with SMTP id x6-20020a170902ea8600b001d07d0b555cmr1554169plb.10.1701893654649; Wed, 06 Dec 2023 12:14:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701893654; cv=none; d=google.com; s=arc-20160816; b=fZfrcQOvrYV+7XNHQWicqyoFc4H4E4iCPnHhNRNPNZiDacFUo0vxEIxBRugJY8nxDv qgkW9DQ31Cfk4fiLvLRS3tkX/5s/Bm5rCmE4C6M5vOzFIdSOMrXReYrPcQsmmTDqKjxi PCO3G3Emcywoc1y7bOO4iF/PCMaTUtvKPR91qsNMeMygDmpvJFWydPC3nwEYC0pujVjJ tVOMGiwJgkHpSeKnG2c+CNqu8/6JdEdvQ10RUJ1t4QDcFjHizFHFSFtqK9Qi6st9JoSv UW1+c0PPdtFoOcx8qdx1gJWx/EolDonYeTmWFNvi8AMz8G3/IDlDg55t1YjjwtkwOLJ9 2igA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vnXZDiXETaBCzfkzQqHcWzXVxZlL24qIpofv7QzNfRM=; fh=GS69O/4cJpYi1pSOvxmc2ttdZCZHkrRB3QAP1aeELJ0=; b=Y+KthRqwql5TFvrace+QR/cqv4bc+IrZXfgPSgNnsQgvB4kj61arYW3bA+QIeOfaxE UA0Ym/OqeCZQWCQH/HNeUCf3+xCrS1c3MDO4YKemOFSft39AQO/CBdx18vyx5ZgDAcyM Qk44OljzyflAZYhZI8wb8/O3CyAOwiv9AppXiIFJpv/CNm+WHcn0NBft3daJmsAcTtC4 RQbvUvGzUkdl+4/pf8+mkq2RnmkO/lsVCCBVpaDkZujanL/QyG91wWpNO6n5DQOEqlvI QRoCp1JH8ds3LfXBCXsAo2T15uimlm5sJUSxUFr10tZBgTmjv+Twy2II+0zrnUHqV82x mxfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=IZIS0aVV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id i2-20020a170902eb4200b001cfda41727esi295491pli.509.2023.12.06.12.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 12:14:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=IZIS0aVV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 5A0858026D93; Wed, 6 Dec 2023 12:14:11 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442910AbjLFUNh (ORCPT + 99 others); Wed, 6 Dec 2023 15:13:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442872AbjLFUNa (ORCPT ); Wed, 6 Dec 2023 15:13:30 -0500 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1BC3D47; Wed, 6 Dec 2023 12:13:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701893615; x=1733429615; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5x40I8ig7vpMobv4oy8YoykaQ1KVI1NUCMksf5v/Ic0=; b=IZIS0aVVULqA1q5kD8PlGBrcOVjz4/IiKCzhd3hQuVy6NSQbMyl99Rjg Nxtu7MLp2erJROUnlDRwTob24dnVMWcN5UVbGATYE6FLiMY64nzAMlSMr kSt7RbgFwTL34B0kpAo6p34+8zNXpAyl2wDsAQilIN6HoEscKTwB9Kt/a TiLR50Ps3b4ShPkFx0YSqVktt2ts0VVzIUo9KYpAHhn1eUb5yLj7Pu0tl J28mYdInfrKUnaR7JAiwTMUw3JQi4L/MkiJN1Oc0AE9nu2QE1sJHvACVo Qw2pl+Gj/ZKKeej7pyckzLGf9g+wDXTqDYlPZp78Mne7dyvfJCrdq366C Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="458445576" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="458445576" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 12:13:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="944766678" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="944766678" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga005.jf.intel.com with ESMTP; 06 Dec 2023 12:13:32 -0800 From: kan.liang@linux.intel.com To: acme@kernel.org, irogers@google.com, peterz@infradead.org, mingo@redhat.com, namhyung@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, john.g.garry@oracle.com, will@kernel.org, james.clark@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, yuhaixin.yhx@linux.alibaba.com, renyu.zj@linux.alibaba.com, tmricht@linux.ibm.com, ravi.bangoria@amd.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Kan Liang Subject: [PATCH 4/6] perf mem: Clean up perf_mem_event__supported() Date: Wed, 6 Dec 2023 12:13:22 -0800 Message-Id: <20231206201324.184059-5-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231206201324.184059-1-kan.liang@linux.intel.com> References: <20231206201324.184059-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 06 Dec 2023 12:14:11 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784564841001434271 X-GMAIL-MSGID: 1784564841001434271 From: Kan Liang For some ARCHs, e.g., ARM and AMD, to get the availability of the mem-events, perf checks the existence of a specific PMU. For the other ARCHs, e.g., Intel and Power, perf has to check the existence of some specific events. The current perf only iterates the mem-events-supported PMUs. It's not required to check the existence of a specific PMU anymore. Rename sysfs_name to event_name, which stores the specific mem-events. Perf only needs to check those events for the availability of the mem-events. Signed-off-by: Kan Liang Reviewed-by: Ian Rogers --- tools/perf/arch/arm64/util/mem-events.c | 8 ++++---- tools/perf/arch/powerpc/util/mem-events.c | 8 ++++---- tools/perf/arch/x86/util/mem-events.c | 20 ++++++++++---------- tools/perf/util/mem-events.c | 16 +++++++++------- tools/perf/util/mem-events.h | 2 +- 5 files changed, 28 insertions(+), 26 deletions(-) diff --git a/tools/perf/arch/arm64/util/mem-events.c b/tools/perf/arch/arm64/util/mem-events.c index eb2ef84f0fc8..590dddd6b0ab 100644 --- a/tools/perf/arch/arm64/util/mem-events.c +++ b/tools/perf/arch/arm64/util/mem-events.c @@ -2,10 +2,10 @@ #include "map_symbol.h" #include "mem-events.h" -#define E(t, n, s, l, a) { .tag = t, .name = n, .sysfs_name = s, .ldlat = l, .aux_event = a } +#define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a } struct perf_mem_event perf_mem_events_arm[PERF_MEM_EVENTS__MAX] = { - E("spe-load", "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/", "arm_spe_0", true, 0), - E("spe-store", "%s/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/", "arm_spe_0", false, 0), - E("spe-ldst", "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/", "arm_spe_0", true, 0), + E("spe-load", "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/", NULL, true, 0), + E("spe-store", "%s/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/", NULL, false, 0), + E("spe-ldst", "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/", NULL, true, 0), }; diff --git a/tools/perf/arch/powerpc/util/mem-events.c b/tools/perf/arch/powerpc/util/mem-events.c index b7883e38950f..72a6ac2b52f5 100644 --- a/tools/perf/arch/powerpc/util/mem-events.c +++ b/tools/perf/arch/powerpc/util/mem-events.c @@ -2,10 +2,10 @@ #include "map_symbol.h" #include "mem-events.h" -#define E(t, n, s, l, a) { .tag = t, .name = n, .sysfs_name = s, .ldlat = l, .aux_event = a } +#define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a } struct perf_mem_event perf_mem_events_power[PERF_MEM_EVENTS__MAX] = { - E("ldlat-loads", "%s/mem-loads/", "cpu/events/mem-loads", false, 0), - E("ldlat-stores", "%s/mem-stores/", "cpu/events/mem-stores", false, 0), - E(NULL, NULL, NULL, false, 0), + E("ldlat-loads", "%s/mem-loads/", "mem-loads", false, 0), + E("ldlat-stores", "%s/mem-stores/", "mem-stores", false, 0), + E(NULL, NULL, NULL, false, 0), }; diff --git a/tools/perf/arch/x86/util/mem-events.c b/tools/perf/arch/x86/util/mem-events.c index f0e66a0151a0..b776d849fc64 100644 --- a/tools/perf/arch/x86/util/mem-events.c +++ b/tools/perf/arch/x86/util/mem-events.c @@ -9,24 +9,24 @@ #define MEM_LOADS_AUX 0x8203 -#define E(t, n, s, l, a) { .tag = t, .name = n, .sysfs_name = s, .ldlat = l, .aux_event = a } +#define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a } struct perf_mem_event perf_mem_events_intel[PERF_MEM_EVENTS__MAX] = { - E("ldlat-loads", "%s/mem-loads,ldlat=%u/P", "%s/events/mem-loads", true, 0), - E("ldlat-stores", "%s/mem-stores/P", "%s/events/mem-stores", false, 0), - E(NULL, NULL, NULL, false, 0), + E("ldlat-loads", "%s/mem-loads,ldlat=%u/P", "mem-loads", true, 0), + E("ldlat-stores", "%s/mem-stores/P", "mem-stores", false, 0), + E(NULL, NULL, NULL, false, 0), }; struct perf_mem_event perf_mem_events_intel_aux[PERF_MEM_EVENTS__MAX] = { - E("ldlat-loads", "{%s/mem-loads-aux/,%s/mem-loads,ldlat=%u/}:P", "%s/events/mem-loads", true, MEM_LOADS_AUX), - E("ldlat-stores", "%s/mem-stores/P", "%s/events/mem-stores", false, 0), - E(NULL, NULL, NULL, false, 0), + E("ldlat-loads", "{%s/mem-loads-aux/,%s/mem-loads,ldlat=%u/}:P", "mem-loads", true, MEM_LOADS_AUX), + E("ldlat-stores", "%s/mem-stores/P", "mem-stores", false, 0), + E(NULL, NULL, NULL, false, 0), }; struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX] = { - E(NULL, NULL, NULL, false, 0), - E(NULL, NULL, NULL, false, 0), - E("mem-ldst", "%s//", "ibs_op", false, 0), + E(NULL, NULL, NULL, false, 0), + E(NULL, NULL, NULL, false, 0), + E("mem-ldst", "%s//", NULL, false, 0), }; bool is_mem_loads_aux_event(struct evsel *leader) diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 3a60cbcd6d8e..9ea9e9a868c4 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -17,12 +17,12 @@ unsigned int perf_mem_events__loads_ldlat = 30; -#define E(t, n, s, l, a) { .tag = t, .name = n, .sysfs_name = s, .ldlat = l, .aux_event = a } +#define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a } struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX] = { - E("ldlat-loads", "%s/mem-loads/,ldlat=%u/P", "cpu/events/mem-loads", true, 0), - E("ldlat-stores", "%s/mem-stores/P", "cpu/events/mem-stores", false, 0), - E(NULL, NULL, NULL, false, 0), + E("ldlat-loads", "%s/mem-loads/,ldlat=%u/P", "mem-loads", true, 0), + E("ldlat-stores", "%s/mem-stores/P", "mem-stores", false, 0), + E(NULL, NULL, NULL, false, 0), }; #undef E @@ -150,12 +150,14 @@ int perf_mem_events__parse(struct perf_pmu *pmu, const char *str) static bool perf_mem_event__supported(const char *mnt, struct perf_pmu *pmu, struct perf_mem_event *e) { - char sysfs_name[100]; char path[PATH_MAX]; struct stat st; - scnprintf(sysfs_name, sizeof(sysfs_name), e->sysfs_name, pmu->name); - scnprintf(path, PATH_MAX, "%s/devices/%s", mnt, sysfs_name); + if (!e->event_name) + return true; + + scnprintf(path, PATH_MAX, "%s/devices/%s/events/%s", mnt, pmu->name, e->event_name); + return !stat(path, &st); } diff --git a/tools/perf/util/mem-events.h b/tools/perf/util/mem-events.h index d257cf67d6d9..d2875d731da8 100644 --- a/tools/perf/util/mem-events.h +++ b/tools/perf/util/mem-events.h @@ -18,7 +18,7 @@ struct perf_mem_event { u32 aux_event; const char *tag; const char *name; - const char *sysfs_name; + const char *event_name; }; struct mem_info { From patchwork Wed Dec 6 20:13:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 174721 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4353923vqy; Wed, 6 Dec 2023 12:14:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IGGw4M8nEFf1CB7jDv7SzrxFuGeHSRQ+xFh1pxspI5WmyU9Ng4d+jyif/accPxwHZzJ8Yvh X-Received: by 2002:a17:90a:68c4:b0:286:6cc1:8670 with SMTP id q4-20020a17090a68c400b002866cc18670mr1129754pjj.85.1701893643060; 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[2620:137:e000::3:1]) by mx.google.com with ESMTPS id gt7-20020a17090af2c700b002806cdeecc6si370261pjb.35.2023.12.06.12.14.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 12:14:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Rm4RPvVD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id A60AA82A177F; Wed, 6 Dec 2023 12:14:00 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442872AbjLFUNk (ORCPT + 99 others); Wed, 6 Dec 2023 15:13:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442887AbjLFUNc (ORCPT ); Wed, 6 Dec 2023 15:13:32 -0500 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22FA41A5; Wed, 6 Dec 2023 12:13:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701893617; x=1733429617; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sDPNIp9IXTZNk2JbRgBfRXncy7cROcPc5+X7nvCxRM0=; b=Rm4RPvVD9f7MNq5+3vW8wb7VqF5AYzvL+Z6lUVqLgQhAkHtPTdazcJgf YxhDk7MPMuwWCzdNwRhqdZzpS8H+BuhvYfHTHrXy1QoIWbjR0ftm+nRmS yBn7zfGdFKQiOHb430mSlTMosclqiegcF2pI7PI3Ukwvca0QfosQkcOGw y5QfcUvY7kngAvgSru80A4ouTnI9ZSCrTIrPtGO+2xNOqOjI3ekPVpWvP 6wNOCowXVBcUhRIcrDLBuHxTxJI9pVHs4pBQOYKx/fiRLT8R6EME3XZs1 +TQG7oivcsqibRik73IkdV00F/DC/B9oVrqIMiwe604t+CK3Q5AmFMlic A==; X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="458445588" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="458445588" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 12:13:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="944766683" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="944766683" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga005.jf.intel.com with ESMTP; 06 Dec 2023 12:13:32 -0800 From: kan.liang@linux.intel.com To: acme@kernel.org, irogers@google.com, peterz@infradead.org, mingo@redhat.com, namhyung@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, john.g.garry@oracle.com, will@kernel.org, james.clark@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, yuhaixin.yhx@linux.alibaba.com, renyu.zj@linux.alibaba.com, tmricht@linux.ibm.com, ravi.bangoria@amd.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Kan Liang Subject: [PATCH 5/6] perf mem: Clean up is_mem_loads_aux_event() Date: Wed, 6 Dec 2023 12:13:23 -0800 Message-Id: <20231206201324.184059-6-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231206201324.184059-1-kan.liang@linux.intel.com> References: <20231206201324.184059-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 06 Dec 2023 12:14:00 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784564828437449715 X-GMAIL-MSGID: 1784564828437449715 From: Kan Liang The aux_event can be retrieved from the perf_pmu now. Implement a generic support. Signed-off-by: Kan Liang Reviewed-by: Ian Rogers --- tools/perf/arch/x86/util/mem-events.c | 13 ------------- tools/perf/util/mem-events.c | 14 ++++++++++++-- 2 files changed, 12 insertions(+), 15 deletions(-) diff --git a/tools/perf/arch/x86/util/mem-events.c b/tools/perf/arch/x86/util/mem-events.c index b776d849fc64..71ffe16de751 100644 --- a/tools/perf/arch/x86/util/mem-events.c +++ b/tools/perf/arch/x86/util/mem-events.c @@ -28,16 +28,3 @@ struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX] = { E(NULL, NULL, NULL, false, 0), E("mem-ldst", "%s//", NULL, false, 0), }; - -bool is_mem_loads_aux_event(struct evsel *leader) -{ - struct perf_pmu *pmu = perf_pmus__find("cpu"); - - if (!pmu) - pmu = perf_pmus__find("cpu_core"); - - if (pmu && !perf_pmu__have_event(pmu, "mem-loads-aux")) - return false; - - return leader->core.attr.config == MEM_LOADS_AUX; -} diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 9ea9e9a868c4..336d1109b3a5 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -103,9 +103,19 @@ static const char *perf_mem_events__name(int i, struct perf_pmu *pmu) return NULL; } -__weak bool is_mem_loads_aux_event(struct evsel *leader __maybe_unused) +bool is_mem_loads_aux_event(struct evsel *leader) { - return false; + struct perf_pmu *pmu = leader->pmu; + struct perf_mem_event *e; + + if (!pmu || !pmu->mem_events) + return false; + + e = &pmu->mem_events[PERF_MEM_EVENTS__LOAD]; + if (!e->aux_event) + return false; + + return leader->core.attr.config == e->aux_event; } int perf_mem_events__parse(struct perf_pmu *pmu, const char *str) From patchwork Wed Dec 6 20:13:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 174723 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4354013vqy; Wed, 6 Dec 2023 12:14:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IHUsETtkh8XLhJiQY1+fsfYLrnklOK83zHhFRP+ssjLOpDEFFQNMmkwxi4/ZjoZ1w/lI9HU X-Received: by 2002:a05:6a20:9387:b0:18c:19ab:d2e5 with SMTP id x7-20020a056a20938700b0018c19abd2e5mr1393090pzh.33.1701893652598; Wed, 06 Dec 2023 12:14:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701893652; cv=none; d=google.com; s=arc-20160816; b=itClB7p+MkPuwCFpFN5XweNS1JmWY5J57wP0hvhefB1uJNNN9QYJW/OsiETNE83SWI dAY5Bc0tUBxYiwgFSVUIHiafObmDYHa+9HvpIsaJmZw+WiJDylK4JHTE53gWoR8rLxH+ wJ+5a+gNaVdTvCdIo5oLi2NkU8yukhEYoRsVrT0kMlOSYSIp5sHN+B724XhjC4xz80W+ 0LBMoKDLPmtZyDtOaQQIO9pyKs+taDvKx2hkpfoXiYboTW6C0bzwiBnltJsCWz6q/8gT MlJ4hzx6e0b2gBrU7S1hi7dA1lUbG2I7dC7RXnkD2lx5o4VKT6RuHxZiRUy1wKB66D3p cHww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=d+oiHRHmb30t+xAzMGRpEoc7hdXVdoGReA7GKXG/eoM=; fh=GS69O/4cJpYi1pSOvxmc2ttdZCZHkrRB3QAP1aeELJ0=; b=rDz2wu8B5A6CYbPHrE2V9FWVnbBdc97FBYhEvOyH9gAm85awa4i9ptHreN6X16/7Co vpz0a+Cb7YPrDY5GiVV7irJjwJ0mTWoH+CBccjjKtcb3IFG2YsRXfRghzaDlLh8WjyvJ C3C/hnDMyYiOdaquXtznHZ5hDOfbme1pHPzbmx6VVKZ9bfqvRBaRbBUg75kQJgS/F+Tv TOM0XsrqQw60agoRVmyl841vm6JcN75t+Gwo/ohZrZEnKC8fTu2iCF+teNSRsMGi5Myh OCNZPkN7CWcsssX7IMdFvWQHbEDW8haZBPM5DVmWe1ORjYvZPTceMFzHQtHv0tRn68K0 rvdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=f77V06k7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id cn6-20020a056a020a8600b005c2791fedb1si401831pgb.874.2023.12.06.12.14.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 12:14:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=f77V06k7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 597E880236C0; Wed, 6 Dec 2023 12:14:08 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379539AbjLFUNp (ORCPT + 99 others); Wed, 6 Dec 2023 15:13:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442892AbjLFUNc (ORCPT ); Wed, 6 Dec 2023 15:13:32 -0500 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C7D8D62; Wed, 6 Dec 2023 12:13:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701893617; x=1733429617; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xauO0p/GUkiGEzh2PvYpS4cwj2BY8SDJavt28LY2Q5I=; b=f77V06k7BtsDCeC0SzMUFOzmMDKmwqfls/HmbRr1E+plkpMQWRBywgZY yo5NUhIM/n3fN21gnORCoOX5JV+QPIuShPo7c7DNmrsYglw+Y3BFXLMZp O9RMIpF4VU+PHxNqJixg36g6en89haG+t2HmX0EZJ/uYsqOpFLrzamHmB GtSH7kwXUeueOOfHyukO0Zr5cV1l2dc7vWHIXkmjTXZeaB6YNT2x5Ewgw wat1Mo7itMC4tPO3+MMyg361SRlxvIyJBRxWAKYVT/1M3Drem1VlnBQPB eylrv8k8bIe74a0qbZgm2g2FL93ApcfG/3Y67UJL1LUNpnzbh+eflu9C1 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="458445601" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="458445601" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 12:13:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10916"; a="944766687" X-IronPort-AV: E=Sophos;i="6.04,256,1695711600"; d="scan'208";a="944766687" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga005.jf.intel.com with ESMTP; 06 Dec 2023 12:13:32 -0800 From: kan.liang@linux.intel.com To: acme@kernel.org, irogers@google.com, peterz@infradead.org, mingo@redhat.com, namhyung@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, john.g.garry@oracle.com, will@kernel.org, james.clark@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, yuhaixin.yhx@linux.alibaba.com, renyu.zj@linux.alibaba.com, tmricht@linux.ibm.com, ravi.bangoria@amd.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Kan Liang Subject: [PATCH 6/6] perf mem: Remove useless header files for X86 Date: Wed, 6 Dec 2023 12:13:24 -0800 Message-Id: <20231206201324.184059-7-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231206201324.184059-1-kan.liang@linux.intel.com> References: <20231206201324.184059-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 06 Dec 2023 12:14:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784564838873629473 X-GMAIL-MSGID: 1784564838873629473 From: Kan Liang The X86 mem-events.c only has perf_mem_events array now. Remove useless header files. Signed-off-by: Kan Liang --- tools/perf/arch/x86/util/mem-events.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/tools/perf/arch/x86/util/mem-events.c b/tools/perf/arch/x86/util/mem-events.c index 71ffe16de751..62df03e91c7e 100644 --- a/tools/perf/arch/x86/util/mem-events.c +++ b/tools/perf/arch/x86/util/mem-events.c @@ -1,11 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 -#include "util/pmu.h" -#include "util/pmus.h" -#include "util/env.h" -#include "map_symbol.h" -#include "mem-events.h" #include "linux/string.h" -#include "env.h" +#include "util/map_symbol.h" +#include "util/mem-events.h" +#include "mem-events.h" + #define MEM_LOADS_AUX 0x8203