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[23.128.96.36]) by mx.google.com with ESMTPS id f18-20020a170902e99200b001d080c0e21fsi6772072plb.632.2023.12.06.06.51.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 06:51:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=sntech.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 5BC3A81A7D01; Wed, 6 Dec 2023 06:51:06 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442161AbjLFOux (ORCPT + 99 others); Wed, 6 Dec 2023 09:50:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442127AbjLFOuv (ORCPT ); Wed, 6 Dec 2023 09:50:51 -0500 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB414D49; Wed, 6 Dec 2023 06:50:55 -0800 (PST) Received: from i53875b61.versanet.de ([83.135.91.97] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rAtEe-0002nV-3l; Wed, 06 Dec 2023 15:50:48 +0100 From: Heiko Stuebner To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, heiko@sntech.de, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, quentin.schulz@theobroma-systems.com, Heiko Stuebner Subject: [PATCH] dt-bindings: PCI: dwc: rockchip: document optional pcie reference clock input Date: Wed, 6 Dec 2023 15:50:41 +0100 Message-Id: <20231206145041.667900-1-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:51:06 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784544521871013820 X-GMAIL-MSGID: 1784544521871013820 From: Heiko Stuebner On some boards the 100MHz PCIe reference clock to both controller and devices is controllable. Add that clock to the list of clocks. The clock is optional, so the minItems stays the same. Signed-off-by: Heiko Stuebner Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 1ae8dcfa072c..5f719218c472 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -49,6 +49,7 @@ properties: - description: APB clock for PCIe - description: Auxiliary clock for PCIe - description: PIPE clock + - description: Reference clock for PCIe clock-names: minItems: 5 @@ -59,6 +60,7 @@ properties: - const: pclk - const: aux - const: pipe + - const: ref interrupts: items: