From patchwork Wed Dec 6 14:41:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 174607 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4151473vqy; Wed, 6 Dec 2023 06:44:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IFgdMmCQ9qnvI5asGplLaso1NrzdX0MfQsscQ0ijjNQFJSaz1DdO6GlnHiyStX/TnHJ7vJK X-Received: by 2002:a05:6358:e4a5:b0:170:6ed7:2b9c with SMTP id by37-20020a056358e4a500b001706ed72b9cmr430159rwb.21.1701873875372; Wed, 06 Dec 2023 06:44:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701873875; cv=none; d=google.com; s=arc-20160816; b=ljvLiPGxDaclWALgX+P1Mp36t7kr0r0ATWndKzP+no1zPz6HqgrV/xtsCSwtObLHKa LO2evcmKqX/Q6jS3MvTqxkFsiYRknL+Q0a2AeNlZN+NVCr8zs6rg3sby5+o2Ztp73c6Z lOU4QhJ/qy6Y/VJzSHR0b/V2RqEVb3nQkWHtdWRAe5+MCkyLVb7dB9Kn42oV7o+4fCEo XB96Y0w/oZo4R9SEABQN9f+mUXi0YvTJ8tHzNORV3gheEueys1ydag5KrPhBc8EF1Qz7 fP4c4dGmeSlwPlu1V6IYBP7XOBOODFlrWaNRQcR70dhI7rHKeoktWHBiIYDjUvzqLY8o PORw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZNb5mGtHz1UeWfUC79dgVMDzRbY7b/tvjIXIDYkEZss=; fh=ltYwvILgD5pj0Rly1blr/5KGxhpSp2Y+0x4fOITKRXI=; b=XcRfV6dxPNb6biNWEvqZZVhiwNzumiJpmGxWyCsrC/Uu1Kk34ys9T4B+m1r4kBjCWV VGdq+qUN9MUCRtWEOZVKlZMArUbePRdBV8Vb9PoD0K2rGcCxohJRXtireiPCDPNZINX8 FmP3YpguK+75IbkkF6wZWDv49vMEFGQ5JTc7wAQv4iSaQYhPdGF4f6zAy+3o3Qq3lMih 0VAUj1LFrKkELTSEMtyqRGTzSoqQlKDThuGrlob+Y9QTWkbb/cNs/gFG+RSJSqzXnpLM RSoD0oOHu1mC1MHN9ljpQmydcu9uhWRY0r1vlE9pgQ4vtsytuEz/J7QuC8pi2eqmop1f XE/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=JrKJwofq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id p4-20020a634204000000b005c658bf30aasi4932pga.412.2023.12.06.06.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 06:44:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=JrKJwofq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 59E9D80294DC; Wed, 6 Dec 2023 06:44:34 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379006AbjLFOoX (ORCPT + 99 others); Wed, 6 Dec 2023 09:44:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378978AbjLFOoW (ORCPT ); Wed, 6 Dec 2023 09:44:22 -0500 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49025D4B; Wed, 6 Dec 2023 06:44:27 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2C388C0131; Wed, 6 Dec 2023 15:44:24 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873864; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ZNb5mGtHz1UeWfUC79dgVMDzRbY7b/tvjIXIDYkEZss=; b=JrKJwofqVfNgFuFtuUXKuPJizfwinPAMvh+r6cvsIHCksvxfV2eQ983vVXcNeqoIChyMyz KaeRn08igBAvXK2tqgTlsgeENTx7n1HuVdTN7YCm2EaChInWi7NOf9vEfdGzoFRBwFBBUb BWHxUl8FzybRLpg33dY+PHnduCYypZAYHZwOl9uJBmptwp3HLxSymat9S5vZzSkVjtWrEL B6Umf1omFpwYjEgcD+Z1TRWy8xzaBkRsjNKbDw2zqdBicjckNpM2j40Nt41bF/twSij/qH ROmTAcvgP8PPdIa6OImesReRjojxA1OLm5FEgGfA0KDhCG3D59+QYkIJ+6wDTA== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 01/14] arm64: dts: imx8mm-kontron: Add support for display bridges on BL i.MX8MM Date: Wed, 6 Dec 2023 15:41:04 +0100 Message-ID: <20231206144201.46911-2-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:44:34 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784544100804789949 X-GMAIL-MSGID: 1784544100804789949 From: Frieder Schrempf The Kontron Electronics BL i.MX8MM has oboard disply bridges for DSI->HDMI and DSI->LVDS conversion. The DSI interface is muxed by a GPIO-controlled switch to one of these two bridges. By default the HDMI bridge is enabled. The LVDS bridge can be selected by loading an additional (panel-specific) overlay. Signed-off-by: Frieder Schrempf --- Changes for v3: * Address Shawn's review comments (thanks!) Changes for v2: * Rework DSI mux GPIO logic to be compatible with overlay * Switch from 4 to 2 DSI lanes for LVDS bridge to fix non-working display --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 160 ++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index dcec57c20399e..a0f0be3f104fb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -25,6 +25,17 @@ osc_can: clock-osc-can { clock-output-names = "osc-can"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_in_conn: endpoint { + remote-endpoint = <&bridge_out_conn>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -132,6 +143,104 @@ ethphy: ethernet-phy@0 { }; }; +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + + dsi_mux_sel_hdmi: dsi-mux-sel-hdmi-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "dsi-mux-sel"; + }; + + dsi_mux_sel_lvds: dsi-mux-sel-lvds-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "dsi-mux-sel"; + status = "disabled"; + }; + + dsi-mux-oe-hog { + gpio-hog; + gpios = <15 GPIO_ACTIVE_LOW>; + output-high; + line-name = "dsi-mux-oe"; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + hdmi: hdmi@39 { + compatible = "adi,adv7535"; + reg = <0x39>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adv7535>; + + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + + adi,dsi-lanes = <4>; + + a2vdd-supply = <®_vdd_1v8>; + avdd-supply = <®_vdd_1v8>; + dvdd-supply = <®_vdd_1v8>; + pvdd-supply = <®_vdd_1v8>; + v1p2-supply = <®_vdd_1v8>; + v3p3-supply = <®_vdd_3v3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in_dsi_hdmi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + }; + }; + + port@1 { + reg = <1>; + + bridge_out_conn: endpoint { + remote-endpoint = <&hdmi_in_conn>; + }; + }; + }; + }; + + lvds: bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sn65dsi84>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in_dsi_lvds: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <1 2>; + }; + }; + }; + }; +}; + &i2c4 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -144,6 +253,30 @@ rx8900: rtc@32 { }; }; +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <54000000>; + /* + * Let the driver calculate an appropriate clock rate based on the pixel + * clock instead of using the fixed value from imx8mm.dtsi. + */ + /delete-property/ samsung,pll-clock-frequency; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out_bridge: endpoint { + remote-endpoint = <&bridge_in_dsi_hdmi>; + }; + }; + }; +}; + &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; @@ -207,6 +340,12 @@ &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio>; + pinctrl_adv7535: adv7535grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 + >; + }; + pinctrl_can: cangrp { fsl,pins = < MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 @@ -277,6 +416,20 @@ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 >; }; + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -290,6 +443,13 @@ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 >; }; + pinctrl_sn65dsi84: sn65dsi84grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x19 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 From patchwork Wed Dec 6 14:41:05 2023 Content-Type: text/plain; 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[23.128.96.34]) by mx.google.com with ESMTPS id t20-20020a17090ae51400b0028649cc70b2si10801040pjy.14.2023.12.06.06.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 06:44:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=cyd8vAXB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 4A68A8328AE4; Wed, 6 Dec 2023 06:44:41 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379054AbjLFOo3 (ORCPT + 99 others); Wed, 6 Dec 2023 09:44:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379049AbjLFOoY (ORCPT ); Wed, 6 Dec 2023 09:44:24 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 882419A; Wed, 6 Dec 2023 06:44:30 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DD368C018E; Wed, 6 Dec 2023 15:44:27 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873868; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Hndc5GdbsWYNRG+SAYE5hHf0spaPTonGByAkploGSR8=; b=cyd8vAXBZHYzmCyKtL9YMcD5n7B3sPxzqb+tPMvDyrT8Z3EgJRhrdWmVlOVNHqyWkwAPut h7DT4mQmeWxF/zzy/S4K9P8S8e0ja5TzURPQ7fbYm3m5FHyCrd2fMqSe5smcbuIyGReikG xkcBKyh5SbYDDyJscFpUCTkDsjwCa9v89YavLc5Olr0GSH1iDOH1vYIjfJGQGyig5CNjhS ArBTbKLTGNc9vNU4QjgXGmzMjc8KnorzhoJQz1RGiSaqDqNJ7CMB36c9uOjnhTLjQ7A2TN qbz/8SdAfjLq63yg+nRdDz1QQBCHLeVPjN7Fxl8EXyxiZ3JgdmCd4YeVTtNdiQ== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Alexander Stein , Fabio Estevam , Gregor Herburger , Marcel Ziswiler , Marek Vasut , NXP Linux Team , Pengutronix Kernel Team , Philippe Schenker , Tim Harvey Subject: [PATCH v3 02/14] arm64: dts: imx8mm-kontron: Add DL (Display-Line) overlay with LVDS support Date: Wed, 6 Dec 2023 15:41:05 +0100 Message-ID: <20231206144201.46911-3-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:44:41 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784544115886648386 X-GMAIL-MSGID: 1784544115886648386 From: Frieder Schrempf The Kontron Electronics DL i.MX8MM consists of the BL i.MX8MM board and a 7" LVDS panel. Provide an overlay that enables the panel. Signed-off-by: Frieder Schrempf --- Changes for v3: * Address Shawn's review comments (thanks!) Changes for v2: * Rework DSI mux GPIO logic to be compatible with overlay --- arch/arm64/boot/dts/freescale/Makefile | 4 + .../boot/dts/freescale/imx8mm-kontron-dl.dtso | 201 ++++++++++++++++++ 2 files changed, 205 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 300049037eb0b..e08024797721a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -166,6 +166,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb +imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb + imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso b/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso new file mode 100644 index 0000000000000..6784bea857c00 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Kontron Electronics GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include "imx8mm-pinfunc.h" + +&{/} { + compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000 0>; + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <100>; + }; + + panel { + compatible = "panel-lvds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + backlight = <&backlight>; + data-mapping = "vesa-24"; + enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + height-mm = <86>; + width-mm = <154>; + + panel-timing { + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hsync-len = <1>; + hfront-porch = <160>; + hback-porch = <160>; + vsync-len = <1>; + vfront-porch = <12>; + vback-porch = <23>; + }; + + port { + panel_out_bridge: endpoint { + remote-endpoint = <&bridge_out_panel>; + }; + }; + }; +}; + +&dsi_mux_sel_hdmi { + status = "disabled"; +}; + +&dsi_mux_sel_lvds { + status = "okay"; +}; + +&dsi_out_bridge { + remote-endpoint = <&bridge_in_dsi_lvds>; +}; + +&gpio3 { + panel_rst { + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "panel-reset"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_rst>; + }; + + panel_stby { + gpio-hog; + gpios = <21 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "panel-standby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_stby>; + }; + + panel_hinv { + gpio-hog; + gpios = <24 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "panel-horizontal-invert"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_hinv>; + }; + + panel_vinv { + gpio-hog; + gpios = <25 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "panel-vertical-invert"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_vinv>; + }; +}; + +&hdmi { + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + gt911@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio3>; + interrupts = <22 8>; + reset-gpios = <&gpio3 23 0>; + irq-gpios = <&gpio3 22 0>; + }; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 + >; + }; + + pinctrl_panel_hinv: panelhinvgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 + >; + }; + + pinctrl_panel_rst: panelrstgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 + >; + }; + + pinctrl_panel_stby: panelstbygrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 + >; + }; + + pinctrl_panel_vinv: panelvinvgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 + >; + }; +}; From patchwork Wed Dec 6 14:41:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 175199 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4844739vqy; Thu, 7 Dec 2023 07:07:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IHpkQCqKM4zuMjmHgVp4fs8mlJB0pJFKDsbW36cmMhJAZmWhfkjJZY7wIOw/jVOgN8RT09W X-Received: by 2002:a17:902:ce8a:b0:1d0:9162:75fb with SMTP id f10-20020a170902ce8a00b001d0916275fbmr3348474plg.0.1701961654307; Thu, 07 Dec 2023 07:07:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701961654; 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[23.128.96.34]) by mx.google.com with ESMTPS id j2-20020a170902da8200b0019c354055d0si1305766plx.304.2023.12.07.07.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 07:07:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=diSwOy9y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 2C98F8328AEA; Wed, 6 Dec 2023 06:44:53 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379082AbjLFOob (ORCPT + 99 others); Wed, 6 Dec 2023 09:44:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378978AbjLFOo0 (ORCPT ); Wed, 6 Dec 2023 09:44:26 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80AA0D50; Wed, 6 Dec 2023 06:44:32 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9839DBFD15; Wed, 6 Dec 2023 15:44:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873871; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=NkMKnEjwIGTkVluEw4nFhKYXxAKXw2JtUmP+2W0Q83E=; b=diSwOy9yZUei6M299O6MJLnYq/3SMDZOXAmm4xLzGKAe/JdM01/CeKDps0p5yJtcHKhiFn NHBAK8c5nSUdra3bC9w7amclupXt4LnH2EyR8BewvOqbXR7sOFteNJUxguwSgCcpB3td2B qPPAfLqQ1KrAkQrmcUGSF1ddRmHvZKhk7NWEin6yj+0sHONdg0fDzU+IcwG+crA0jwUeT6 BtbZ1Z4zVVHd8dYwunnrMVY8Zzcp/UhQoar/bUNy4795aKCkTELOGHNki8TbuVt63GXh3a XKx4rvgQ62KLEdCm1V01sdFriQSq48T8kYJ41Xuc74986uMw66RMGI+5F2po9g== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 03/14] arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on OSM-S i.MX8MM Date: Wed, 6 Dec 2023 15:41:06 +0100 Message-ID: <20231206144201.46911-4-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:44:53 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784636144058652236 X-GMAIL-MSGID: 1784636144058652236 From: Frieder Schrempf There are external pullup resistors on the board and due to silicon errata ERR050080 let's disable the internal ones to prevent any unwanted behavior in case they wear out. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-S") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts | 4 ++-- arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 8b16bd68576c0..0730c22e5b6b9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -294,8 +294,8 @@ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 pinctrl_i2c4: i2c4grp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 6e75ab879bf59..3e7db968f7e64 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -252,8 +252,8 @@ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083 >; }; From patchwork Wed Dec 6 14:41:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 174608 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4151613vqy; Wed, 6 Dec 2023 06:44:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IG6uen7JyZbT7nkStjUqFcUjDr2KqSXkow2zMc4XKIPYyGzmzwHa2qSnnRxavy4w8hlUI/Z X-Received: by 2002:a17:902:f80f:b0:1d0:6b76:3d61 with SMTP id ix15-20020a170902f80f00b001d06b763d61mr673063plb.58.1701873887006; Wed, 06 Dec 2023 06:44:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701873886; cv=none; d=google.com; s=arc-20160816; b=DelebgiWQVgDmGHfkPinUn+13HP9FgG4OPP8zDbh5CykmJ5Q69LQ4h9fxzCDbdgMmq W/cFvUKk8FMAIWYbcKDdWS2+v4yZnqa4usdS7kCn1ar1d6D2gwU3ESrglg2L55vTUpQr xH9I9XTx7ffPW8RirsRh4zH/sBrASKnSmE/Q6px0ioYa1MXsW1Bc4hgAdj5GMtYwoZv5 y3oz9KIRYgHNzaYPR7bkgq4UOYKCGPxUQ9YZMJbu/f79ZB/IS4TbHMOD0LPpnMExKUhC SNJC7LfUeEK1nQXUK9UkvAsL4KUUaJ+dSjKgPETlRrD2Bz5+rJCGwuXXt2xsLMWXEvpA L8KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pVj+CwTGyuX92NILB7TfCfvXVQCKdjB8BZSb9PIcYsg=; fh=mWDe8CjyAdhhjLFVNrKsiT00acIg4QHc0YGM2tZgom8=; b=B1RLDnB+xbvxD4BVwrv1GmBeBL/ZAawvSQw63mfLNLDA8rmogi3xKddeBw/Z4COWcB TlEIIxIgFQiYzFYQwCSUPhQkUeToA3l6D9Wc9F2uIFUfVZASgP5qz8yWKXcwT7xc8LNM VMFWs00VmJN6gpcESgNk8eOgTdzTYmllOxnzUAY+JMSHHzUWblJhamQnpNJKzlEwVhoe TuXUHLwz8KXdQlV8rtRq7KGcSWCbrCVYiCNCAv2j4h/mleHNL6Oox5werscERv2HrKTW BEQ0giuV59uv3aPtNbXmE2gom9EyQ666ihQxFTi8esYtAAjyFgcCYVqruOjeiuKBB1mq dxDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=k+axlHeK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id k5-20020a170902c40500b001c77674ea97si11783661plk.423.2023.12.06.06.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 06:44:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=k+axlHeK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 9E4168029261; Wed, 6 Dec 2023 06:44:45 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379069AbjLFOod (ORCPT + 99 others); Wed, 6 Dec 2023 09:44:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379064AbjLFOo3 (ORCPT ); Wed, 6 Dec 2023 09:44:29 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1863FD72; Wed, 6 Dec 2023 06:44:34 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EB777C0190; Wed, 6 Dec 2023 15:44:32 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873873; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=pVj+CwTGyuX92NILB7TfCfvXVQCKdjB8BZSb9PIcYsg=; b=k+axlHeKuImr6h2w6Buolj4EEEnx5vfX7QeW+af4zC+f3zQBU2FMOlH5sbzLFFehh9WSHZ 56hWDn+0rhA55pKTDpF+qLL9lhA5XxEYTiYnFsWzvBecMpftX+LYaEQlKRqcx1BswWwDin cYZc+hfSsWY1TIu0beeAB0cMiGmI/luma3iD4Gb113GcREoBHwZveNW2hY0lywM06jXJEQ j/J21t0qUh3dWLb4xYR6wDd5GWVeyFkspBFPeOMx/kJVwVDdICByrj6iVtLVOcb/0YRVjE X1oVL9iwmWVc3QUKRIX6LHoDnOuhnatoknuAz6r3bsTricHgsUtmLTtDT5SnXg== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 04/14] arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on SL/BL i.MX8MM Date: Wed, 6 Dec 2023 15:41:07 +0100 Message-ID: <20231206144201.46911-5-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_NEUTRAL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:44:45 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784544112958896699 X-GMAIL-MSGID: 1784544112958896699 From: Frieder Schrempf There are external pullup resistors on the board and due to silicon errata ERR050080 let's disable the internal ones to prevent any unwanted behavior in case they wear out. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts | 4 ++-- arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index a0f0be3f104fb..866f35d1633d4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -432,8 +432,8 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 pinctrl_i2c4: i2c4grp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi index 1f8326613ee9e..2076148e08627 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi @@ -237,8 +237,8 @@ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083 >; }; From patchwork Wed Dec 6 14:41:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 174610 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4151646vqy; Wed, 6 Dec 2023 06:44:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IGNbbPppBgKk1wWnLkjAAahdejhM6UOcxjmrmTOpAHUsBlMV2e7ka+CTeMyRW13gzKGoCvm X-Received: by 2002:a17:90b:1d07:b0:286:6cc1:3f15 with SMTP id on7-20020a17090b1d0700b002866cc13f15mr1026171pjb.76.1701873891276; Wed, 06 Dec 2023 06:44:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701873891; cv=none; d=google.com; s=arc-20160816; b=tgLUMflfSaiw9m1/AumCWhl+v6/UAtdF/EjFpUNK4abP5BG9LwSwa5FET/Z6kmDwYL xA7JpEG2BF/7Dq8X7cmyOBKIMeP2b6fWSxcgJn32f0tC7B4kLBbbWhugxsuaBL+m+Cds VNDeKecilcIi68rfkksFTJzLc2FSyIfG3/mhpZKBJRImqqQfCX0hiVn2lAdjhuKTBTs0 5e1StYNW2ijSSRKtWNlrTHHlwFPlN59nYFC/PwoVcL8tgP5+Gftq9yUVzyITnCpApzhw d7iQpp+HzY774cLINKmY/W+auMdoLR6L495tDDUjaD08imJWooauqAX6bh21/wNIIxLt N/EQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oeyirk30VzrJwXs/jPqp36nZYKhhaMWlQBYYBY4oDRg=; fh=5WBVB9KggvEUZrfL2cFjcxt7hrbLV0CECJcyvKKi3zA=; b=xG5FO5FA0kBrjHXJ/hOG9pn6nig5ZJJpuXlL5eSPR2s1pj+IbEDOtwbduAvUsiBk2W fH1gG/uJd/KrQMYrsqkfN/WI12Z61eMwGR0QHGSF23xayN7oxLcVP5fHNECBQd/UMNlN SpMO2bpovNBIttR3m/BbVJGEolyA26lESxqV8cI0i9VTUQrmAZzEZo7nWwyZBDJbIJZn OdCARQ4SfOcbO+7DJHGDaRa0kunvvQAbylR39XuvQTZafj29JKcUm4+vXdxoq2SlJWgm emcNRgGzrBIVDEUVIyEtGxhVZe8fBirARruO+Fky43DnzzBzk/PJqsU+4TjuU42MVjJ7 lcpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=g1WWld62; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id cl18-20020a17090af69200b00286e5da4d84si2707564pjb.158.2023.12.06.06.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 06:44:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=g1WWld62; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 479F080291F6; Wed, 6 Dec 2023 06:44:50 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379097AbjLFOog (ORCPT + 99 others); Wed, 6 Dec 2023 09:44:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379077AbjLFOob (ORCPT ); Wed, 6 Dec 2023 09:44:31 -0500 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98BFFD47; Wed, 6 Dec 2023 06:44:36 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7F65BC00E1; Wed, 6 Dec 2023 15:44:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873874; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=oeyirk30VzrJwXs/jPqp36nZYKhhaMWlQBYYBY4oDRg=; b=g1WWld62zYcSAD+OzHDUgIIPySaYHRHD3moakIVOl50tfEtz4AHpTg3qiaOCmnsPrKyPFf VaTRdD3cNAhcP0Kq2+UuHEdfWmi8LQAdGHsVNm+/FwgPQRWKPDcLn5wK5q3+hIj5Y6JJ5s cuopLKS4SH+Jml0QA/RatdtlCiRNK7Ir2QEr2QDu21oLcm9+0oiTo7ILG7qjt3DmQTc2Fg MhUn4XCSs5JXnCkGeU6gZqdn/EODiYEkrf1+n3EkfSy2E8DkEjNNZ1NWr+c8iCEa1E0kJP d7MYkrumx05ifhqit1q0Tfaa6I7h+NXixOgENGeqTZ76MkikgN05ASMXMgLbjw== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 05/14] arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL OSM-S board Date: Wed, 6 Dec 2023 15:41:08 +0100 Message-ID: <20231206144201.46911-6-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:44:50 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784544117380854917 X-GMAIL-MSGID: 1784544117380854917 From: Frieder Schrempf These signals are actively driven by the SoC or by the onboard transceiver. There's no need to enable the internal pull resistors and due to silicon errata ERR050080 let's disable the internal ones to prevent any unwanted behavior in case they wear out. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-S") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 0730c22e5b6b9..1dd03ef0a7835 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -313,19 +313,19 @@ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 pinctrl_uart1: uart1grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 >; }; From patchwork Wed Dec 6 14:41:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 175871 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp5521820vqy; Fri, 8 Dec 2023 07:15:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IEU5UM/Ji/GEwwCotKkTnTJpzaIuEaczGDHSz50OQKL4dodZ6dyFCZnWB/wm54KE5LHz9tV X-Received: by 2002:a05:6a20:12c7:b0:190:3244:1798 with SMTP id v7-20020a056a2012c700b0019032441798mr145835pzg.71.1702048545695; Fri, 08 Dec 2023 07:15:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702048545; cv=none; d=google.com; s=arc-20160816; b=RyC2Gskl6yRj/yv0s0+PDrf0tJ7WZQ1CkYlOrxrOu2F0OXxbO9G0dxHbO9ImkYG5jG WhNkYyGv68ai5BmfhjcDqPyNss7lRUHQcbjGpjzLqtLa3+dou/mhtHlXfu8rkpAK4HH+ d+jrJmNuoyT8kMFw1WP54kU0/7s2Rd7CuCIXES01DOy46h0idFBgpoJ3n29VikDy9el7 xREtCZgtoWPLgKgdTd720ZjkLY3i7rz01goz6dlIksIJEcglg9aAW8Ysp4uZl7qQTITd +RNPFzyy4FR+vBfXFM5HHasabkcDLHl4FZuj8mpL0AZOCiYniP1n6Hbk9oJbpqjIU+r4 8JbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QLCjnonuAbegej4DQkbKP3MHbkGcNHZPvf2RlTiENxo=; fh=mWDe8CjyAdhhjLFVNrKsiT00acIg4QHc0YGM2tZgom8=; b=ZGhW/hE6J3lM7J2J++/FYP9grS7Z8N2A+QZzqDsUm3caY8gCsv4JPxJCu4dFpABdIv N7iQW+cr+jBZlLFQmdfWu8xitfiygT9IumqMpEZf33ZjEAoRkNRY/YC4J9QU5Mfv3s3z c+7HgNoVJmgMWRtIVh2vqZPRwT6dycQLRNpAfePISY/XJVoTwsWCKEElFhalLVeets3M eaTZW4teAKEun8xsuPm/ltnNoWRJP24nswBwwv7H0Ql4TBXIp+7E6tiZAI1BsFUA+Tjx h7sXdAsuoFhr4aj8fBc8ufMEE4gzgKGU7HS8GqPPjfotxtFbamnbFjlwCFzME07JAEod R9iA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=zX6fAcHq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id z9-20020a656649000000b005b9602a7badsi1654026pgv.688.2023.12.08.07.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 07:15:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=zX6fAcHq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 8AAB68029264; Wed, 6 Dec 2023 06:44:53 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379050AbjLFOok (ORCPT + 99 others); Wed, 6 Dec 2023 09:44:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379057AbjLFOoc (ORCPT ); Wed, 6 Dec 2023 09:44:32 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D329D62; Wed, 6 Dec 2023 06:44:38 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 02823C0191; Wed, 6 Dec 2023 15:44:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873876; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=QLCjnonuAbegej4DQkbKP3MHbkGcNHZPvf2RlTiENxo=; b=zX6fAcHqiFqB0GVbo5b3W1dFBicZS3zkQ/aOxZnb1ZpTMGtjdv36CtG0aVNhQ6Dy3ktN02 AOt+dd/kdhxHnXQtI0a8lmuSyjkmmYYNoFO5ruqXYsmfwo0j8mFLxx7mRPQYXle/sO0AMP 82D4LLWvAkyhzZZ2RU8p97tkCYnX7tY0upljLEQF0+ciRnhpzV2XHRS2sSUN9dR6CQG/Vn BCz2lVjnZ7+th+mNQ2bnG89ElJjNwR4Uk/D2eRga8b5fMxti4fNbUDFDxRsvxh6cViVOlO F7VW0qvcpY/AsdaQIArg1+L/d/YFN1l09fJvZUCl0fdkZF928Girpc7RIdlz6Q== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 06/14] arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL board Date: Wed, 6 Dec 2023 15:41:09 +0100 Message-ID: <20231206144201.46911-7-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_NEUTRAL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:44:53 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784727255513477929 X-GMAIL-MSGID: 1784727255513477929 From: Frieder Schrempf These signals are actively driven by the SoC or by the onboard transceiver. There's no need to enable the internal pull resistors and due to silicon errata ERR050080 let's disable the internal ones to prevent any unwanted behavior in case they wear out. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index 866f35d1633d4..767012661bfca 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -452,19 +452,19 @@ MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19 pinctrl_uart1: uart1grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 >; }; From patchwork Wed Dec 6 14:41:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 175190 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4831968vqy; Thu, 7 Dec 2023 06:50:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IHHLvrdQFPoJzwjwM2c9dFWAtjkFHs1jUpVp1RQj6nNNKVODIzID+dUk9opO4x8c+kIHPaC X-Received: by 2002:a17:903:22cf:b0:1d0:820a:ceec with SMTP id y15-20020a17090322cf00b001d0820aceecmr6222360plg.55.1701960615655; Thu, 07 Dec 2023 06:50:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701960615; cv=none; d=google.com; s=arc-20160816; b=Qj2/ClxbECJf8qgMbEhcOSQYTBQNOT2rElHUZN1xksWyAli8mRLR48woOlZ2yMIix+ OeACmkqNs7ryV5Ex1l8V7w+i+8S/v4xOev71m1Zc1UKnE2tfDeZ52jUoqHOT39q7wKCx NlG3nIjL9541eYxMI9/R1ovEt+i9YwU7eLeaqnh7SqXgYPPqVtaFtn4EVbqPfDehzfA/ mTZe7SdbbOdtgB8buWtLjYeUfcI1ddQGZkocuipPaXXvC0gP3gIu79dkWyq6aKAte18O GNw06wW3/R+typa14h2oa0VR3WHJt1bqQdRSktRxVMRuAoCCAffGaoK/UxSHT4UEPEwA 8C+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tMSX8hysbUP88C2UKn2uKuZ0nkUjhmVSfTTqVo0O4Rk=; fh=5WBVB9KggvEUZrfL2cFjcxt7hrbLV0CECJcyvKKi3zA=; b=XZE8k6vOK2fxNR3oF+R0fpr5s+GFsdUWl2y9UJW8exGuRIydY9eGvoeKVtKaloDvMG IuiVsjOtUdf/BTLSYxUkN+S+Sd5ZrLnplULEri3i9s4JKeIE5mxh9qnwLCEOFZ+Etvsn TiIW819ax2+TBrZ5fwiYrRI2e+2GQtd4uR7/KDVmeeilXC6TOInwQcKga9X+36C+N2N2 MwjkrE3i8LUjUI484PfeyGXej450cIkxdNjexoFcWDww7gWQ+PXBglt8V4eoO9QOSN0/ jm/VcCrNJXUGoAkhHwrKBQWxPj8o8groOkdQxxrl5lWYAQpta6oWqQ+4ok62fIvTIOjp aOqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=UCYx6MrK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from lipwig.vger.email (lipwig.vger.email. [23.128.96.33]) by mx.google.com with ESMTPS id jo3-20020a170903054300b001d1ce4cc5b4si1276761plb.50.2023.12.07.06.50.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 06:50:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=UCYx6MrK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id AE3438029863; Wed, 6 Dec 2023 06:45:01 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379128AbjLFOol (ORCPT + 99 others); Wed, 6 Dec 2023 09:44:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379078AbjLFOoe (ORCPT ); Wed, 6 Dec 2023 09:44:34 -0500 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 690B6D59; Wed, 6 Dec 2023 06:44:39 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7D5BBC0131; Wed, 6 Dec 2023 15:44:37 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873877; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=tMSX8hysbUP88C2UKn2uKuZ0nkUjhmVSfTTqVo0O4Rk=; b=UCYx6MrKF2ksjayBn+9pCB7GcXteUArdpZEbvpemiq9EoFtB6F5KJRTOLoLDrDgHkUaaQ2 a2ZGwYnDTiBDr8feqKWexaJe2ecbJLgR9FP4nyvd7UD3VtXyFCHbqLPYlsQhi5UkffJKhf AXMrdK8+JGZE+0yoLXIEZKTRh7Vc7GXoQIoPJDGQ1+gMuNWnCvRZCa8gKt802Bg0MmquVf Icd+IEfeP/6sXRwds38WlNLlpxqWzSFW3Vz4vKrvyyaWiHfO50ZkwBfGRcek7Iy4LtfGdE 8yy66P5hCkEfJlolNgJoem27FilAp9hrz+Li+K51jgvCfYREqHS4gFqPBUQF3g== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 07/14] arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL OSM-S board Date: Wed, 6 Dec 2023 15:41:10 +0100 Message-ID: <20231206144201.46911-8-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:45:02 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784635054592318078 X-GMAIL-MSGID: 1784635054592318078 From: Frieder Schrempf Some signals have external pullup resistors on the board and don't need the internal ones to be enabled. Due to silicon errata ERR050080 let's disable the internal pull resistors whererever possible and prevent any unwanted behavior in case they wear out. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-S") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 1dd03ef0a7835..d9fa0deea7002 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -337,40 +337,40 @@ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; }; From patchwork Wed Dec 6 14:41:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 175191 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4832263vqy; Thu, 7 Dec 2023 06:50:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IFqY0LwwygEjdHVghVcjDBWnQ3W9ENXtf0X6NO6nO8Rz6JsRA0+g8rEMzahO7xBlYCm1YP1 X-Received: by 2002:a17:90b:3c4c:b0:285:cc9c:75f8 with SMTP id pm12-20020a17090b3c4c00b00285cc9c75f8mr2646558pjb.1.1701960643964; Thu, 07 Dec 2023 06:50:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701960643; cv=none; d=google.com; s=arc-20160816; b=EoaL7iD2X3DH9yhhyzXF/Gpfd1g0XdB08KWOEhyxrd38WI0Mom3Bjtm2xS0GzSrHOk e/xpNceDIBk4hSEUH13eMCr4PYj4YGbvTNvmcWES9A7Mhqq4tjR6IN5LLbh3fJK/mt2V mKmFkjc4djDiehe9F3vI3sd01rC54zd209gA5Osvs4PgmkpmgGvn5x4Spo+23DEd2t+g 60eWSJVuY7H3eZrz6oKLoozwjANJJt7rX5rYjic4QRYTLNrCzc8hygk0iZMgx5ZV0w4L +gzJmvL1CaH+auRlLciVedtN0mJrSKehcQV8tOAb4JWGs2fQPBTrODV3GDR5vmsw58yO kD+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=43HCmKNvhTMgU+tmRX/01rhcuMtpJdHFx7eklJmzHm8=; fh=mWDe8CjyAdhhjLFVNrKsiT00acIg4QHc0YGM2tZgom8=; b=EOIGPRcwwmXvq/VX3JOzANLAPJ/xpG5SiZWxpPpK2XPGKfZRKuX/VI5FQDFqn7EKzN 2n6z+k9aBjcVv5wgFhXLFPXS1m2lfBvksqJ5VNHbjMJ4nhgUVjjRfgEzNdjOmbZaJnxG k2Hn16tDSMfiYcf/1WwkN1OZ9L0FBiWHaqZjUleif4tXH1KB7y3zXAPdw1usfLbfubAp 1Vh8N43VFUZ5YooYSFOUALVUDespKQSeHOre92cweBEaJaojjue5Qxgc5X8/H9Na6Y83 t4mtwjxdHkEXukP3UVE2lp/6U32Uh6XxF4x4s1nWaAJNpO0odhcDWItyi2Vncv32vXc1 /Y8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=RI54nktl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id c24-20020a170902b69800b001cf677b6c20si1222138pls.594.2023.12.07.06.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 06:50:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=RI54nktl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 6CD7D802B163; Wed, 6 Dec 2023 06:44:59 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379004AbjLFOot (ORCPT + 99 others); Wed, 6 Dec 2023 09:44:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379103AbjLFOoj (ORCPT ); Wed, 6 Dec 2023 09:44:39 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD75110C4; Wed, 6 Dec 2023 06:44:40 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D93BBBFD15; Wed, 6 Dec 2023 15:44:38 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873879; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=43HCmKNvhTMgU+tmRX/01rhcuMtpJdHFx7eklJmzHm8=; b=RI54nktluwH01eTYEPAlbBa+uvOJLEBu65gCH8UuXjmE7TbUgqT7ITwyB11tBhfAtzVzLf BaQv4d/oXWau6cTDr1vgn9YzxMFNuBXTn5P9xOQXPtSPowCXrsm2yJdTtpo2WEHvQTyJWt esY5K4JUzityIKFAMJ+Qbmr1eUNG+174urOnAWKHITf8axSRAHvISvLoEmMlbkvfYvpPSC GVK3zdmSO+YOkThh1IWyhuAI1hX0Llbp3OWf9YCleqUJ+yp0oRnNKYac1zcvG04k2zXRV7 BFvSnYHoy7KCkiEJDmwj2x5jg26sib+GCPnLCijIUJ5f2AoLKj34VbenR1brMQ== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 08/14] arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL board Date: Wed, 6 Dec 2023 15:41:11 +0100 Message-ID: <20231206144201.46911-9-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:44:59 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784635084161280226 X-GMAIL-MSGID: 1784635084161280226 From: Frieder Schrempf Some signals have external pullup resistors on the board and don't need the internal ones to be enabled. Due to silicon errata ERR050080 let's disable the internal pull resistors whererever possible and prevent any unwanted behavior in case they wear out. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index 767012661bfca..01722ab25392d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -476,40 +476,40 @@ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; }; From patchwork Wed Dec 6 14:41:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 175878 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp5538044vqy; Fri, 8 Dec 2023 07:42:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IEl+6PUUOSaqt5XngxgYOFy/mj1qOAYexuRqncS3OoUv0SDYG945jAqJHOYGQmqX0pACzWH X-Received: by 2002:a17:90a:df86:b0:28a:464d:5ecb with SMTP id p6-20020a17090adf8600b0028a464d5ecbmr267762pjv.36.1702050144524; Fri, 08 Dec 2023 07:42:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702050144; cv=none; d=google.com; s=arc-20160816; b=rTgcB1zMcJXsmDkA4/09kD3oj+kRLkANjt0jOYFhEKvCF67sjxkefK9szZnxXw0eVl GC6P2QgS4V2q+ShpDMw1bC+TClOFon0y7eO6EUDCYJGpHKjpBwKw1LubuAcMze/iPkA5 SROIBmU3bNi3U+V4UpvrreDunfbEvHg3NcjTA0Mgx2MNhtene3YPSHP9c2Z5cPCTdSj5 N/fQKq9D9tT3Dd895y46or5R7moejwT3l/IYbEBL484Dxmo27k8sbo/9mSsi9MNzr2hc xnXoU8uk7BL8E2mlJoPz7ae35Cg6146JPv3PGAAKBA8rQHJiVpU/rehNKmjtGh+AVR2B b+PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wTGxRgaKGKupnoXw4GHvrCi9OifBL1yEtA/OEf2ONgk=; fh=5WBVB9KggvEUZrfL2cFjcxt7hrbLV0CECJcyvKKi3zA=; b=MiJ4mv4UYlUGjNSWlAWe1NMZv8ZBreyHscS5GTkY85ghhXlTz+BVZJ9Htn0NFDzl2w vSbzItvnIe1dd/nkTXojXly4uSeul4t4mk2zJOofYSUYrjYLBaXbi5Dv5FDKalmDL4sP Jct7Js6uAuS6btQdqoWZjsgDwLfgMUlf9olGuPucPAuD70DWu4iD/7C2Kvhwno26o2iR 0FzvKVWSdAwohtwIxqmR5podkY9sZ6Ui8Z73A3m7ivkN1A++BIXcDtQjwvKYNlVeBZxk YS0v70iqt8nQLqEzMuYdUOITzVpN4k2SI5zNyGOeOtCYrIMfQ7DOGYMZAuOwUNlgnHrN 2fsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=TWBfRiIB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id cp6-20020a17090afb8600b00286adfd9206si2988744pjb.103.2023.12.08.07.42.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 07:42:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=TWBfRiIB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 9ABA880291FF; Wed, 6 Dec 2023 06:45:03 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442111AbjLFOox (ORCPT + 99 others); Wed, 6 Dec 2023 09:44:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442092AbjLFOoq (ORCPT ); Wed, 6 Dec 2023 09:44:46 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE61210EB; Wed, 6 Dec 2023 06:44:42 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 64F7BC00E1; Wed, 6 Dec 2023 15:44:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873880; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=wTGxRgaKGKupnoXw4GHvrCi9OifBL1yEtA/OEf2ONgk=; b=TWBfRiIBUbghnDgwE6d1IzO6XlWafpLVCkuR6KMgN+kNwUHDqJPLimKn8F1FVJnCCoYkN3 W94CGtzWTunAH9KCbNyhHMy0yNv527Xl275PT3Jv6xiHRztSb7jUU/9qqQsdkxbaA2CWC1 O8z89qFUm2lZk6XkgYtq75H5WWbzquHgO9PLnZroDLFqHrJfyfjVTc4oAElz38ln2BboQ7 jEn9HLmND3tCxX6Fh516MO2bXQ8NA8hCAR/qsd9/q2j5aYnLVUVA7ijS9Xb4CbaJjHNsz0 9xv52VscFsHuGqouMDk7hHo5a6PQkqyxazDgzuAgRWLeEC4xUCb3zNnNyMlF/Q== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 09/14] arm64: dts: imx8mm-kontron: Fix interrupt for RTC on OSM-S i.MX8MM module Date: Wed, 6 Dec 2023 15:41:12 +0100 Message-ID: <20231206144201.46911-10-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_NEUTRAL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:45:03 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784728932176490849 X-GMAIL-MSGID: 1784728932176490849 From: Frieder Schrempf The level of the interrupt signal is active low instead. Fix this. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-S") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 3e7db968f7e64..60abcb636cedf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -210,7 +210,7 @@ rv3028: rtc@52 { reg = <0x52>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc>; - interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_LOW>; trickle-diode-disable; }; }; From patchwork Wed Dec 6 14:41:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 175846 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp5513936vqy; Fri, 8 Dec 2023 07:05:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IHUSxAoIw/wk6lZ2aI0iUvRJ2M9M5WLA7VJnSIjOkS6NlqaoZMfnnXX29z4wX3oWtfmZmFj X-Received: by 2002:a05:6a00:1797:b0:6ce:1966:20fa with SMTP id s23-20020a056a00179700b006ce196620famr155182pfg.10.1702047933780; Fri, 08 Dec 2023 07:05:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702047933; cv=none; d=google.com; s=arc-20160816; b=ZYnkbDtHFEMhLsq8E09pNcPNGMIJkLee/WujKzGokMQ234P6VmqtfE63zqT+Ayl6GQ p7MarS5HIT9Vvrt/h6skWFxusIb3ND2NkXlIUMeNrv11YI3A/gyTD24RnLLGiujHA+Nf B2IbdTHeSvq/pUXAp+hqCu0HXTeyszsFSAnkhaIpAjErCul5gH/ANrjc55X0F5SkmHPn Vokpsnmc8nPp4W+X7EMOSVsJjlvK6aRdcO6XmB+F1UnGQd46g9grCq/vmHqvZ4hNsam9 cEfl4W8UYI6E5dIOELaLsPneBwLy8+efWwl3CLHHlxsX0tmI8cbrtsY5Scn4mSNMKavi dD7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3Yd/dhTIQX+6qNHj+D/jIQXXO34y08h1WfgywDqS/fc=; fh=5WBVB9KggvEUZrfL2cFjcxt7hrbLV0CECJcyvKKi3zA=; b=Zz4XxSangXmq5cNB6H6igLVTY/JGfM6WP+bdwjiGdix5yiJhW7b1uHGFtnNAkI3iUM c7aeUU9qPRDhC/8krb1Pi3vCPe0CInf+/ETZUsMNUBLjEGKdIt3zxvcvvKQ5HhzExFru FltU7L3FS78iLWv/+LmOEp0dkeZLJk0vLaUGmONcXTwXWbmIrgu7fJ1bdpcsMhka79yv FDGrrOo5xnqJRMlVNYdZeYOK+ioMfAdySzjlxtE1N36F4gVMXNy5j2fTszPPYXgRucRz H8b/obUFelj7XuhmPg8Fn1bPcjB6VKxQS3CFG8dUmixecGYuPO81qEOSxlDH9SM/5wlp JI+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=wGVrRJRL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id i3-20020a6551c3000000b005c6977f9c0dsi1666855pgq.214.2023.12.08.07.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 07:05:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=wGVrRJRL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id AE48C8072582; Wed, 6 Dec 2023 06:45:20 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442337AbjLFOo4 (ORCPT + 99 others); Wed, 6 Dec 2023 09:44:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442167AbjLFOos (ORCPT ); Wed, 6 Dec 2023 09:44:48 -0500 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3581A10FF; Wed, 6 Dec 2023 06:44:44 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id BEADCC0131; Wed, 6 Dec 2023 15:44:41 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873882; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=3Yd/dhTIQX+6qNHj+D/jIQXXO34y08h1WfgywDqS/fc=; b=wGVrRJRLThsCcqPt0XUEPRc96dXb7M2T6Pjo1t9o1oocl3HtsKs+IWh4nfM/hhltawot3A pEIOxMKokx6A08kTukQD326u2qqyw5P6sVSCr4YO+G4ug9uzGG19VsWe50T7xyUuHtXqZQ WPedxVvMZUlNe+UNTUk3HuRGX4C+WH7U3G/uj3yvx+mM1hhis9pJuFttf1sOUAh/emjc/Q v40fKm5ZZS90ki0ydY8cSpwQtAyPcn4pYyS4At2ZDbWZ3FE8qd6TUuUB7C7iaYFf26DnLq cx/ySjpPSp3G2aJLstLFLhQHO2tTydrhFXWIXZcL3yy2lLTn5w7Azzi6qgDv2Q== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 10/14] arm64: dts: imx8mm-kontron: Fix OSM-S devicetrees to match latest hardware Date: Wed, 6 Dec 2023 15:41:13 +0100 Message-ID: <20231206144201.46911-11-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:45:20 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784726614063052362 X-GMAIL-MSGID: 1784726614063052362 From: Frieder Schrempf The current state of the devicetree for the i.MX8MM OSM-S and the BL baseboard reflects deprecated prototype hardware. Update the board description to match the latest hardware revision. As the old hardware is not available anymore, was only produced in very small quantities and was broken in some ways, we can safely fixup the original devicetree. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM-S") Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 64 ++++++++++++------- 1 file changed, 41 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index d9fa0deea7002..7c5586efccc59 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -30,18 +30,18 @@ leds { led1 { label = "led1"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; led2 { label = "led2"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; }; led3 { label = "led3"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; }; }; @@ -54,7 +54,7 @@ reg_rst_eth2: regulator-rst-eth2 { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb_eth2>; - gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; regulator-name = "rst-usb-eth2"; @@ -91,7 +91,7 @@ can@0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can>; clocks = <&osc_can>; - interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>; /* * Limit the SPI clock to 15 MHz to prevent issues * with corrupted data due to chip errata. @@ -118,7 +118,7 @@ eeram@0 { &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-connection-type = "rgmii-rxid"; + phy-connection-type = "rgmii-id"; phy-handle = <ðphy>; status = "okay"; @@ -127,10 +127,11 @@ mdio { #size-cells = <0>; ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-id4f51.e91b", + "ethernet-phy-ieee802.3-c22"; reg = <0>; - reset-assert-us = <1>; - reset-deassert-us = <15000>; - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; }; }; @@ -153,11 +154,24 @@ &gpio5 { "", "", "", "", "", "", "", ""; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + usb-hub@2c { + compatible = "microchip,usb2514b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_hub>; + reg = <0x2c>; + non-removable-ports = <0>, <3>; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + }; +}; + &i2c4 { - clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; }; &pwm2 { @@ -196,13 +210,13 @@ &usbotg2 { status = "okay"; usb1@1 { - compatible = "usb424,9514"; + compatible = "usb424,2514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; usbnet: ethernet@1 { - compatible = "usb424,ec00"; + compatible = "usbb95,772b"; reg = <1>; local-mac-address = [ 00 00 00 00 00 00 ]; }; @@ -223,7 +237,7 @@ &usdhc2 { &iomuxc { pinctrl_can: cangrp { fsl,pins = < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 >; }; @@ -261,27 +275,24 @@ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */ - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* PHY RST */ >; }; pinctrl_gpio_led: gpioledgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 >; }; pinctrl_gpio1: gpio1grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 >; }; @@ -292,6 +303,13 @@ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 @@ -331,7 +349,7 @@ MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 pinctrl_usb_eth2: usbeth2grp { fsl,pins = < - MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 >; }; From patchwork Wed Dec 6 14:41:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 175838 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp5507066vqy; Fri, 8 Dec 2023 06:56:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IEu75uB6SgckCFLIYD/X6AyBejl62x9OCAqTbVLp3QI5dsclJm6ucrJCbjm1vuBOFFXdIW6 X-Received: by 2002:a17:902:dac4:b0:1d0:6ffe:1e9b with SMTP id q4-20020a170902dac400b001d06ffe1e9bmr137792plx.126.1702047376149; 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[23.128.96.38]) by mx.google.com with ESMTPS id q6-20020a17090311c600b001bdd0d0530dsi1732525plh.129.2023.12.08.06.56.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 06:56:16 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=HP+2WGA2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id DCCF980C3AB3; Wed, 6 Dec 2023 06:52:53 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378966AbjLFOwk (ORCPT + 99 others); Wed, 6 Dec 2023 09:52:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379102AbjLFOos (ORCPT ); Wed, 6 Dec 2023 09:44:48 -0500 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53C2CD44; Wed, 6 Dec 2023 06:44:45 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 77FDEC0191; Wed, 6 Dec 2023 15:44:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873883; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=9tDzhWrZuTaKInW57NumdE7scux5IsL/tfSmFVPexRg=; b=HP+2WGA2lTX9jZ7iMu98kMGZJuLSt65SAea3jw+Y9GRJdLiEi6UwcYJMo8bEyFNtjwjvF0 mJ2fG1aUu2/otSybMa6d1TCki1S1qd9df9PUeO5+sDHKbjB1YHbSJ64ragM0jC7JExkkGM cZKYMQ9L4Y736vH91Onffn3MLduwcjXCSkxjUk3mBJSbLDZ0vc66R7BFQBFdwnELt8zGhj zUIZCRa67B4MoRkDVN3l1KnJ66Ue8keV8JfHwYi/cwGCRte4KPuAvNcw0G4Fj/q6DpMsEP DlS6xtaB1wU0TvTYHJ9WX1AworZDJ/JAROnrnlPslaatNsHnNM89Qc1tp5EKWQ== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 11/14] arm64: dts: imx8mm-kontron: Disable uneffective PUE bit in SDIO IOMUX Date: Wed, 6 Dec 2023 15:41:14 +0100 Message-ID: <20231206144201.46911-12-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:52:54 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784726029258653564 X-GMAIL-MSGID: 1784726029258653564 From: Frieder Schrempf The PUE bit is only effective if the PE bit is also set. To avoid confusion, disable the PUE bit if it is not needed. Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 7c5586efccc59..12f786a72fbd5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -362,7 +362,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 >; }; @@ -375,7 +375,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 >; }; @@ -388,7 +388,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 >; }; }; From patchwork Wed Dec 6 14:41:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 175827 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp5501579vqy; Fri, 8 Dec 2023 06:45:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IHO89YYQhDKRSXKruVrEXmi9Zo+1HmYwxQ3BXImjxcxkZzWr24yawn717zBRIEEv5YP7Ehx X-Received: by 2002:a05:6a20:65b0:b0:18f:97c:928b with SMTP id p48-20020a056a2065b000b0018f097c928bmr81234pzh.112.1702046721951; Fri, 08 Dec 2023 06:45:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702046721; cv=none; d=google.com; s=arc-20160816; b=oiTM5gFtbv9qqHF5UvswqgiYRY2uh9JM/U0Vlbf67nBubS5YGU7JbYLRjf+TJlOjS9 QFD8zY+XlwOFfMNjx+8puMrpq8sT5Yge94STq7tqe5U5CtAlWwL+LJfbt3DHaK66dzye ySVV01Y+OVnOsuSCBNbu5MCmgzhcwnlw31cQhkw8+jbcJ7Q5aGvCnAeWp1XZDrXQ7TlV fD7SbjJwmz/KgUVl5Ql44ziWJYDlKakDRA3tjhqN84Ggg59OmfvNWLs2fuZDCT4s9y3f b9pu9l7Kif1JHknTlUPFFDbaYOXa2lLrxRrkwao8OFs6x8OOUWgW967l6RLywYZmYmfl o/qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IKeKgwpFsNj9YrDVbsZmnB9SqQh3ugfmHYM2RQIQqoo=; fh=ltYwvILgD5pj0Rly1blr/5KGxhpSp2Y+0x4fOITKRXI=; b=SV1L6M9T36+mhrH3Aea4AL530RSU2/uNatPf3E3X6rB40Ss6f1rCH61PDLQMmlOfgm nfkRa8nZ+uWl9/w1Wg4iCbEInxUVHD4/OWQXsPCnaE15DeYAfvD3pKPMA7q0VuczGonZ ihDnTHyt4v2RPWunnD9ewIEgzOwzFLxf4cnSADnpb06nbkcNFFlYNL6jf9kavCzzfZ5W 4XeLYQ9gdQJ2H+qYTmgd7BIFx/x2FfXyDfOKHrW1eGmVlbnZ303o3mPrdNw1D9NObi6+ hK5sLyup2IwMOMI+eXJppbJWZ5VvmCR1qlNMtJeW/c1IpTJRbJIPnNqpCIKJHfzggY/t +QeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=DUQik+0w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id l5-20020a656805000000b005c66072691asi1614217pgt.551.2023.12.08.06.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 06:45:21 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=DUQik+0w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 25A1A826E3B6; Wed, 6 Dec 2023 06:52:59 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378989AbjLFOwo (ORCPT + 99 others); Wed, 6 Dec 2023 09:52:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379120AbjLFOot (ORCPT ); Wed, 6 Dec 2023 09:44:49 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40C45D59; Wed, 6 Dec 2023 06:44:46 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DB699C0190; Wed, 6 Dec 2023 15:44:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873885; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=IKeKgwpFsNj9YrDVbsZmnB9SqQh3ugfmHYM2RQIQqoo=; b=DUQik+0wkRvmJAHx/RNOxS6DwLKwXsI2bs3Za+zyQz4Ep6gYREaLLpuU9xmVVdhfK4gYkd 1+CSK1660MIbrOoCl68VX4htwC/zj8RNwn0IiokbS06mMpjgzzTM3lr+wIxMCyFbuR/Glk V8hZq4YA7wUFBkiATYnv93/nmLsOWOP9/crBJTtQYC2wapV/tM/6PHtEMr7r5dx7i/qjaF bxnjly63f+Ag0HDuKUNImdJC/Eeu5sqIBxxMOREBI9Jctmk9Rim+dz0Wnre6kQ7FFz32Ls YlRhM1nkoIALE8G8tGi1GxbgmfL6cF1ZVE1SNIDdvB8zsViFpvDiraMRpmO2vA== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 12/14] arm64: dts: imx8mm-kontron: Remove useless trickle-diode-disable from RTC node Date: Wed, 6 Dec 2023 15:41:15 +0100 Message-ID: <20231206144201.46911-13-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:52:59 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784725343347820755 X-GMAIL-MSGID: 1784725343347820755 From: Frieder Schrempf The RV3028 driver doesn't use this property. Remove it. Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 60abcb636cedf..b161b0c85d61e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -211,7 +211,6 @@ rv3028: rtc@52 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc>; interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_LOW>; - trickle-diode-disable; }; }; From patchwork Wed Dec 6 14:41:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 175866 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp5518399vqy; Fri, 8 Dec 2023 07:11:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IHCNWveMnCIgAj3bdHQz7s5u06mYMhvjqWKeSwOAybDD5/ZzlspujCsyZ566WGrD7Q4onQO X-Received: by 2002:a17:902:ec87:b0:1d0:6ffd:ae17 with SMTP id x7-20020a170902ec8700b001d06ffdae17mr140402plg.126.1702048267836; Fri, 08 Dec 2023 07:11:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702048267; cv=none; d=google.com; s=arc-20160816; b=imzlX9qTw2OEBdlNKk6fpxquQafZ+22FAykXzZ91Y7E0QHuM1ALJNinVHM4+ZzpeoC lNwpdjH+cD52f33AN9QQhvKEsDKxo6ogXLEYgl+qPzwj5ZbWODHzat6uSI/e2dVZR8qr IcClCpFus4A7Os48VheS09OPbsnZHQciza2YhJyD0NFRvsTnTehSNZEiOP4ZtiIc3GCO Hjf2bFDqxRUhNkCV79ckCSXd15KoWnUv9uhHDG/M5qdk4pcIY/U4daIpz6WiK0A7Xmh2 RNL+MNGD55nWHFdZ94xnbrwACANCOSwAQ2A9I3tpywh2LS2v2AUBiSww+5l7lUWyvDgT UbkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kx4/WNwSRtSkIKBw7sjNm52ZpZ7M2ZKDAMkBQh2uf30=; fh=ltYwvILgD5pj0Rly1blr/5KGxhpSp2Y+0x4fOITKRXI=; b=iYB0+TwkSeEsks5hOw4FBCdbJMhSzs+8d7LaT3jsKoUmuu54kTtB5Mv3eCcVS2qVTL 5cMhRxhMHETGdvEucSZZk50eR2zi/uLUCxyDNouGLFKhxp0nX7+jvJuPMVfjJjZmCf1u TZRHKvWQ1sJ6gz9yhOM2tlzDswiEMcbQdHzv+nr+c+eU0Ho4r5a0jtPQHvnOvq8t1R03 BiGc88anAqU8gjMOaCFPNsLVys+M9cnHumxv8BZLYTbFDH8yY6H2ZwfZQ5RrgTeR8hPR h+b1EK3ZCWuuRsmo9HDSwGN4+FALAMC8MfYWvSQJDqgfQ9VUttL7+iYe2cg3h/iWacJO JHRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b="Qei/bilb"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id j9-20020a17090276c900b001d06d5f9533si1713296plt.619.2023.12.08.07.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 07:11:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b="Qei/bilb"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 9D15C80886B9; Wed, 6 Dec 2023 06:45:34 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379149AbjLFOpI (ORCPT + 99 others); Wed, 6 Dec 2023 09:45:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442276AbjLFOov (ORCPT ); Wed, 6 Dec 2023 09:44:51 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9E901725; Wed, 6 Dec 2023 06:44:48 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 56B03C0128; Wed, 6 Dec 2023 15:44:46 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873886; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=kx4/WNwSRtSkIKBw7sjNm52ZpZ7M2ZKDAMkBQh2uf30=; b=Qei/bilbQZvonf/vDhu6vrfBzQHNyoukyPFVD7Vi/C1ZxfOJFMZRwQQOWHN+nzz51iSXnZ rU65UBsTvs2JwfTVukbGLFhuH4iYsdKia/PL+L4hl1t9IF7KKZWV4mwPgaZH7WmUKwaQjI OSkKUY1IWRv3yXzqj7HvgdzTomrZnWYRUfrpvdNFJS45cqrLqwxU7bF+oCyolfe5dBJc92 AgcwvaB3e7FSQtLruxveBQS5lDCFT3BHuWRjj072vI7Y+EG95LZyT845On2I65nAPV40+X gE145IroEnL0pmt3l9bdyilJ0/Z7fOymjOsK/OPs6BjjStlColR7q6Wx75JqZA== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 13/14] arm64: dts: imx8mm-kontron: Add I2C EEPROM on OSM-S Kontron i.MX8MM Date: Wed, 6 Dec 2023 15:41:16 +0100 Message-ID: <20231206144201.46911-14-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_NEUTRAL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:45:34 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784726964472402927 X-GMAIL-MSGID: 1784726964472402927 From: Frieder Schrempf There is an EEPROM on the SoM module. Add it to the description. Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index b161b0c85d61e..6b9058fc53332 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -205,6 +205,14 @@ reg_nvcc_sd: LDO5 { }; }; + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + address-width = <16>; + pagesize = <32>; + size = <8192>; + }; + rv3028: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; From patchwork Wed Dec 6 14:41:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frieder Schrempf X-Patchwork-Id: 175200 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4844810vqy; Thu, 7 Dec 2023 07:07:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IHYR5xpdN1zJFebewWR0Tk+shrunNmQ9DJB9Mm+dmFDurn/Mlg87d1kT2F70AnSqlQT7rI8 X-Received: by 2002:a17:90b:3812:b0:27c:f309:f381 with SMTP id mq18-20020a17090b381200b0027cf309f381mr2775138pjb.6.1701961659126; Thu, 07 Dec 2023 07:07:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701961659; cv=none; d=google.com; s=arc-20160816; b=iPlhPK3qvQkAbMwEpyF81zxP804Ow+lnczgWeglq4X0YigiFdeEJTluJN8qX8fOAAT JlnSQHqmNkDeX1lAKMJPTL8X93SVTWTd47QMnGzdbSxBVN8ZoQBmZJ0XWYOMCsy0raUD 64/QOizob/knsQo29mYSLjDVAR5kbUkJrhkX51iuaGllt2iV7Byt8rluxK1A1WwGN9fY yh1CkrjoRRRfk8QEA2g7+QXzxF6fo6DXB0EGclSN69K6nkWuiVrXfEyi+hqzezrg9BC7 rRAh8ahocI5CzLIMLP8J+eeFeVlJI/xFNSmJF4VxocnAcV4R0vrlpI/EK3cyU2wMSgrA hL2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LzCepDPihJFEKeRie8QIRkXeAXlAu8NPaswOAfzNp8c=; fh=ltYwvILgD5pj0Rly1blr/5KGxhpSp2Y+0x4fOITKRXI=; b=KJ5Z8TKBcRdsePOyO7YlugoG7kRFi6BdDPVfDWdqzESViEkPtNP/aHVoD+cbS3sSq1 k9+lZQlS0tuMCdk8/ZSQQXfuRAp/M65vwZlknzdYZyub1aRbGVo5AIEcRk/aheirrqGW yeauGKTEtzH7CU6/qtJ1dUSYElhfAFam6x+sB2Vfrozj9SmKvKiNTC19YAxi475ay61H SnsumJI/orqOjaiMHHS6S5krCbeSv5LjypnwVBO2LBu67MPfBSOFJRgB11NokrgKTyZh SlmqH+2tpaeoLsJnf+e/u0WziSlg1eRCn/C7b+72INBmIUGQuCqZuSKXytKapxxXjrHT u4IQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=oiq+3yC8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id g8-20020a17090a708800b002839be230b2si1229090pjk.44.2023.12.07.07.07.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 07:07:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@fris.de header.s=dkim header.b=oiq+3yC8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=fris.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 816F480756C1; Wed, 6 Dec 2023 06:45:29 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1442156AbjLFOpT (ORCPT + 99 others); Wed, 6 Dec 2023 09:45:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1442111AbjLFOpI (ORCPT ); Wed, 6 Dec 2023 09:45:08 -0500 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B715198B; Wed, 6 Dec 2023 06:44:51 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id ADF9FBFD15; Wed, 6 Dec 2023 15:44:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701873889; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=LzCepDPihJFEKeRie8QIRkXeAXlAu8NPaswOAfzNp8c=; b=oiq+3yC8b1H9TqXnTWRzOw3pndvyxQRJUN07OMNivKWAAXfy1FZIhfu/b6O2kuP9eUpVBK LGMpVf1KFNwHXvKV6ir6bmVREEsNmvm2Y53N0BkQEDLR//uRZm5DCKz3AebN4wEYYa5wlM YCPu40uYPXbrURSx25Jc9LRduDrBsmcAro+bm2mcrhX58cxhzqRdBKCYOHSBpXAeOjbFGK 9WMIIweEHlNOWmzw1v7Ti/kTA9jcgGtotyA6d3o1nVXmSItrxrSrrwqJR21ifCw/VOzV0m H7SSaWPyTQ1ZE7hvlg324VioelStMk8981f5vIwxFE/aGX9XmvfguZnNwBxavg== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v3 14/14] arm64: dts: imx8mm-kontron: Refactor devicetree for OSM-S module and board Date: Wed, 6 Dec 2023 15:41:17 +0100 Message-ID: <20231206144201.46911-15-frieder@fris.de> In-Reply-To: <20231206144201.46911-1-frieder@fris.de> References: <20231206144201.46911-1-frieder@fris.de> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:45:30 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784636148793355264 X-GMAIL-MSGID: 1784636148793355264 From: Frieder Schrempf The OSM spec defines dedicated functions for all pads of the SoM. Therefore we can assume that carrier board designs stick to these definitions and extend the SoM devicetree include with matching default nodes and pinmux settings. This way we can reduce the overhead and redundancy in the carrier board devicetrees while still sticking to the policy of separating board and module description. Even if the carrier board design deviates slightly from the spec it can define its own pinmux definitions and use them as necessary or even disable unused nodes from the SoM devicetree. Signed-off-by: Frieder Schrempf --- Changes for v3: * Address Shawn's review comments (thanks!) Changes for v2: * none --- .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 269 +++------ .../dts/freescale/imx8mm-kontron-osm-s.dtsi | 552 +++++++++++++++++- 2 files changed, 616 insertions(+), 205 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 12f786a72fbd5..efadfdff00af1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -25,8 +25,6 @@ osc_can: clock-osc-can { leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; led1 { label = "led1"; @@ -52,24 +50,12 @@ pwm-beeper { reg_rst_eth2: regulator-rst-eth2 { compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_eth2>; gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; regulator-name = "rst-usb-eth2"; }; - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_vbus>; - gpio = <&gpio3 25 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "usb1-vbus"; - }; - reg_vdd_5v: regulator-5v { compatible = "regulator-fixed"; regulator-always-on; @@ -80,9 +66,6 @@ reg_vdd_5v: regulator-5v { }; &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; status = "okay"; can@0 { @@ -103,9 +86,6 @@ can@0 { }; &ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; status = "okay"; eeram@0 { @@ -117,7 +97,7 @@ eeram@0 { &fec1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; + pinctrl-0 = <&pinctrl_enet_rgmii>; phy-connection-type = "rgmii-id"; phy-handle = <ðphy>; status = "okay"; @@ -136,27 +116,59 @@ ethphy: ethernet-phy@0 { }; }; +/* + * Rename SoM signals according to board usage: + * GPIO_B_0 -> DIO1_OUT + * GPIO_B_1 -> DIO2_OUT + */ &gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>; - gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out", - "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; + gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1", + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", + "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "DIO1_OUT", + "DIO2_OUT", "USB_A_OC#", "CAM_MCK", "USB_B_OC#", + "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3", + "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1", + "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)", + "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)", + "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0", + "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2", + "ETH_A_(R)(G)MII_RXD3"; }; -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio5>; - gpio-line-names = "", "", "dio4-in", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; +/* + * Rename SoM signals according to board usage: + * GPIO_B_2 -> DIO3_OUT + * GPIO_B_3 -> DIO4_OUT + */ +&gpio3 { + gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5", + "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1", + "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4", + "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "DIO3_OUT", + "USB_B_EN", "DIO4_OUT", "PCIe_CLKREQ#", "PCIe_A_PERST#", + "PCIe_WAKE#", "USB_A_EN"; +}; + +/* + * Rename SoM signals according to board usage: + * GPIO_B_4 -> DIO1_IN + * GPIO_B_5 -> DIO2_IN + * GPIO_B_6 -> DIO3_IN + * GPIO_B_7 -> DIO4_IN + */ +&gpio4 { + gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN", + "DIO1_IN", "BOOT_SEL0#", "BOOT_SEL1#", "", + "", "", "I2S_LRCLK", "I2S_BITCLK", + "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "DIO2_IN", "DIO3_IN", + "DIO4_IN", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6", + "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS", + "UART_A_RTS", "", "", "", + "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX"; }; &i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; usb-hub@2c { @@ -169,27 +181,28 @@ usb-hub@2c { }; }; -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; -}; - &pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; }; +®_usb2_vbus { + status = "disabled"; +}; + +®_usdhc2_vcc { + status = "disabled"; +}; + +®_usdhc3_vcc { + status = "disabled"; +}; + &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; uart-has-rtscts; status = "okay"; }; &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; linux,rs485-enabled-at-boot-time; uart-has-rtscts; status = "okay"; @@ -197,8 +210,6 @@ &uart2 { &usbotg1 { dr_mode = "otg"; - disable-over-current; - vbus-supply = <®_usb1_vbus>; status = "okay"; }; @@ -209,6 +220,9 @@ &usbotg2 { #size-cells = <0>; status = "okay"; + /* VBUS is controlled by the hub */ + /delete-property/ vbus-supply; + usb1@1 { compatible = "usb424,2514"; reg = <1>; @@ -224,171 +238,20 @@ usbnet: ethernet@1 { }; &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; vmmc-supply = <®_vdd_3v3>; - vqmmc-supply = <®_nvcc_sd>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; status = "okay"; }; &iomuxc { pinctrl_can: cangrp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* PHY RST */ - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 - >; - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 - >; - }; - - pinctrl_gpio5: gpio5grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 - >; - }; - - pinctrl_reg_usb1_vbus: regusb1vbusgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 - >; - }; - - pinctrl_usb_eth2: usbeth2grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */ >; }; - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + pinctrl_usb_hub: usbhubgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */ >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 6b9058fc53332..663ae52b48526 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2022 Kontron Electronics GmbH */ +#include #include #include "imx8mm.dtsi" @@ -28,6 +29,73 @@ memory@40000000 { chosen { stdout-path = &uart3; }; + + reg_vdd_carrier: regulator-vdd-carrier { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vdd_carrier>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "VDD_CARRIER"; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_vbus>; + enable-active-high; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VBUS_USB1"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_vbus>; + enable-active-high; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VBUS_USB2"; + }; + + reg_usdhc2_vcc: regulator-usdhc2-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>; + enable-active-high; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SDIO_A"; + }; + + reg_usdhc3_vcc: regulator-usdhc3-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>; + enable-active-high; + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SDIO_B"; + }; }; &A53_0 { @@ -96,6 +164,79 @@ partition@1f0000 { }; }; +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_ecspi2_gpio>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1", + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", + "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "GPIO_B_0", + "GPIO_B_1", "USB_A_OC#", "CAM_MCK", "USB_B_OC#", + "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3", + "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1", + "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)", + "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)", + "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0", + "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2", + "ETH_A_(R)(G)MII_RXD3"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "SDIO_A_CD#", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0", + "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN", + "SDIO_A_WP"; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>; + gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5", + "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1", + "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4", + "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_2", + "USB_B_EN", "GPIO_B_3", "PCIe_CLKREQ#", "PCIe_A_PERST#", + "PCIe_WAKE#", "USB_A_EN"; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN", + "GPIO_B_4", "BOOT_SEL0#", "BOOT_SEL1#", "", + "", "", "I2S_LRCLK", "I2S_BITCLK", + "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "GPIO_B_5", "GPIO_B_6", + "GPIO_B_7", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6", + "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS", + "UART_A_RTS", "", "", "", + "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX"; +}; + +&gpio5 { + gpio-line-names = "UART_B_TX", "SDIO_B_PWR_EN", "SDIO_B_WP", "PWM_2", + "PWM_1", "PWM_0", "", "", + "", "", "SPI_A_SCK", "SPI_A_SDO_(IO1)", + "SPI_A_SCK", "SPI_A_CS0#", "", "", + "I2C_A_SCL", "I2C_A_SDA", "I2C_B_SCL", "I2C_B_SDA", + "PCIe_SMCLK", "PCIe_SMDAT", "SPI_B_SCK", "SPI_B_SDO", + "SPI_B_SDI", "SPI_B_CS0#", "UART_CON_RX", "UART_CON_TX", + "UART_C_RX", "UART_C_TX"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -222,12 +363,69 @@ rv3028: rtc@52 { }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + &uart3 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + vbus-supply = <®_usb1_vbus>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + vbus-supply = <®_usb2_vbus>; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -240,6 +438,26 @@ &usdhc1 { status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vcc>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + vmmc-supply = <®_usdhc3_vcc>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -248,6 +466,12 @@ &wdog1 { }; &iomuxc { + pinctrl_csi_mck: csimckgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 /* CAM_MCK */ + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 @@ -257,6 +481,106 @@ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 >; }; + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 /* SPI_A_SDI_(IO0) */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 /* SPI_A_SDO_(IO1) */ + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 /* SPI_A_SCK */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* SPI_A_CS0# */ + >; + }; + + pinctrl_ecspi2_gpio: ecspi2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* SPI_A_/WP_(IO2) */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* SPI_A_/HOLD_(IO3) */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 /* SPI_B_SDI */ + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 /* SPI_B_SDO */ + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 /* SPI_B_SCK */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* SPI_B_CS0# */ + >; + }; + + pinctrl_enet_rgmii: enetrgmiigrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */ + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */ + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */ + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */ + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */ + >; + }; + + pinctrl_enet_rmii: enetrmiigrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f /* ETH_A_(S)(R)(G)MII_TXD2 */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 /* ETH_A_(S)(R)(G)MII_TXD1 */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 /* ETH_A_(S)(R)(G)MII_TXD0 */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 /* ETH_A_(S)(R)(G)MII_RXD1 */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 /* ETH_A_(S)(R)(G)MII_RXD0 */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 /* ETH_A_(R)(G)MII_TX_EN(_ER) */ + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* GPIO_A_0 */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* GPIO_A_1 */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* GPIO_A_2 */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* GPIO_A_3 */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* GPIO_A_4 */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 /* GPIO_A_5 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* GPIO_A_6 */ + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* GPIO_A_7 */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* GPIO_B_0 */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* GPIO_B_1 */ + >; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* GPIO_C_5 */ + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* GPIO_C_4 */ + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* GPIO_C_0 */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* GPIO_C_1 */ + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* GPIO_C_2 */ + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* GPIO_C_3 */ + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* GPIO_B_2 */ + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* GPIO_B_3 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* GPIO_C_7 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* GPIO_B_4 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* BOOT_SEL0# */ + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* BOOT_SEL1# */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* GPIO_B_5 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* GPIO_B_6 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* GPIO_B_7 */ + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* GPIO_C_6 */ + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 @@ -264,22 +588,149 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083 >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */ + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 /* I2C_B_SCL */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 /* I2C_B_SDA */ + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 /* PCIe_SMCLK and I2C_CAM_SCL/CSI_TX_P */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 /* PCIe_SMDAT and I2C_CAM_SDA/CSI_TX_N */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* PCIe_CLKREQ# */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* PCIe_A_PERST# */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* PCIe_WAKE# */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* PCIe_SM_ALERT */ + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19 /* PWM_0 */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 /* PWM_1 */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x19 /* PWM_2 */ + >; + }; + + pinctrl_reg_usb1_vbus: regusb1vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* USB_A_EN */ + >; + }; + + pinctrl_reg_usb2_vbus: regusb2vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* USB_B_EN */ + >; + }; + + pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */ + >; + }; + + pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */ + >; + }; + + pinctrl_reg_vdd_carrier: regvddcarriergrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* CARRIER_PWR_EN */ + >; + }; + pinctrl_rtc: rtcgrp { fsl,pins = < MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 /* I2S_A_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 /* I2S_A_DATA_OUT */ + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 /* I2S_B_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 /* I2S_B_DATA_OUT */ + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 /* I2S_MCLK */ + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 /* I2S_LRCLK */ + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 /* I2S_BITCLK */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 /* UART_A_RX */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 /* UART_A_TX */ + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 /* UART_A_CTS */ + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 /* UART_A_RTS */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 /* UART_B_RX */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 /* UART_B_TX */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 /* UART_B_CTS */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 /* UART_B_RTS */ + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 /* UART_CON_RX */ + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 /* UART_CON_TX */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x0 /* UART_C_RX */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0 /* UART_C_TX */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 /* USB_A_OC# */ + >; + }; + + pinctrl_usb2: usb2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x19 /* USB_B_OC# */ >; }; @@ -334,6 +785,103 @@ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 >; }; + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 /* SDIO_A_CD# */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x90 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x90 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x90 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x90 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x90 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x90 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x90 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x90 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x90 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x90 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x94 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x94 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x94 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x94 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x94 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x94 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x94 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x94 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x94 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x94 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x96 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x96 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x96 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x96 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x96 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x96 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x96 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x96 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x96 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x96 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_gpio: usdhc3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* SDIO_B_CD# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */ + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6