From patchwork Wed Dec 6 10:58:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174499 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4024974vqy; Wed, 6 Dec 2023 03:01:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IGhzC4lZ0/pqWP+ALS3yrhEt8f5dUNJodDqM658SVW14+8J6Ur2NUnTWRSzmRUiE0blKC3w X-Received: by 2002:a05:6358:8a3:b0:16d:bec8:654f with SMTP id m35-20020a05635808a300b0016dbec8654fmr1077053rwj.1.1701860484125; Wed, 06 Dec 2023 03:01:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860484; cv=none; d=google.com; s=arc-20160816; b=ovcieLNr4nm+XeaXSx5GADpUvCUskHuRBpG3OQiyi0zbTNxjd48A0euvBOJ/ms2BBk SksHrQ8ggmoVWDDcSWDAHfR34/0qNPj9KXpmGY9vIft/1Z4KXwAMF8pdI0ldh9eoxzkH 1Uvv9KuaYmmM6u5TARpUX19OL9LELp3TnlW2Tm7SE9AbwqHeYJka6xRoS766wKAkgwL5 uOisF0bEKXiHMfOl/5Gge1LSQIOtkA5LJhrUxgGwCVZOqhh8AFqe3Yl4kiX1dxHKonJu gZs4rwRq5o8njqh31zJH1oAbhyJPiUpsqgnMm10JhKYrt6JICdt6bKgcHHYw/L1ky28d NBnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=K7UZdmdyYz24tezUgGACcYCmJKOSO6Q04qEPwmoKWvY=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=OOKYf6SUXTe7HKTpkT0SsUE/dLYAZFFcM+i0/VlIevc+g8DwOiWrVherhgMInTIE0p pbX5RiE2aYvMMS1G/upnGEMfMmeck5E0Gr4kQPKWAhbeqgYLXMRcQfYZFjHb2PKYIvg5 b5nLgZSTfCzADteJnDijdg3QnOex/Wx2U7k4xuNEM+BoEpc2UK0v8y3Bqu/YccyBL1OV Pqlkj3k3Vut6s8SoiIkM3MouBvEcmqhuRz60HqMMxJF6R6fzqqpgwmbHiPvBMxD6XCq8 EpaTQJ++35XfSuoDI1rwkS9FSOOf6hGj5779sNr+7S7GfcwV290ynTUmVeAbPPT0865+ +uvg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id bg2-20020a056a02010200b005c6259da621si11497355pgb.555.2023.12.06.03.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:01:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 636A08075952; Wed, 6 Dec 2023 03:00:20 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378022AbjLFK7e (ORCPT + 99 others); Wed, 6 Dec 2023 05:59:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377929AbjLFK7G (ORCPT ); Wed, 6 Dec 2023 05:59:06 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A4E1D42; Wed, 6 Dec 2023 02:58:57 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id A79637FFE; Wed, 6 Dec 2023 18:58:43 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:43 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:41 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 01/21] dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties Date: Wed, 6 Dec 2023 18:58:19 +0800 Message-ID: <20231206105839.25805-2-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:00:20 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530058622950008 X-GMAIL-MSGID: 1784530058622950008 Add PLDA XpressRICH PCIe host common properties dt-binding doc. PolarFire PCIe host using PLDA IP. Move common properties from Microchip PolarFire PCIe host to PLDA files. Signed-off-by: Minda Chen Reviewed-by: Hal Feng Reviewed-by: Conor Dooley Reviewed-by: Rob Herring Tested-by: John Clark --- .../bindings/pci/microchip,pcie-host.yaml | 55 +------------- .../pci/plda,xpressrich3-axi-common.yaml | 75 +++++++++++++++++++ 2 files changed, 76 insertions(+), 54 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index f7a3c2636355..7c2d51221f65 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -10,21 +10,13 @@ maintainers: - Daire McNamara allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: plda,xpressrich3-axi-common.yaml# - $ref: /schemas/interrupt-controller/msi-controller.yaml# properties: compatible: const: microchip,pcie-host-1.0 # PolarFire - reg: - maxItems: 2 - - reg-names: - items: - - const: cfg - - const: apb - clocks: description: Fabric Interface Controllers, FICs, are the interface between the FPGA @@ -52,18 +44,6 @@ properties: items: pattern: '^fic[0-3]$' - interrupts: - minItems: 1 - items: - - description: PCIe host controller - - description: builtin MSI controller - - interrupt-names: - minItems: 1 - items: - - const: pcie - - const: msi - ranges: maxItems: 1 @@ -71,39 +51,6 @@ properties: minItems: 1 maxItems: 6 - msi-controller: - description: Identifies the node as an MSI controller. - - msi-parent: - description: MSI controller the device is capable of using. - - interrupt-controller: - type: object - properties: - '#address-cells': - const: 0 - - '#interrupt-cells': - const: 1 - - interrupt-controller: true - - required: - - '#address-cells' - - '#interrupt-cells' - - interrupt-controller - - additionalProperties: false - -required: - - reg - - reg-names - - "#interrupt-cells" - - interrupts - - interrupt-map-mask - - interrupt-map - - msi-controller - unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml new file mode 100644 index 000000000000..31bb17b11e58 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/plda,xpressrich3-axi-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PLDA XpressRICH PCIe host common properties + +maintainers: + - Daire McNamara + - Kevin Xie + +description: + Generic PLDA XpressRICH PCIe host common properties. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + reg: + maxItems: 2 + + reg-names: + items: + - const: cfg + - const: apb + + interrupts: + minItems: 1 + items: + - description: PCIe host controller + - description: builtin MSI controller + + interrupt-names: + minItems: 1 + items: + - const: pcie + - const: msi + + msi-controller: + description: Identifies the node as an MSI controller. + + msi-parent: + description: MSI controller the device is capable of using. + + interrupt-controller: + type: object + properties: + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - reg + - reg-names + - interrupts + - msi-controller + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +additionalProperties: true + +... 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[23.128.96.32]) by mx.google.com with ESMTPS id t15-20020a056a0021cf00b006cdfa76e7e8si9890739pfj.299.2023.12.06.02.59.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 02:59:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 4187180321ED; Wed, 6 Dec 2023 02:59:22 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377935AbjLFK7I (ORCPT + 99 others); Wed, 6 Dec 2023 05:59:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377836AbjLFK7B (ORCPT ); Wed, 6 Dec 2023 05:59:01 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C73B110FD; Wed, 6 Dec 2023 02:58:51 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 8182224E2B5; Wed, 6 Dec 2023 18:58:44 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:44 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:43 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 02/21] PCI: microchip: Move pcie-microchip-host.c to plda directory Date: Wed, 6 Dec 2023 18:58:20 +0800 Message-ID: <20231206105839.25805-3-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 06 Dec 2023 02:59:22 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784529934618080235 X-GMAIL-MSGID: 1784529934618080235 For Microchip Polarfire PCIe host is PLDA XpressRich IP, move to plda directory. Prepare for refactoring the codes. Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- MAINTAINERS | 4 ++-- drivers/pci/controller/Kconfig | 9 +-------- drivers/pci/controller/Makefile | 2 +- drivers/pci/controller/plda/Kconfig | 14 ++++++++++++++ drivers/pci/controller/plda/Makefile | 2 ++ .../controller/{ => plda}/pcie-microchip-host.c | 2 +- 6 files changed, 21 insertions(+), 12 deletions(-) create mode 100644 drivers/pci/controller/plda/Kconfig create mode 100644 drivers/pci/controller/plda/Makefile rename drivers/pci/controller/{ => plda}/pcie-microchip-host.c (99%) diff --git a/MAINTAINERS b/MAINTAINERS index 788be9ab5b73..46728cc258ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16842,7 +16842,7 @@ M: Daire McNamara L: linux-pci@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/pci/microchip* -F: drivers/pci/controller/*microchip* +F: drivers/pci/controller/plda/*microchip* PCIE DRIVER FOR QUALCOMM MSM M: Manivannan Sadhasivam @@ -18643,7 +18643,7 @@ F: drivers/char/hw_random/mpfs-rng.c F: drivers/clk/microchip/clk-mpfs*.c F: drivers/i2c/busses/i2c-microchip-corei2c.c F: drivers/mailbox/mailbox-mpfs.c -F: drivers/pci/controller/pcie-microchip-host.c +F: drivers/pci/controller/plda/pcie-microchip-host.c F: drivers/pwm/pwm-microchip-core.c F: drivers/reset/reset-mpfs.c F: drivers/rtc/rtc-mpfs.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index e534c02ee34f..4d2c188f5835 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -215,14 +215,6 @@ config PCIE_MT7621 help This selects a driver for the MediaTek MT7621 PCIe Controller. -config PCIE_MICROCHIP_HOST - tristate "Microchip AXI PCIe controller" - depends on PCI_MSI && OF - select PCI_HOST_COMMON - help - Say Y here if you want kernel to support the Microchip AXI PCIe - Host Bridge driver. - config PCI_HYPERV_INTERFACE tristate "Microsoft Hyper-V PCI Interface" depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI @@ -356,4 +348,5 @@ config PCIE_XILINX_CPM source "drivers/pci/controller/cadence/Kconfig" source "drivers/pci/controller/dwc/Kconfig" source "drivers/pci/controller/mobiveil/Kconfig" +source "drivers/pci/controller/plda/Kconfig" endmenu diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index f2b19e6174af..038ccbd9e3ba 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o -obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o obj-$(CONFIG_VMD) += vmd.o obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o @@ -44,6 +43,7 @@ obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ obj-y += mobiveil/ +obj-y += plda/ # The following drivers are for devices that use the generic ACPI diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig new file mode 100644 index 000000000000..5cb3be4fc98c --- /dev/null +++ b/drivers/pci/controller/plda/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0 + +menu "PLDA-based PCIe controllers" + depends on PCI + +config PCIE_MICROCHIP_HOST + tristate "Microchip AXI PCIe controller" + depends on PCI_MSI && OF + select PCI_HOST_COMMON + help + Say Y here if you want kernel to support the Microchip AXI PCIe + Host Bridge driver. + +endmenu diff --git a/drivers/pci/controller/plda/Makefile b/drivers/pci/controller/plda/Makefile new file mode 100644 index 000000000000..e1a265cbf91c --- /dev/null +++ b/drivers/pci/controller/plda/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c similarity index 99% rename from drivers/pci/controller/pcie-microchip-host.c rename to drivers/pci/controller/plda/pcie-microchip-host.c index 137fb8570ba2..cb09a8137e25 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -18,7 +18,7 @@ #include #include -#include "../pci.h" +#include "../../pci.h" /* Number of MSI IRQs */ #define MC_MAX_NUM_MSI_IRQS 32 From patchwork Wed Dec 6 10:58:21 2023 Content-Type: text/plain; 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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id m1-20020a632601000000b005c663eae38dsi6961005pgm.370.2023.12.06.02.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 02:59:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 7DB8A802BE70; Wed, 6 Dec 2023 02:59:17 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377913AbjLFK7F (ORCPT + 99 others); Wed, 6 Dec 2023 05:59:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377883AbjLFK7B (ORCPT ); Wed, 6 Dec 2023 05:59:01 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A93E1700; Wed, 6 Dec 2023 02:58:51 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 567D824E2E2; Wed, 6 Dec 2023 18:58:45 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:45 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:44 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 03/21] PCI: microchip: Move PLDA IP register macros to pcie-plda.h Date: Wed, 6 Dec 2023 18:58:21 +0800 Message-ID: <20231206105839.25805-4-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 02:59:17 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784529926965001332 X-GMAIL-MSGID: 1784529926965001332 Move PLDA PCIe host controller IP registers macros to pcie-plda.h, including bridge registers and local IRQ event number. Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- MAINTAINERS | 8 ++ .../pci/controller/plda/pcie-microchip-host.c | 108 +++--------------- drivers/pci/controller/plda/pcie-plda.h | 102 +++++++++++++++++ 3 files changed, 126 insertions(+), 92 deletions(-) create mode 100644 drivers/pci/controller/plda/pcie-plda.h diff --git a/MAINTAINERS b/MAINTAINERS index 46728cc258ca..a034ef4cce93 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16610,6 +16610,14 @@ S: Maintained F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt F: drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c +PCI DRIVER FOR PLDA PCIE IP +M: Daire McNamara +M: Kevin Xie +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/plda,* +F: drivers/pci/controller/plda/*plda* + PCI DRIVER FOR RENESAS R-CAR M: Marek Vasut M: Yoshihiro Shimoda diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index cb09a8137e25..a34ec6aad4be 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -19,6 +19,7 @@ #include #include "../../pci.h" +#include "pcie-plda.h" /* Number of MSI IRQs */ #define MC_MAX_NUM_MSI_IRQS 32 @@ -30,84 +31,6 @@ #define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR) #define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR) -/* PCIe Bridge Phy Regs */ -#define PCIE_PCI_IRQ_DW0 0xa8 -#define MSIX_CAP_MASK BIT(31) -#define NUM_MSI_MSGS_MASK GENMASK(6, 4) -#define NUM_MSI_MSGS_SHIFT 4 - -#define IMASK_LOCAL 0x180 -#define DMA_END_ENGINE_0_MASK 0x00000000u -#define DMA_END_ENGINE_0_SHIFT 0 -#define DMA_END_ENGINE_1_MASK 0x00000000u -#define DMA_END_ENGINE_1_SHIFT 1 -#define DMA_ERROR_ENGINE_0_MASK 0x00000100u -#define DMA_ERROR_ENGINE_0_SHIFT 8 -#define DMA_ERROR_ENGINE_1_MASK 0x00000200u -#define DMA_ERROR_ENGINE_1_SHIFT 9 -#define A_ATR_EVT_POST_ERR_MASK 0x00010000u -#define A_ATR_EVT_POST_ERR_SHIFT 16 -#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u -#define A_ATR_EVT_FETCH_ERR_SHIFT 17 -#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u -#define A_ATR_EVT_DISCARD_ERR_SHIFT 18 -#define A_ATR_EVT_DOORBELL_MASK 0x00000000u -#define A_ATR_EVT_DOORBELL_SHIFT 19 -#define P_ATR_EVT_POST_ERR_MASK 0x00100000u -#define P_ATR_EVT_POST_ERR_SHIFT 20 -#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u -#define P_ATR_EVT_FETCH_ERR_SHIFT 21 -#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u -#define P_ATR_EVT_DISCARD_ERR_SHIFT 22 -#define P_ATR_EVT_DOORBELL_MASK 0x00000000u -#define P_ATR_EVT_DOORBELL_SHIFT 23 -#define PM_MSI_INT_INTA_MASK 0x01000000u -#define PM_MSI_INT_INTA_SHIFT 24 -#define PM_MSI_INT_INTB_MASK 0x02000000u -#define PM_MSI_INT_INTB_SHIFT 25 -#define PM_MSI_INT_INTC_MASK 0x04000000u -#define PM_MSI_INT_INTC_SHIFT 26 -#define PM_MSI_INT_INTD_MASK 0x08000000u -#define PM_MSI_INT_INTD_SHIFT 27 -#define PM_MSI_INT_INTX_MASK 0x0f000000u -#define PM_MSI_INT_INTX_SHIFT 24 -#define PM_MSI_INT_MSI_MASK 0x10000000u -#define PM_MSI_INT_MSI_SHIFT 28 -#define PM_MSI_INT_AER_EVT_MASK 0x20000000u -#define PM_MSI_INT_AER_EVT_SHIFT 29 -#define PM_MSI_INT_EVENTS_MASK 0x40000000u -#define PM_MSI_INT_EVENTS_SHIFT 30 -#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u -#define PM_MSI_INT_SYS_ERR_SHIFT 31 -#define NUM_LOCAL_EVENTS 15 -#define ISTATUS_LOCAL 0x184 -#define IMASK_HOST 0x188 -#define ISTATUS_HOST 0x18c -#define IMSI_ADDR 0x190 -#define ISTATUS_MSI 0x194 - -/* PCIe Master table init defines */ -#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u -#define ATR0_PCIE_ATR_SIZE 0x25 -#define ATR0_PCIE_ATR_SIZE_SHIFT 1 -#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u -#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u -#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu -#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u - -/* PCIe AXI slave table init defines */ -#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u -#define ATR_SIZE_SHIFT 1 -#define ATR_IMPL_ENABLE 1 -#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u -#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u -#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu -#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u -#define PCIE_TX_RX_INTERFACE 0x00000000u -#define PCIE_CONFIG_INTERFACE 0x00000001u - -#define ATR_ENTRY_SIZE 32 - /* PCIe Controller Phy Regs */ #define SEC_ERROR_EVENT_CNT 0x20 #define DED_ERROR_EVENT_CNT 0x24 @@ -179,20 +102,21 @@ #define EVENT_LOCAL_DMA_END_ENGINE_1 12 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14 -#define EVENT_LOCAL_A_ATR_EVT_POST_ERR 15 -#define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR 16 -#define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR 17 -#define EVENT_LOCAL_A_ATR_EVT_DOORBELL 18 -#define EVENT_LOCAL_P_ATR_EVT_POST_ERR 19 -#define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR 20 -#define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR 21 -#define EVENT_LOCAL_P_ATR_EVT_DOORBELL 22 -#define EVENT_LOCAL_PM_MSI_INT_INTX 23 -#define EVENT_LOCAL_PM_MSI_INT_MSI 24 -#define EVENT_LOCAL_PM_MSI_INT_AER_EVT 25 -#define EVENT_LOCAL_PM_MSI_INT_EVENTS 26 -#define EVENT_LOCAL_PM_MSI_INT_SYS_ERR 27 -#define NUM_EVENTS 28 +#define NUM_MC_EVENTS 15 +#define EVENT_LOCAL_A_ATR_EVT_POST_ERR (NUM_MC_EVENTS + EVENT_A_ATR_EVT_POST_ERR) +#define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + EVENT_A_ATR_EVT_FETCH_ERR) +#define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + EVENT_A_ATR_EVT_DISCARD_ERR) +#define EVENT_LOCAL_A_ATR_EVT_DOORBELL (NUM_MC_EVENTS + EVENT_A_ATR_EVT_DOORBELL) +#define EVENT_LOCAL_P_ATR_EVT_POST_ERR (NUM_MC_EVENTS + EVENT_P_ATR_EVT_POST_ERR) +#define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + EVENT_P_ATR_EVT_FETCH_ERR) +#define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + EVENT_P_ATR_EVT_DISCARD_ERR) +#define EVENT_LOCAL_P_ATR_EVT_DOORBELL (NUM_MC_EVENTS + EVENT_P_ATR_EVT_DOORBELL) +#define EVENT_LOCAL_PM_MSI_INT_INTX (NUM_MC_EVENTS + EVENT_PM_MSI_INT_INTX) +#define EVENT_LOCAL_PM_MSI_INT_MSI (NUM_MC_EVENTS + EVENT_PM_MSI_INT_MSI) +#define EVENT_LOCAL_PM_MSI_INT_AER_EVT (NUM_MC_EVENTS + EVENT_PM_MSI_INT_AER_EVT) +#define EVENT_LOCAL_PM_MSI_INT_EVENTS (NUM_MC_EVENTS + EVENT_PM_MSI_INT_EVENTS) +#define EVENT_LOCAL_PM_MSI_INT_SYS_ERR (NUM_MC_EVENTS + EVENT_PM_MSI_INT_SYS_ERR) +#define NUM_EVENTS (NUM_MC_EVENTS + NUM_PLDA_EVENTS) #define PCIE_EVENT_CAUSE(x, s) \ [EVENT_PCIE_ ## x] = { __stringify(x), s } diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h new file mode 100644 index 000000000000..727fc54312c9 --- /dev/null +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * PLDA PCIe host controller driver + */ + +#ifndef _PCIE_PLDA_H +#define _PCIE_PLDA_H + +/* PCIe Bridge Phy Regs */ +#define PCIE_PCI_IRQ_DW0 0xa8 +#define MSIX_CAP_MASK BIT(31) +#define NUM_MSI_MSGS_MASK GENMASK(6, 4) +#define NUM_MSI_MSGS_SHIFT 4 + +#define IMASK_LOCAL 0x180 +#define DMA_END_ENGINE_0_MASK 0x00000000u +#define DMA_END_ENGINE_0_SHIFT 0 +#define DMA_END_ENGINE_1_MASK 0x00000000u +#define DMA_END_ENGINE_1_SHIFT 1 +#define DMA_ERROR_ENGINE_0_MASK 0x00000100u +#define DMA_ERROR_ENGINE_0_SHIFT 8 +#define DMA_ERROR_ENGINE_1_MASK 0x00000200u +#define DMA_ERROR_ENGINE_1_SHIFT 9 +#define A_ATR_EVT_POST_ERR_MASK 0x00010000u +#define A_ATR_EVT_POST_ERR_SHIFT 16 +#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u +#define A_ATR_EVT_FETCH_ERR_SHIFT 17 +#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u +#define A_ATR_EVT_DISCARD_ERR_SHIFT 18 +#define A_ATR_EVT_DOORBELL_MASK 0x00000000u +#define A_ATR_EVT_DOORBELL_SHIFT 19 +#define P_ATR_EVT_POST_ERR_MASK 0x00100000u +#define P_ATR_EVT_POST_ERR_SHIFT 20 +#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u +#define P_ATR_EVT_FETCH_ERR_SHIFT 21 +#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u +#define P_ATR_EVT_DISCARD_ERR_SHIFT 22 +#define P_ATR_EVT_DOORBELL_MASK 0x00000000u +#define P_ATR_EVT_DOORBELL_SHIFT 23 +#define PM_MSI_INT_INTA_MASK 0x01000000u +#define PM_MSI_INT_INTA_SHIFT 24 +#define PM_MSI_INT_INTB_MASK 0x02000000u +#define PM_MSI_INT_INTB_SHIFT 25 +#define PM_MSI_INT_INTC_MASK 0x04000000u +#define PM_MSI_INT_INTC_SHIFT 26 +#define PM_MSI_INT_INTD_MASK 0x08000000u +#define PM_MSI_INT_INTD_SHIFT 27 +#define PM_MSI_INT_INTX_MASK 0x0f000000u +#define PM_MSI_INT_INTX_SHIFT 24 +#define PM_MSI_INT_MSI_MASK 0x10000000u +#define PM_MSI_INT_MSI_SHIFT 28 +#define PM_MSI_INT_AER_EVT_MASK 0x20000000u +#define PM_MSI_INT_AER_EVT_SHIFT 29 +#define PM_MSI_INT_EVENTS_MASK 0x40000000u +#define PM_MSI_INT_EVENTS_SHIFT 30 +#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u +#define PM_MSI_INT_SYS_ERR_SHIFT 31 +#define NUM_LOCAL_EVENTS 15 +#define ISTATUS_LOCAL 0x184 +#define IMASK_HOST 0x188 +#define ISTATUS_HOST 0x18c +#define IMSI_ADDR 0x190 +#define ISTATUS_MSI 0x194 + +/* PCIe Master table init defines */ +#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u +#define ATR0_PCIE_ATR_SIZE 0x25 +#define ATR0_PCIE_ATR_SIZE_SHIFT 1 +#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u +#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u +#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu +#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u + +/* PCIe AXI slave table init defines */ +#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u +#define ATR_SIZE_SHIFT 1 +#define ATR_IMPL_ENABLE 1 +#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u +#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u +#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu +#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u +#define PCIE_TX_RX_INTERFACE 0x00000000u +#define PCIE_CONFIG_INTERFACE 0x00000001u + +#define ATR_ENTRY_SIZE 32 + +#define EVENT_A_ATR_EVT_POST_ERR 0 +#define EVENT_A_ATR_EVT_FETCH_ERR 1 +#define EVENT_A_ATR_EVT_DISCARD_ERR 2 +#define EVENT_A_ATR_EVT_DOORBELL 3 +#define EVENT_P_ATR_EVT_POST_ERR 4 +#define EVENT_P_ATR_EVT_FETCH_ERR 5 +#define EVENT_P_ATR_EVT_DISCARD_ERR 6 +#define EVENT_P_ATR_EVT_DOORBELL 7 +#define EVENT_PM_MSI_INT_INTX 8 +#define EVENT_PM_MSI_INT_MSI 9 +#define EVENT_PM_MSI_INT_AER_EVT 10 +#define EVENT_PM_MSI_INT_EVENTS 11 +#define EVENT_PM_MSI_INT_SYS_ERR 12 +#define NUM_PLDA_EVENTS 13 + +#endif From patchwork Wed Dec 6 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[2620:137:e000::3:5]) by mx.google.com with ESMTPS id b5-20020a170902d88500b001d0b9edced7si3745228plz.581.2023.12.06.02.59.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 02:59:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 1892F803D02A; Wed, 6 Dec 2023 02:59:53 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377997AbjLFK7l (ORCPT + 99 others); Wed, 6 Dec 2023 05:59:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377959AbjLFK7O (ORCPT ); Wed, 6 Dec 2023 05:59:14 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 773C6D5B; Wed, 6 Dec 2023 02:58:54 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 33A0080C5; Wed, 6 Dec 2023 18:58:46 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:46 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:45 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 04/21] PCI: microchip: Add bridge_addr field to struct mc_pcie Date: Wed, 6 Dec 2023 18:58:22 +0800 Message-ID: <20231206105839.25805-5-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 06 Dec 2023 02:59:53 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784529966857646238 X-GMAIL-MSGID: 1784529966857646238 For bridge address base is common PLDA field, Add this to struct mc_pcie first. INTx and MSI codes interrupts codes will get the bridge base address from port->bridge_addr. These codes will be changed to common codes. axi_base_addr is Microchip its own data. Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 23 ++++++++----------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index a34ec6aad4be..60870ee1f1c9 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -195,6 +195,7 @@ struct mc_pcie { struct irq_domain *event_domain; raw_spinlock_t lock; struct mc_msi msi; + void __iomem *bridge_addr; }; struct cause { @@ -339,8 +340,7 @@ static void mc_handle_msi(struct irq_desc *desc) struct irq_chip *chip = irq_desc_get_chip(desc); struct device *dev = port->dev; struct mc_msi *msi = &port->msi; - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; unsigned long status; u32 bit; int ret; @@ -365,8 +365,7 @@ static void mc_handle_msi(struct irq_desc *desc) static void mc_msi_bottom_irq_ack(struct irq_data *data) { struct mc_pcie *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; u32 bitpos = data->hwirq; writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); @@ -488,8 +487,7 @@ static void mc_handle_intx(struct irq_desc *desc) struct mc_pcie *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct device *dev = port->dev; - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; unsigned long status; u32 bit; int ret; @@ -514,8 +512,7 @@ static void mc_handle_intx(struct irq_desc *desc) static void mc_ack_intx_irq(struct irq_data *data) { struct mc_pcie *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); @@ -524,8 +521,7 @@ static void mc_ack_intx_irq(struct irq_data *data) static void mc_mask_intx_irq(struct irq_data *data) { struct mc_pcie *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; unsigned long flags; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); u32 val; @@ -540,8 +536,7 @@ static void mc_mask_intx_irq(struct irq_data *data) static void mc_unmask_intx_irq(struct irq_data *data) { struct mc_pcie *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; unsigned long flags; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); u32 val; @@ -896,8 +891,7 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, static int mc_pcie_setup_windows(struct platform_device *pdev, struct mc_pcie *port) { - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; struct pci_host_bridge *bridge = platform_get_drvdata(pdev); struct resource_entry *entry; u64 pci_addr; @@ -1081,6 +1075,7 @@ static int mc_host_probe(struct platform_device *pdev) mc_disable_interrupts(port); bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + port->bridge_addr = bridge_base_addr; /* Allow enabling MSI by disabling MSI-X */ val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); From patchwork Wed Dec 6 10:58:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174491 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4023971vqy; Wed, 6 Dec 2023 02:59:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IFHxT7EtM87x8rGbAC8LoD/vYQk3GwtEdN+Y/aJed11v94kXSYiZrIpgfeMI3ac4KM2m1Jw X-Received: by 2002:a9d:798b:0:b0:6d8:7cf8:a069 with SMTP id h11-20020a9d798b000000b006d87cf8a069mr794575otm.75.1701860374800; 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[23.128.96.37]) by mx.google.com with ESMTPS id y184-20020a638ac1000000b005c668dc242asi6736804pgd.162.2023.12.06.02.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 02:59:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id C07E0802B059; Wed, 6 Dec 2023 02:59:33 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377968AbjLFK7W (ORCPT + 99 others); Wed, 6 Dec 2023 05:59:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377902AbjLFK7D (ORCPT ); Wed, 6 Dec 2023 05:59:03 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77A7CD5F; Wed, 6 Dec 2023 02:58:53 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id EB4E224E307; Wed, 6 Dec 2023 18:58:46 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:46 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:45 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 05/21] PCI: microchip: Rename two PCIe data structures Date: Wed, 6 Dec 2023 18:58:23 +0800 Message-ID: <20231206105839.25805-6-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 02:59:33 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784529944237099707 X-GMAIL-MSGID: 1784529944237099707 Add PLDA PCIe related data structures by rename data structure name from mc_* to plda_*. axi_base_addr is stayed in struct mc_pcie for it's microchip its own data. The event interrupt codes is still using struct mc_pcie because the event interrupt codes can not be re-used. The modification includes: mc_pcie --> plda_pcie_rp (Get most of data members) mc_msi --> plda_msi Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 96 ++++++++++--------- 1 file changed, 53 insertions(+), 43 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 60870ee1f1c9..3dc4d4ca9d0c 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -22,7 +22,7 @@ #include "pcie-plda.h" /* Number of MSI IRQs */ -#define MC_MAX_NUM_MSI_IRQS 32 +#define PLDA_MAX_NUM_MSI_IRQS 32 /* PCIe Bridge Phy and Controller Phy offsets */ #define MC_PCIE1_BRIDGE_ADDR 0x00008000u @@ -179,25 +179,29 @@ struct event_map { u32 event_bit; }; -struct mc_msi { +struct plda_msi { struct mutex lock; /* Protect used bitmap */ struct irq_domain *msi_domain; struct irq_domain *dev_domain; u32 num_vectors; u64 vector_phy; - DECLARE_BITMAP(used, MC_MAX_NUM_MSI_IRQS); + DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS); }; -struct mc_pcie { - void __iomem *axi_base_addr; +struct plda_pcie_rp { struct device *dev; struct irq_domain *intx_domain; struct irq_domain *event_domain; raw_spinlock_t lock; - struct mc_msi msi; + struct plda_msi msi; void __iomem *bridge_addr; }; +struct mc_pcie { + struct plda_pcie_rp plda; + void __iomem *axi_base_addr; +}; + struct cause { const char *sym; const char *str; @@ -313,7 +317,7 @@ static struct mc_pcie *port; static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) { - struct mc_msi *msi = &port->msi; + struct plda_msi *msi = &port->plda.msi; u16 reg; u8 queue_size; @@ -336,10 +340,10 @@ static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) static void mc_handle_msi(struct irq_desc *desc) { - struct mc_pcie *port = irq_desc_get_handler_data(desc); + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct device *dev = port->dev; - struct mc_msi *msi = &port->msi; + struct plda_msi *msi = &port->msi; void __iomem *bridge_base_addr = port->bridge_addr; unsigned long status; u32 bit; @@ -364,7 +368,7 @@ static void mc_handle_msi(struct irq_desc *desc) static void mc_msi_bottom_irq_ack(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; u32 bitpos = data->hwirq; @@ -373,7 +377,7 @@ static void mc_msi_bottom_irq_ack(struct irq_data *data) static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); phys_addr_t addr = port->msi.vector_phy; msg->address_lo = lower_32_bits(addr); @@ -400,8 +404,8 @@ static struct irq_chip mc_msi_bottom_irq_chip = { static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *args) { - struct mc_pcie *port = domain->host_data; - struct mc_msi *msi = &port->msi; + struct plda_pcie_rp *port = domain->host_data; + struct plda_msi *msi = &port->msi; unsigned long bit; mutex_lock(&msi->lock); @@ -425,8 +429,8 @@ static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { struct irq_data *d = irq_domain_get_irq_data(domain, virq); - struct mc_pcie *port = irq_data_get_irq_chip_data(d); - struct mc_msi *msi = &port->msi; + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); + struct plda_msi *msi = &port->msi; mutex_lock(&msi->lock); @@ -456,11 +460,11 @@ static struct msi_domain_info mc_msi_domain_info = { .chip = &mc_msi_irq_chip, }; -static int mc_allocate_msi_domains(struct mc_pcie *port) +static int mc_allocate_msi_domains(struct plda_pcie_rp *port) { struct device *dev = port->dev; struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); - struct mc_msi *msi = &port->msi; + struct plda_msi *msi = &port->msi; mutex_init(&port->msi.lock); @@ -484,7 +488,7 @@ static int mc_allocate_msi_domains(struct mc_pcie *port) static void mc_handle_intx(struct irq_desc *desc) { - struct mc_pcie *port = irq_desc_get_handler_data(desc); + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct device *dev = port->dev; void __iomem *bridge_base_addr = port->bridge_addr; @@ -511,7 +515,7 @@ static void mc_handle_intx(struct irq_desc *desc) static void mc_ack_intx_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); @@ -520,7 +524,7 @@ static void mc_ack_intx_irq(struct irq_data *data) static void mc_mask_intx_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; unsigned long flags; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); @@ -535,7 +539,7 @@ static void mc_mask_intx_irq(struct irq_data *data) static void mc_unmask_intx_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; unsigned long flags; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); @@ -625,21 +629,22 @@ static u32 local_events(struct mc_pcie *port) return val; } -static u32 get_events(struct mc_pcie *port) +static u32 get_events(struct plda_pcie_rp *port) { + struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); u32 events = 0; - events |= pcie_events(port); - events |= sec_errors(port); - events |= ded_errors(port); - events |= local_events(port); + events |= pcie_events(mc_port); + events |= sec_errors(mc_port); + events |= ded_errors(mc_port); + events |= local_events(mc_port); return events; } static irqreturn_t mc_event_handler(int irq, void *dev_id) { - struct mc_pcie *port = dev_id; + struct plda_pcie_rp *port = dev_id; struct device *dev = port->dev; struct irq_data *data; @@ -655,7 +660,7 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) static void mc_handle_event(struct irq_desc *desc) { - struct mc_pcie *port = irq_desc_get_handler_data(desc); + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); unsigned long events; u32 bit; struct irq_chip *chip = irq_desc_get_chip(desc); @@ -672,12 +677,13 @@ static void mc_handle_event(struct irq_desc *desc) static void mc_ack_event_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); u32 event = data->hwirq; void __iomem *addr; u32 mask; - addr = port->axi_base_addr + event_descs[event].base + + addr = mc_port->axi_base_addr + event_descs[event].base + event_descs[event].offset; mask = event_descs[event].mask; mask |= event_descs[event].enb_mask; @@ -687,13 +693,14 @@ static void mc_ack_event_irq(struct irq_data *data) static void mc_mask_event_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); u32 event = data->hwirq; void __iomem *addr; u32 mask; u32 val; - addr = port->axi_base_addr + event_descs[event].base + + addr = mc_port->axi_base_addr + event_descs[event].base + event_descs[event].mask_offset; mask = event_descs[event].mask; if (event_descs[event].enb_mask) { @@ -717,13 +724,14 @@ static void mc_mask_event_irq(struct irq_data *data) static void mc_unmask_event_irq(struct irq_data *data) { - struct mc_pcie *port = irq_data_get_irq_chip_data(data); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); u32 event = data->hwirq; void __iomem *addr; u32 mask; u32 val; - addr = port->axi_base_addr + event_descs[event].base + + addr = mc_port->axi_base_addr + event_descs[event].base + event_descs[event].mask_offset; mask = event_descs[event].mask; @@ -811,7 +819,7 @@ static int mc_pcie_init_clks(struct device *dev) return 0; } -static int mc_pcie_init_irq_domains(struct mc_pcie *port) +static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) { struct device *dev = port->dev; struct device_node *node = dev->of_node; @@ -889,7 +897,7 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, } static int mc_pcie_setup_windows(struct platform_device *pdev, - struct mc_pcie *port) + struct plda_pcie_rp *port) { void __iomem *bridge_base_addr = port->bridge_addr; struct pci_host_bridge *bridge = platform_get_drvdata(pdev); @@ -970,7 +978,7 @@ static void mc_disable_interrupts(struct mc_pcie *port) writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); } -static int mc_init_interrupts(struct platform_device *pdev, struct mc_pcie *port) +static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) { struct device *dev = &pdev->dev; int irq; @@ -1043,12 +1051,12 @@ static int mc_platform_init(struct pci_config_window *cfg) mc_pcie_enable_msi(port, cfg->win); /* Configure non-config space outbound ranges */ - ret = mc_pcie_setup_windows(pdev, port); + ret = mc_pcie_setup_windows(pdev, &port->plda); if (ret) return ret; /* Address translation is up; safe to enable interrupts */ - ret = mc_init_interrupts(pdev, port); + ret = mc_init_interrupts(pdev, &port->plda); if (ret) return ret; @@ -1059,6 +1067,7 @@ static int mc_host_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; void __iomem *bridge_base_addr; + struct plda_pcie_rp *plda; int ret; u32 val; @@ -1066,7 +1075,8 @@ static int mc_host_probe(struct platform_device *pdev) if (!port) return -ENOMEM; - port->dev = dev; + plda = &port->plda; + plda->dev = dev; port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(port->axi_base_addr)) @@ -1075,7 +1085,7 @@ static int mc_host_probe(struct platform_device *pdev) mc_disable_interrupts(port); bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; - port->bridge_addr = bridge_base_addr; + plda->bridge_addr = bridge_base_addr; /* Allow enabling MSI by disabling MSI-X */ val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); @@ -1087,10 +1097,10 @@ static int mc_host_probe(struct platform_device *pdev) val &= NUM_MSI_MSGS_MASK; val >>= NUM_MSI_MSGS_SHIFT; - port->msi.num_vectors = 1 << val; + plda->msi.num_vectors = 1 << val; /* Pick vector address from design */ - port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); + plda->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); ret = mc_pcie_init_clks(dev); if (ret) { From patchwork Wed Dec 6 10:58:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174492 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4023984vqy; Wed, 6 Dec 2023 02:59:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IEbNaT1tVZzinRgrdeTKWoOajVsHnnmybhszxf91vTxPOqPu8y7Ap3ZLFK87f6oI2uaMR7J X-Received: by 2002:a05:6830:160e:b0:6d8:74e2:94ee with SMTP id g14-20020a056830160e00b006d874e294eemr653959otr.52.1701860378554; Wed, 06 Dec 2023 02:59:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860378; cv=none; d=google.com; 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[2620:137:e000::3:3]) by mx.google.com with ESMTPS id z21-20020a630a55000000b005bdbe64cc26si11260846pgk.535.2023.12.06.02.59.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 02:59:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 92062802F44A; Wed, 6 Dec 2023 02:59:34 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377941AbjLFK7L (ORCPT + 99 others); Wed, 6 Dec 2023 05:59:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377837AbjLFK7B (ORCPT ); Wed, 6 Dec 2023 05:59:01 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C684110FC; Wed, 6 Dec 2023 02:58:51 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id BACE624E314; Wed, 6 Dec 2023 18:58:47 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:47 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:46 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 06/21] PCI: microchip: Move PCIe host data structures to plda-pcie.h Date: Wed, 6 Dec 2023 18:58:24 +0800 Message-ID: <20231206105839.25805-7-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 06 Dec 2023 02:59:34 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784529947949036369 X-GMAIL-MSGID: 1784529947949036369 Move the common data structures definition to head file for these two data structures can be re-used. Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 20 ------------------ drivers/pci/controller/plda/pcie-plda.h | 21 +++++++++++++++++++ 2 files changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 3dc4d4ca9d0c..261147a0a446 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -21,9 +21,6 @@ #include "../../pci.h" #include "pcie-plda.h" -/* Number of MSI IRQs */ -#define PLDA_MAX_NUM_MSI_IRQS 32 - /* PCIe Bridge Phy and Controller Phy offsets */ #define MC_PCIE1_BRIDGE_ADDR 0x00008000u #define MC_PCIE1_CTRL_ADDR 0x0000a000u @@ -179,23 +176,6 @@ struct event_map { u32 event_bit; }; -struct plda_msi { - struct mutex lock; /* Protect used bitmap */ - struct irq_domain *msi_domain; - struct irq_domain *dev_domain; - u32 num_vectors; - u64 vector_phy; - DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS); -}; - -struct plda_pcie_rp { - struct device *dev; - struct irq_domain *intx_domain; - struct irq_domain *event_domain; - raw_spinlock_t lock; - struct plda_msi msi; - void __iomem *bridge_addr; -}; struct mc_pcie { struct plda_pcie_rp plda; diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index 727fc54312c9..363fcbbaf6ec 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -6,6 +6,9 @@ #ifndef _PCIE_PLDA_H #define _PCIE_PLDA_H +/* Number of MSI IRQs */ +#define PLDA_MAX_NUM_MSI_IRQS 32 + /* PCIe Bridge Phy Regs */ #define PCIE_PCI_IRQ_DW0 0xa8 #define MSIX_CAP_MASK BIT(31) @@ -99,4 +102,22 @@ #define EVENT_PM_MSI_INT_SYS_ERR 12 #define NUM_PLDA_EVENTS 13 +struct plda_msi { + struct mutex lock; /* Protect used bitmap */ + struct irq_domain *msi_domain; + struct irq_domain *dev_domain; + u32 num_vectors; + u64 vector_phy; + DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS); +}; + +struct plda_pcie_rp { + struct device *dev; + struct irq_domain *intx_domain; + struct irq_domain *event_domain; + raw_spinlock_t lock; + struct plda_msi msi; + void __iomem *bridge_addr; +}; + #endif From patchwork Wed Dec 6 10:58:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174490 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4023943vqy; Wed, 6 Dec 2023 02:59:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IFdG2CSdKU52nX9621u/nsq+vKXFPhvjDfliN/L+4FY6pNS/BTwjdKYYvdYWL1tL9zpcTMH X-Received: by 2002:a17:902:ea86:b0:1d0:7908:ab64 with SMTP id x6-20020a170902ea8600b001d07908ab64mr1065228plb.10.1701860370652; Wed, 06 Dec 2023 02:59:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860370; cv=none; d=google.com; s=arc-20160816; b=g5MZMJDkffkhJjGKIPEJco1iv79tV8CV9OP6jPLZI44X28UyQpOXL2MQtI47SJ0n0Y KWcl/bbM05ITEYQ4z84JQra8dNOkjpC6PQN7ylBc/jZVyBrqZRfC/LSXq0eUzKJeHf8B A+RcbjK/uL2e6zPqxMMcU8KXp5tmDBEYK/O9Zdo3JL/gvlOLJmmGH7BkD+muBSkK1zOr VK77hnvGEbFmC9LKWtfD4aOj69LIj0cG4mJiicrimpLYjv/3iuX60oEs2wVLZe6RTnbh KIcfAIEB0VRnyJxT5m//xILvppUBL/WQFsXP889ewlJcgg/JQYQQUjUurzE1OmWYB+JX jw6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=jQZq/YQDnR3Pr/RcapRDcBqrLga+xw4R46ixTtMt38U=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=g8QFcI3Zdgl9shG2LEp7q5uMPD/VBsnepgPjZg9mX6Dj11fvcsnuh8vZtu2UI4BXBu 8i4+JEF5xZWcU9G3SjXLkD9mvHtJPh7mkyvL/GxWtQmRI41wNvWEWqDN84qqciPb671Y 7EM9txkpDAzyDmZZwi8HDnmi34xz3tcjKCgcxOYvwsrazFRxfIMaW8T11ii03/94MjGI 13leDEf0IL1A4K9caeLz1UeXgYjqlCcqE8PqxaK7i9gkAtxPR9YDohgqKf/gytIz3bxa YaDIJJijC1MSdvkm1aM+bsFrjz70Gnq8U7b/BFW5LfQFcSGP1QFyi+qm62DZG5UDG8gS SvVg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id z8-20020a170902708800b001cf5cb58df6si11096309plk.73.2023.12.06.02.59.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 02:59:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id A7A20802B055; Wed, 6 Dec 2023 02:59:28 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377950AbjLFK7T (ORCPT + 99 others); Wed, 6 Dec 2023 05:59:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377894AbjLFK7D (ORCPT ); Wed, 6 Dec 2023 05:59:03 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EB59135; Wed, 6 Dec 2023 02:58:54 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 9D4DE80A7; Wed, 6 Dec 2023 18:58:48 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:48 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:47 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 07/21] PCI: microchip: Rename two setup functions Date: Wed, 6 Dec 2023 18:58:25 +0800 Message-ID: <20231206105839.25805-8-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 02:59:28 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784529940202218947 X-GMAIL-MSGID: 1784529940202218947 Rename two setup functions to plda prefix. Prepare to re-use these two setup function. For two setup functions names are similar, rename mc_pcie_setup_windows() to plda_pcie_setup_iomems(). Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 261147a0a446..4877d130ee4c 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -838,9 +838,9 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) return mc_allocate_msi_domains(port); } -static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, - phys_addr_t axi_addr, phys_addr_t pci_addr, - size_t size) +static void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, + phys_addr_t axi_addr, phys_addr_t pci_addr, + size_t size) { u32 atr_sz = ilog2(size) - 1; u32 val; @@ -876,8 +876,8 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); } -static int mc_pcie_setup_windows(struct platform_device *pdev, - struct plda_pcie_rp *port) +static int plda_pcie_setup_iomems(struct platform_device *pdev, + struct plda_pcie_rp *port) { void __iomem *bridge_base_addr = port->bridge_addr; struct pci_host_bridge *bridge = platform_get_drvdata(pdev); @@ -888,9 +888,9 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, resource_list_for_each_entry(entry, &bridge->windows) { if (resource_type(entry->res) == IORESOURCE_MEM) { pci_addr = entry->res->start - entry->offset; - mc_pcie_setup_window(bridge_base_addr, index, - entry->res->start, pci_addr, - resource_size(entry->res)); + plda_pcie_setup_window(bridge_base_addr, index, + entry->res->start, pci_addr, + resource_size(entry->res)); index++; } } @@ -1023,15 +1023,15 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, - resource_size(&cfg->res)); + plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, + cfg->res.start, + resource_size(&cfg->res)); /* Need some fixups in config space */ mc_pcie_enable_msi(port, cfg->win); /* Configure non-config space outbound ranges */ - ret = mc_pcie_setup_windows(pdev, &port->plda); + ret = plda_pcie_setup_iomems(pdev, &port->plda); if (ret) return ret; From patchwork Wed Dec 6 10:58:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174486 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4023844vqy; Wed, 6 Dec 2023 02:59:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IET8D2hBHvRDlhVvyEIvy6jUVnJI/DLmE5LtwxqEYEHYo/Lm/dDCBBIcA/6n1tyU3mgYyfG X-Received: by 2002:a17:90a:17eb:b0:286:8abc:e66 with SMTP id q98-20020a17090a17eb00b002868abc0e66mr913357pja.42.1701860354894; Wed, 06 Dec 2023 02:59:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860354; cv=none; d=google.com; s=arc-20160816; b=jHZ4WbBnnVAd6xwcNeOXXyINNwi/yarlaj/Zy8tOfsVcjK+ECgJqTb2/9Bhes3qmmf Yqz9s25mjCyYsi2Xv2dC07BvOUeqzTdyT9cQjHZwdM0mEIlllfmJHxqviUQiRSGfjOlU Jkw5N1089fOlbkmet6qKn28jE5qZeJ2rnpq/ravKy2YUHmgYPwLrUOHi5DJ2AY3LTXJp R2QnbUvm5idzx74CytOZ6rwmN3Sr+bVtUFZSbiBhizRpXmRkYwYeEZtEZyZBYayYAD8N outvd2tJXa5VLRqMgE66IzN/MQcxkGRipOeQWbBWycCy28wo97ySqEvIIF2GqVYyLScl fkvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=GO+1rX1I4UT1MiT5u2qbeRFKm0W9wcXM4jsnuvUR7YM=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=cgfkPQb7f+g7ZJvnguZG/7CgRmLdcowgDRIokNFhor3f3p82neh+2sXo91OWn6MbMi bBSQla807vO65wFaoC8gyirew4gNfs86JT478F1B3ga2jUZpjxQX58p3kKOeU7nSqoU/ OToIs2kcKPVYpPBXSdFVKP5wZuR3yf2NsZGoFbd4c1gUylqYrRjBYMUrQzXia8pyEITl NBiduUuJgoACFIGoQV4bdXE2fcUo82bBuoTAch8NBFJaWiUxpXjpnGOe5mrpYiUt//TX OaOGRkfn79ZFlHCgoXHwR1ZB5MHgMeINktYubQsrCsAvMMbRt/xBdzfn+oUsYiieB7a4 FXmg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id f8-20020a17090a9b0800b002859d83de02si11454551pjp.139.2023.12.06.02.59.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 02:59:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 04F6A8040380; Wed, 6 Dec 2023 02:59:12 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377892AbjLFK7D (ORCPT + 99 others); Wed, 6 Dec 2023 05:59:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377838AbjLFK7B (ORCPT ); Wed, 6 Dec 2023 05:59:01 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 773161BD; Wed, 6 Dec 2023 02:58:54 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 9FDE180C7; Wed, 6 Dec 2023 18:58:49 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:49 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:48 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 08/21] PCI: microchip: Change the argument of plda_pcie_setup_iomems() Date: Wed, 6 Dec 2023 18:58:26 +0800 Message-ID: <20231206105839.25805-9-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 06 Dec 2023 02:59:12 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784529923440441797 X-GMAIL-MSGID: 1784529923440441797 If other vendor do not select PCI_HOST_COMMON, the driver data is not struct pci_host_bridge. Move calling platform_get_drvdata() to mc_platform_init(). Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- drivers/pci/controller/plda/pcie-microchip-host.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 4877d130ee4c..31ca8d44ee2a 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -876,11 +876,10 @@ static void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); } -static int plda_pcie_setup_iomems(struct platform_device *pdev, +static int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, struct plda_pcie_rp *port) { void __iomem *bridge_base_addr = port->bridge_addr; - struct pci_host_bridge *bridge = platform_get_drvdata(pdev); struct resource_entry *entry; u64 pci_addr; u32 index = 1; @@ -1018,6 +1017,7 @@ static int mc_platform_init(struct pci_config_window *cfg) { struct device *dev = cfg->parent; struct platform_device *pdev = to_platform_device(dev); + struct pci_host_bridge *bridge = platform_get_drvdata(pdev); void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; int ret; @@ -1031,7 +1031,7 @@ static int mc_platform_init(struct pci_config_window *cfg) mc_pcie_enable_msi(port, cfg->win); /* Configure non-config space outbound ranges */ - ret = plda_pcie_setup_iomems(pdev, &port->plda); + ret = plda_pcie_setup_iomems(bridge, &port->plda); if (ret) return ret; From patchwork Wed Dec 6 10:58:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174489 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4023923vqy; Wed, 6 Dec 2023 02:59:27 -0800 (PST) X-Google-Smtp-Source: AGHT+IE/KMZ+agyqRSIEMNur3Z9uAwc9CKl0AXcIfl2icc4MC99eP68L28bI6PHcqAcIeXQ3GeHO X-Received: by 2002:a17:903:22d0:b0:1d0:6ffd:6e69 with SMTP id y16-20020a17090322d000b001d06ffd6e69mr477703plg.97.1701860367544; Wed, 06 Dec 2023 02:59:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860367; cv=none; d=google.com; s=arc-20160816; b=ZlW1t1p9C6Ei21aNf/3uekZRQpq5QdrZr+R02cKfpNLuq5ytoOWwicd2KcRThGrP4S wqZtWU+ecWxAq1BuECBSQ6rC14juTtkNoPLll2y1pDplEI9drlJTDpPZDxJUYCI0fICc fVmga2iF5HI++fwBB+35qZbkb1slmWIlgjb5FMCmAQWvqXC6zoU2BCuw9LpSmx6yFphY e+CUJ9klszf6+T/LYYAGbK5+kgyWQcK5FOz6hdjF6uBZ+oUcdEdft0SwFc2IsYx4n3Sz GJOqD63rGzclnVhM38xtZHjanMKXLtHBAFe27aKOZA2DS60581vomC0uDnw2RO4M9bOj 0tzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=HT+C62rzedQZz/Ax7lSkHoej6hQLWKhZ9ZD0r+oqlf8=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=z2ew5qXJ8RLuabD7xsaNXQ3MHvLBFIDUPk264GBNshRUQFd48znvRO9p+DBs6AbNNG DGWOOmOvcVOC3kDlzJySzmJnZaz0blnQF6SJf7UydpOSq6vaSP8rLA/4G5fkJlc22zWb aKiWRiefA1TXu36nXb+JVODmM9DzPVGwdRNmpy3lIcq2trvsZMoV3JKH4riBT70bUXu0 3gFLoH1P3xDDJwj5pv7bIgLhmeaP8zORKf/1GPdmu2jvslFAEI+BMJO2l2XH47FBxrOf 26J0176+FxfuC5z94Epm0sIpe0nqg/xfxJKrGPsmUOFwH2PsRYe4Gtt80vkVMNj+bRW8 ghwg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id f9-20020a170902684900b001c9c83947d1si3693018pln.645.2023.12.06.02.59.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 02:59:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 05F11802B043; Wed, 6 Dec 2023 02:59:26 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377952AbjLFK7O (ORCPT + 99 others); Wed, 6 Dec 2023 05:59:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377886AbjLFK7B (ORCPT ); Wed, 6 Dec 2023 05:59:01 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4239518D; Wed, 6 Dec 2023 02:58:51 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 69CEC24E315; Wed, 6 Dec 2023 18:58:50 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:50 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:49 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 09/21] PCI: microchip: Move setup functions to pcie-plda-host.c Date: Wed, 6 Dec 2023 18:58:27 +0800 Message-ID: <20231206105839.25805-10-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 02:59:26 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784529936806507231 X-GMAIL-MSGID: 1784529936806507231 Move setup functions to common pcie-plda-host.c. So these two functions can be re-used. Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- drivers/pci/controller/plda/Kconfig | 4 + drivers/pci/controller/plda/Makefile | 1 + .../pci/controller/plda/pcie-microchip-host.c | 59 -------------- drivers/pci/controller/plda/pcie-plda-host.c | 80 +++++++++++++++++++ drivers/pci/controller/plda/pcie-plda.h | 5 ++ 5 files changed, 90 insertions(+), 59 deletions(-) create mode 100644 drivers/pci/controller/plda/pcie-plda-host.c diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig index 5cb3be4fc98c..e54a82ee94f5 100644 --- a/drivers/pci/controller/plda/Kconfig +++ b/drivers/pci/controller/plda/Kconfig @@ -3,10 +3,14 @@ menu "PLDA-based PCIe controllers" depends on PCI +config PCIE_PLDA_HOST + bool + config PCIE_MICROCHIP_HOST tristate "Microchip AXI PCIe controller" depends on PCI_MSI && OF select PCI_HOST_COMMON + select PCIE_PLDA_HOST help Say Y here if you want kernel to support the Microchip AXI PCIe Host Bridge driver. diff --git a/drivers/pci/controller/plda/Makefile b/drivers/pci/controller/plda/Makefile index e1a265cbf91c..4340ab007f44 100644 --- a/drivers/pci/controller/plda/Makefile +++ b/drivers/pci/controller/plda/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PCIE_PLDA_HOST) += pcie-plda-host.o obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 31ca8d44ee2a..2e79bcc7c0a5 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -838,65 +838,6 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) return mc_allocate_msi_domains(port); } -static void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, - phys_addr_t axi_addr, phys_addr_t pci_addr, - size_t size) -{ - u32 atr_sz = ilog2(size) - 1; - u32 val; - - if (index == 0) - val = PCIE_CONFIG_INTERFACE; - else - val = PCIE_TX_RX_INTERFACE; - - writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + - ATR0_AXI4_SLV0_TRSL_PARAM); - - val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | - ATR_IMPL_ENABLE; - writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + - ATR0_AXI4_SLV0_SRCADDR_PARAM); - - val = upper_32_bits(axi_addr); - writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + - ATR0_AXI4_SLV0_SRC_ADDR); - - val = lower_32_bits(pci_addr); - writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + - ATR0_AXI4_SLV0_TRSL_ADDR_LSB); - - val = upper_32_bits(pci_addr); - writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + - ATR0_AXI4_SLV0_TRSL_ADDR_UDW); - - val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); - val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); - writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); - writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); -} - -static int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, - struct plda_pcie_rp *port) -{ - void __iomem *bridge_base_addr = port->bridge_addr; - struct resource_entry *entry; - u64 pci_addr; - u32 index = 1; - - resource_list_for_each_entry(entry, &bridge->windows) { - if (resource_type(entry->res) == IORESOURCE_MEM) { - pci_addr = entry->res->start - entry->offset; - plda_pcie_setup_window(bridge_base_addr, index, - entry->res->start, pci_addr, - resource_size(entry->res)); - index++; - } - } - - return 0; -} - static inline void mc_clear_secs(struct mc_pcie *port) { void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c new file mode 100644 index 000000000000..19131181897f --- /dev/null +++ b/drivers/pci/controller/plda/pcie-plda-host.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PLDA PCIe XpressRich host controller driver + * + * Copyright (C) 2023 Microchip Co. Ltd + * + * Author: Daire McNamara + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-plda.h" + +void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, + phys_addr_t axi_addr, phys_addr_t pci_addr, + size_t size) +{ + u32 atr_sz = ilog2(size) - 1; + u32 val; + + if (index == 0) + val = PCIE_CONFIG_INTERFACE; + else + val = PCIE_TX_RX_INTERFACE; + + writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + + ATR0_AXI4_SLV0_TRSL_PARAM); + + val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | + ATR_IMPL_ENABLE; + writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + + ATR0_AXI4_SLV0_SRCADDR_PARAM); + + val = upper_32_bits(axi_addr); + writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + + ATR0_AXI4_SLV0_SRC_ADDR); + + val = lower_32_bits(pci_addr); + writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + + ATR0_AXI4_SLV0_TRSL_ADDR_LSB); + + val = upper_32_bits(pci_addr); + writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + + ATR0_AXI4_SLV0_TRSL_ADDR_UDW); + + val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); + val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); + writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); + writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); +} +EXPORT_SYMBOL_GPL(plda_pcie_setup_window); + +int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, + struct plda_pcie_rp *port) +{ + void __iomem *bridge_base_addr = port->bridge_addr; + struct resource_entry *entry; + u64 pci_addr; + u32 index = 1; + + resource_list_for_each_entry(entry, &bridge->windows) { + if (resource_type(entry->res) == IORESOURCE_MEM) { + pci_addr = entry->res->start - entry->offset; + plda_pcie_setup_window(bridge_base_addr, index, + entry->res->start, pci_addr, + resource_size(entry->res)); + index++; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(plda_pcie_setup_iomems); diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index 363fcbbaf6ec..3deefd35fa5a 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -120,4 +120,9 @@ struct plda_pcie_rp { void __iomem *bridge_addr; }; +void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, + phys_addr_t axi_addr, phys_addr_t pci_addr, + size_t size); +int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, + struct plda_pcie_rp *port); #endif From patchwork Wed Dec 6 10:58:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174498 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4024967vqy; Wed, 6 Dec 2023 03:01:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IEyQ8pwvMEQVxEq7yFXiQ+ngAbxgj44rhH+ISYo6ksgEBaHtAkuNOOBCXy+0pMFlG6cpEMf X-Received: by 2002:a05:6a20:4282:b0:181:74fe:ba83 with SMTP id o2-20020a056a20428200b0018174feba83mr606283pzj.40.1701860484136; Wed, 06 Dec 2023 03:01:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860484; cv=none; d=google.com; s=arc-20160816; b=AuP9v0SAIhisDx+rW04jJlQ1u+Huy2vrz5cFhRJKnEi2KZhKlp++/pBMzikBpWbRpA BmsJoNU7Cjegty/YYdpTiRcdnd6TnnC6bkv/p5h8dk2r2bxalwdD3jj5bRpoz84xgLAD Lgb4YHXfqRvGaXcYxZDfvfZbrCMDbGjxlKpBYiZIiqVcH+FLD/Nyw5WD5C5IF7kWDIK0 YKp/+bhwHhAEn6Qc3RBg0cuV/TZdzLVCov6DUNH624XJL3q/5Y6b5Ctk6kJnlpYrRoIy FNTH43Q9N++Ltr7QFNZmEy/MHEgGuMwLbACGxJSm6AxyqT4X74OuDmsrVvGGYIkN7Gyd z+/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=FH61yWwTydSRZnqujAYQ10gEm5c9bqKoI6Uha5LLgQg=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=sm96B7dsEraTLiaVRIF/Z9hOuH6X4xzqcF6BGLz9/yfReliGWICARqRYYXjkAdwcZo R9YT18NLATwLzFVBB3t2qDkRa/wKdQo1JowIFQkTUMpE/XI/edCwuHxMDcVAsB00368e ZWVlSpvH4/Yf/ZQDkuyaLI4hGLskn6EmvnhsllqqgXUhd9c024yD4lfXFXVvOar6pvsk cmfRv5m/IWmiB/TSjw+gXy59UfJvnU0Hf8U5c3xlf5MDvUIssDB/tPxZfY8Ns8XtHN0Y GqKqbiF2/AFes1nNkUWVg9+v2t6ol5Ywx8KOrnkPSZCzJonx4hA5ovARJ7LOrE3p9ffu lT0A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id fj8-20020a056a003a0800b0068e3efffe2csi11335553pfb.243.2023.12.06.03.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:01:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id B060480756E2; Wed, 6 Dec 2023 03:00:18 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378111AbjLFLAJ (ORCPT + 99 others); Wed, 6 Dec 2023 06:00:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377954AbjLFK7f (ORCPT ); Wed, 6 Dec 2023 05:59:35 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC8CCD72; Wed, 6 Dec 2023 02:59:07 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 3FED124E31A; Wed, 6 Dec 2023 18:58:51 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:51 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:50 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 10/21] PCI: microchip: Rename interrupt related functions Date: Wed, 6 Dec 2023 18:58:28 +0800 Message-ID: <20231206105839.25805-11-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:00:20 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530059047613982 X-GMAIL-MSGID: 1784530059047613982 Rename mc_* to plda_* for IRQ functions and related IRQ domain ops data instances. MSI, INTx interrupt codes and IRQ init codes are all can be re-used. - function rename list: mc_allocate_msi_domains() --> plda_allocate_msi_domains() mc_init_interrupts() --> plda_init_interrupts() mc_pcie_init_irq_domain() --> plda_pcie_init_irq_domains() mc_handle_event() --> plda_handle_event() get_events() --> mc_get_events() MSI interrupts related functions and IRQ domain (primary function is mc_handle_msi()): mc_handle_msi() --> plda_handle_msi() INTx interrupts related functions and IRQ domain (primary function is mc_handle_intx()): mc_handle_intx() --> plda_handle_intx() Signed-off-by: Minda Chen Acked-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 105 +++++++++--------- 1 file changed, 55 insertions(+), 50 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 2e79bcc7c0a5..54a0d431a471 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -318,7 +318,7 @@ static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI); } -static void mc_handle_msi(struct irq_desc *desc) +static void plda_handle_msi(struct irq_desc *desc) { struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); @@ -333,7 +333,8 @@ static void mc_handle_msi(struct irq_desc *desc) status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); if (status & PM_MSI_INT_MSI_MASK) { - writel_relaxed(status & PM_MSI_INT_MSI_MASK, bridge_base_addr + ISTATUS_LOCAL); + writel_relaxed(status & PM_MSI_INT_MSI_MASK, + bridge_base_addr + ISTATUS_LOCAL); status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); for_each_set_bit(bit, &status, msi->num_vectors) { ret = generic_handle_domain_irq(msi->dev_domain, bit); @@ -346,7 +347,7 @@ static void mc_handle_msi(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static void mc_msi_bottom_irq_ack(struct irq_data *data) +static void plda_msi_bottom_irq_ack(struct irq_data *data) { struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; @@ -355,7 +356,7 @@ static void mc_msi_bottom_irq_ack(struct irq_data *data) writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); } -static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); phys_addr_t addr = port->msi.vector_phy; @@ -368,21 +369,23 @@ static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) (int)data->hwirq, msg->address_hi, msg->address_lo); } -static int mc_msi_set_affinity(struct irq_data *irq_data, - const struct cpumask *mask, bool force) +static int plda_msi_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) { return -EINVAL; } -static struct irq_chip mc_msi_bottom_irq_chip = { - .name = "Microchip MSI", - .irq_ack = mc_msi_bottom_irq_ack, - .irq_compose_msi_msg = mc_compose_msi_msg, - .irq_set_affinity = mc_msi_set_affinity, +static struct irq_chip plda_msi_bottom_irq_chip = { + .name = "PLDA MSI", + .irq_ack = plda_msi_bottom_irq_ack, + .irq_compose_msi_msg = plda_compose_msi_msg, + .irq_set_affinity = plda_msi_set_affinity, }; -static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs, void *args) +static int plda_irq_msi_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, + void *args) { struct plda_pcie_rp *port = domain->host_data; struct plda_msi *msi = &port->msi; @@ -397,7 +400,7 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, set_bit(bit, msi->used); - irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip, + irq_domain_set_info(domain, virq, bit, &plda_msi_bottom_irq_chip, domain->host_data, handle_edge_irq, NULL, NULL); mutex_unlock(&msi->lock); @@ -405,8 +408,9 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, return 0; } -static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs) +static void plda_irq_msi_domain_free(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs) { struct irq_data *d = irq_domain_get_irq_data(domain, virq); struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); @@ -423,24 +427,24 @@ static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, } static const struct irq_domain_ops msi_domain_ops = { - .alloc = mc_irq_msi_domain_alloc, - .free = mc_irq_msi_domain_free, + .alloc = plda_irq_msi_domain_alloc, + .free = plda_irq_msi_domain_free, }; -static struct irq_chip mc_msi_irq_chip = { - .name = "Microchip PCIe MSI", +static struct irq_chip plda_msi_irq_chip = { + .name = "PLDA PCIe MSI", .irq_ack = irq_chip_ack_parent, .irq_mask = pci_msi_mask_irq, .irq_unmask = pci_msi_unmask_irq, }; -static struct msi_domain_info mc_msi_domain_info = { +static struct msi_domain_info plda_msi_domain_info = { .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_PCI_MSIX), - .chip = &mc_msi_irq_chip, + .chip = &plda_msi_irq_chip, }; -static int mc_allocate_msi_domains(struct plda_pcie_rp *port) +static int plda_allocate_msi_domains(struct plda_pcie_rp *port) { struct device *dev = port->dev; struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); @@ -455,7 +459,8 @@ static int mc_allocate_msi_domains(struct plda_pcie_rp *port) return -ENOMEM; } - msi->msi_domain = pci_msi_create_irq_domain(fwnode, &mc_msi_domain_info, + msi->msi_domain = pci_msi_create_irq_domain(fwnode, + &plda_msi_domain_info, msi->dev_domain); if (!msi->msi_domain) { dev_err(dev, "failed to create MSI domain\n"); @@ -466,7 +471,7 @@ static int mc_allocate_msi_domains(struct plda_pcie_rp *port) return 0; } -static void mc_handle_intx(struct irq_desc *desc) +static void plda_handle_intx(struct irq_desc *desc) { struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); @@ -493,7 +498,7 @@ static void mc_handle_intx(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static void mc_ack_intx_irq(struct irq_data *data) +static void plda_ack_intx_irq(struct irq_data *data) { struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; @@ -502,7 +507,7 @@ static void mc_ack_intx_irq(struct irq_data *data) writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); } -static void mc_mask_intx_irq(struct irq_data *data) +static void plda_mask_intx_irq(struct irq_data *data) { struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; @@ -517,7 +522,7 @@ static void mc_mask_intx_irq(struct irq_data *data) raw_spin_unlock_irqrestore(&port->lock, flags); } -static void mc_unmask_intx_irq(struct irq_data *data) +static void plda_unmask_intx_irq(struct irq_data *data) { struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); void __iomem *bridge_base_addr = port->bridge_addr; @@ -532,24 +537,24 @@ static void mc_unmask_intx_irq(struct irq_data *data) raw_spin_unlock_irqrestore(&port->lock, flags); } -static struct irq_chip mc_intx_irq_chip = { - .name = "Microchip PCIe INTx", - .irq_ack = mc_ack_intx_irq, - .irq_mask = mc_mask_intx_irq, - .irq_unmask = mc_unmask_intx_irq, +static struct irq_chip plda_intx_irq_chip = { + .name = "PLDA PCIe INTx", + .irq_ack = plda_ack_intx_irq, + .irq_mask = plda_mask_intx_irq, + .irq_unmask = plda_unmask_intx_irq, }; -static int mc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, - irq_hw_number_t hwirq) +static int plda_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) { - irq_set_chip_and_handler(irq, &mc_intx_irq_chip, handle_level_irq); + irq_set_chip_and_handler(irq, &plda_intx_irq_chip, handle_level_irq); irq_set_chip_data(irq, domain->host_data); return 0; } static const struct irq_domain_ops intx_domain_ops = { - .map = mc_pcie_intx_map, + .map = plda_pcie_intx_map, }; static inline u32 reg_to_event(u32 reg, struct event_map field) @@ -609,7 +614,7 @@ static u32 local_events(struct mc_pcie *port) return val; } -static u32 get_events(struct plda_pcie_rp *port) +static u32 mc_get_events(struct plda_pcie_rp *port) { struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); u32 events = 0; @@ -638,7 +643,7 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static void mc_handle_event(struct irq_desc *desc) +static void plda_handle_event(struct irq_desc *desc) { struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); unsigned long events; @@ -647,7 +652,7 @@ static void mc_handle_event(struct irq_desc *desc) chained_irq_enter(chip, desc); - events = get_events(port); + events = mc_get_events(port); for_each_set_bit(bit, &events, NUM_EVENTS) generic_handle_domain_irq(port->event_domain, bit); @@ -750,7 +755,7 @@ static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq, return 0; } -static const struct irq_domain_ops event_domain_ops = { +static const struct irq_domain_ops mc_event_domain_ops = { .map = mc_pcie_event_map, }; @@ -799,7 +804,7 @@ static int mc_pcie_init_clks(struct device *dev) return 0; } -static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) +static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) { struct device *dev = port->dev; struct device_node *node = dev->of_node; @@ -813,7 +818,7 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) } port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS, - &event_domain_ops, port); + &mc_event_domain_ops, port); if (!port->event_domain) { dev_err(dev, "failed to get event domain\n"); of_node_put(pcie_intc_node); @@ -835,7 +840,7 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) of_node_put(pcie_intc_node); raw_spin_lock_init(&port->lock); - return mc_allocate_msi_domains(port); + return plda_allocate_msi_domains(port); } static inline void mc_clear_secs(struct mc_pcie *port) @@ -898,14 +903,14 @@ static void mc_disable_interrupts(struct mc_pcie *port) writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); } -static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) +static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) { struct device *dev = &pdev->dev; int irq; int i, intx_irq, msi_irq, event_irq; int ret; - ret = mc_pcie_init_irq_domains(port); + ret = plda_pcie_init_irq_domains(port); if (ret) { dev_err(dev, "failed creating IRQ domains\n"); return ret; @@ -938,7 +943,7 @@ static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp } /* Plug the INTx chained handler */ - irq_set_chained_handler_and_data(intx_irq, mc_handle_intx, port); + irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); msi_irq = irq_create_mapping(port->event_domain, EVENT_LOCAL_PM_MSI_INT_MSI); @@ -946,10 +951,10 @@ static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp return -ENXIO; /* Plug the MSI chained handler */ - irq_set_chained_handler_and_data(msi_irq, mc_handle_msi, port); + irq_set_chained_handler_and_data(msi_irq, plda_handle_msi, port); /* Plug the main event chained handler */ - irq_set_chained_handler_and_data(irq, mc_handle_event, port); + irq_set_chained_handler_and_data(irq, plda_handle_event, port); return 0; } @@ -977,7 +982,7 @@ static int mc_platform_init(struct pci_config_window *cfg) return ret; /* Address translation is up; safe to enable interrupts */ - ret = mc_init_interrupts(pdev, &port->plda); + ret = plda_init_interrupts(pdev, &port->plda); if (ret) return ret; From patchwork Wed Dec 6 10:58:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174496 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4024458vqy; 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[23.128.96.37]) by mx.google.com with ESMTPS id x22-20020a170902821600b001cfd52a2266si8259752pln.403.2023.12.06.03.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:00:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id E946D802B06F; Wed, 6 Dec 2023 03:00:27 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377941AbjLFLAN (ORCPT + 99 others); Wed, 6 Dec 2023 06:00:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378029AbjLFK7f (ORCPT ); Wed, 6 Dec 2023 05:59:35 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2DFCD1; Wed, 6 Dec 2023 02:59:09 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 1609180CF; Wed, 6 Dec 2023 18:58:52 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:52 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:50 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 11/21] PCI: microchip: Add num_events field to struct plda_pcie_rp Date: Wed, 6 Dec 2023 18:58:29 +0800 Message-ID: <20231206105839.25805-12-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:00:28 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530004981101900 X-GMAIL-MSGID: 1784530004981101900 The event num is different in other platform. For re-using interrupt process codes, replace macros with variable. Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- drivers/pci/controller/plda/pcie-microchip-host.c | 8 +++++--- drivers/pci/controller/plda/pcie-plda.h | 1 + 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 54a0d431a471..d42278c006bc 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -654,7 +654,7 @@ static void plda_handle_event(struct irq_desc *desc) events = mc_get_events(port); - for_each_set_bit(bit, &events, NUM_EVENTS) + for_each_set_bit(bit, &events, port->num_events) generic_handle_domain_irq(port->event_domain, bit); chained_irq_exit(chip, desc); @@ -817,7 +817,8 @@ static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) return -EINVAL; } - port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS, + port->event_domain = irq_domain_add_linear(pcie_intc_node, + port->num_events, &mc_event_domain_ops, port); if (!port->event_domain) { dev_err(dev, "failed to get event domain\n"); @@ -920,7 +921,7 @@ static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_r if (irq < 0) return -ENODEV; - for (i = 0; i < NUM_EVENTS; i++) { + for (i = 0; i < port->num_events; i++) { event_irq = irq_create_mapping(port->event_domain, i); if (!event_irq) { dev_err(dev, "failed to map hwirq %d\n", i); @@ -1012,6 +1013,7 @@ static int mc_host_probe(struct platform_device *pdev) bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; plda->bridge_addr = bridge_base_addr; + plda->num_events = NUM_EVENTS; /* Allow enabling MSI by disabling MSI-X */ val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index 3deefd35fa5a..e3d35cef9894 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -118,6 +118,7 @@ struct plda_pcie_rp { raw_spinlock_t lock; struct plda_msi msi; void __iomem *bridge_addr; + int num_events; }; void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, From patchwork Wed Dec 6 10:58:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174505 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4025424vqy; Wed, 6 Dec 2023 03:01:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IEE5ZAjrjXEza5nuscPoPsuj25n0LONlOIkLkaz8BC5DwPDNmaJ2g315Oks9YOIqmLPc5Kt X-Received: by 2002:a17:902:7b84:b0:1d0:6ffd:836b with SMTP id w4-20020a1709027b8400b001d06ffd836bmr384207pll.118.1701860519326; Wed, 06 Dec 2023 03:01:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860519; cv=none; d=google.com; s=arc-20160816; b=QoCnJutXspNOKoi1B8xas1ghp0+nBcJH/wMdpFNTFVTbVQytwKQruXxp+UTjXrPRt2 KiDLyy7pAZP/rMwNlGxS0JbIWrAfd7f+S76oWokC/p8qKm0a5mKu0YxQw3RxkdwWVqku t7CZu2dzrQQdnVtKbxt+sk8mKDHlkx15lbLw6yogwlz4Yvw5T2+HkrFG2ff5qD7VBg0W b2ISJQnZ2Kxp7gbXzL9F1EfnIiEU6vTK7quPt6I8PF3GARIz58pOW2BJH3GDkUVvCo3J jH5TDSRoN6oDGPEQ0bw3rD9tT3tEArYjWtBZbj71NcyBzNxYtYW3pZbA4Pz51H6V7rwE ut2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=Ke+uJ6ccoSuPNMaSI3MbA0ie9l+UyrRaoVEmaCQFW8k=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=gbAdyjo/3D7hQKLMxChdw299jeVWtuFUJjSZIKyBmVBGjEAqN9QJUE83cQrXeTeP4h NyZhZqBOgdc8lmbBuzY44/ZEvTG/4leMpJdbLW25vXQ416pMV7sGXLVv7jxIPTtHr1yw fm661vWeD2D11DPOfuv/NZN6Yum8XzoUHWrAnN1KHnt/Kag4VS1Rh2vKJho7263+i1ws WQDKpTDoJ6lSnrtLzCmvJJ4flj/j8yCa5Rgzi2hErt+DvQh2YmPTX/nIFUwMf/LobDvk XE1jm3Gy61CgwNEBII3pPAg45V2i3vfIu4WrIlcBoYsTU8zB1jWYC8pHVERZ47yhEckm XIYg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id d10-20020a170903230a00b001cfd5a36b31si5568900plh.495.2023.12.06.03.01.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:01:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id C0BC3802AF20; Wed, 6 Dec 2023 03:00:47 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378133AbjLFLAZ (ORCPT + 99 others); Wed, 6 Dec 2023 06:00:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378032AbjLFK7f (ORCPT ); Wed, 6 Dec 2023 05:59:35 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3078012F; Wed, 6 Dec 2023 02:59:11 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id D870C80DF; Wed, 6 Dec 2023 18:58:52 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:52 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:51 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 12/21] PCI: microchip: Add request_event_irq() callback function Date: Wed, 6 Dec 2023 18:58:30 +0800 Message-ID: <20231206105839.25805-13-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:00:48 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530095549829517 X-GMAIL-MSGID: 1784530095549829517 PolarFire implements specific PCIe interrupts except PLDA local interrupt. For lack of MSI controller, these interrupts have to be added to global event field. PolarFire PCIe driver also register additional interrupt symbol name. PolarFire PCIe contain total 28 interrupts event while PLDA contain 13 local interrupts event, interrupt to event num mapping is different. So add a callback function to support different IRQ register function. Also Add PLDA default handler function, which will be moved to pcie- plda-host.c in moving codes patch. Signed-off-by: Minda Chen Acked-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 31 ++++++++++++++++--- drivers/pci/controller/plda/pcie-plda.h | 5 +++ 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index d42278c006bc..f89d102f4979 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -643,6 +643,11 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) return IRQ_HANDLED; } +static irqreturn_t plda_event_handler(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + static void plda_handle_event(struct irq_desc *desc) { struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); @@ -804,6 +809,17 @@ static int mc_pcie_init_clks(struct device *dev) return 0; } +static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, + int event) +{ + return devm_request_irq(plda->dev, event_irq, mc_event_handler, + 0, event_cause[event].sym, plda); +} + +static const struct plda_event mc_event = { + .request_event_irq = mc_request_event_irq, +}; + static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) { struct device *dev = port->dev; @@ -904,7 +920,9 @@ static void mc_disable_interrupts(struct mc_pcie *port) writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); } -static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) +static int plda_init_interrupts(struct platform_device *pdev, + struct plda_pcie_rp *port, + const struct plda_event *event) { struct device *dev = &pdev->dev; int irq; @@ -928,8 +946,13 @@ static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_r return -ENXIO; } - ret = devm_request_irq(dev, event_irq, mc_event_handler, - 0, event_cause[i].sym, port); + if (event->request_event_irq) + ret = event->request_event_irq(port, event_irq, i); + else + ret = devm_request_irq(dev, event_irq, + plda_event_handler, + 0, NULL, port); + if (ret) { dev_err(dev, "failed to request IRQ %d\n", event_irq); return ret; @@ -983,7 +1006,7 @@ static int mc_platform_init(struct pci_config_window *cfg) return ret; /* Address translation is up; safe to enable interrupts */ - ret = plda_init_interrupts(pdev, &port->plda); + ret = plda_init_interrupts(pdev, &port->plda, &mc_event); if (ret) return ret; diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index e3d35cef9894..28ed1374e1de 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -121,6 +121,11 @@ struct plda_pcie_rp { int num_events; }; +struct plda_event { + int (*request_event_irq)(struct plda_pcie_rp *pcie, + int event_irq, int event); +}; + void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, size_t size); From patchwork Wed Dec 6 10:58:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174495 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4024308vqy; Wed, 6 Dec 2023 03:00:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IFSgiiP/rxjN9L0eX48cGebB08gfv47/F6Ryi20T4jwHJkJ387qOmguN/xEJgHiJzkka4wf X-Received: by 2002:a05:6a20:a196:b0:18f:97c:8a40 with SMTP id r22-20020a056a20a19600b0018f097c8a40mr602101pzk.107.1701860419013; Wed, 06 Dec 2023 03:00:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860419; cv=none; d=google.com; s=arc-20160816; b=ukIrfVg6XlFlT1TDXv6hn80SgE+4AxU1QSGXkAFOScyV7a7ZYw16H491cJXYG+eC5C YM0pCv2JvFIvMRXCKnMI272QCGsfk7GPL2+FdQuZi1TIJHbbZOeTkqAZFYpPtcGKSNR0 jCJZPtLNDZbdPxWCkagvA+4VvYHCkleOLdeQ5OtARysfqtiAikAEeGMhTzW0fyu/5HB7 3PuMCVvsG0vO4q/xh0kLAtt18OEf9XLXfA6bdFeYbXJTTDnJ2wm1910cfNWoHZTd1v4C X5Z6Mu2joB2iDTzru9gnsocCZjlkmoR70rH+hS4D/316t7q0rTVYxfnyBtz9LcdgNBKd 6sFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=4E7jLlyNWDykg4K0Hs29SedYGWNS9nQGvx9EcIrgOUQ=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=DylfqnHFp3VEO50wsmtFhzo4hzPnO01A1aEmiZeDs/oUlJdCeFM/iruxu8v8FFF2D3 QE6UY4eF5tbafcWyq4QF0uTZkkm3Xvye931RmYKqKd3Ek/5Q8ZE9uLU89phXFf2LjS99 mLrJp84Nvj2xFAe3gyKsZ0dvScD9p1o5o3zIPBfxwNEDHH8BiGApy8XlHlpPp6X9jLPn y9bS1qlQjCbas7G3hL6PCQXYer2VkxqnwAJk8DWEeC1qrYZ+q0rnSWIv4gMfiq2yPxJA tbyedtOab/VyAT4qmFNTO54RogwMdDOAkyDT3hk+IlmZo3X9A5nxmriFHnTk6Q6bes6q BjxQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id s18-20020a656452000000b005b90b310e26si1529951pgv.403.2023.12.06.03.00.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:00:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 64EE2802B065; Wed, 6 Dec 2023 03:00:17 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378104AbjLFLAF (ORCPT + 99 others); Wed, 6 Dec 2023 06:00:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378026AbjLFK7e (ORCPT ); Wed, 6 Dec 2023 05:59:34 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18D3B10EF; Wed, 6 Dec 2023 02:59:08 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id AB54724E31B; Wed, 6 Dec 2023 18:58:53 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:53 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:52 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 13/21] PCI: microchip: Add INTx and MSI event num to struct plda_event Date: Wed, 6 Dec 2023 18:58:31 +0800 Message-ID: <20231206105839.25805-14-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:00:17 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784529990627335530 X-GMAIL-MSGID: 1784529990627335530 The INTx and MSI interrupt event num is different in Microchip and StarFive platform. Signed-off-by: Minda Chen Acked-by: Conor Dooley --- drivers/pci/controller/plda/pcie-microchip-host.c | 6 ++++-- drivers/pci/controller/plda/pcie-plda.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index f89d102f4979..2c03b0354f15 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -818,6 +818,8 @@ static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, static const struct plda_event mc_event = { .request_event_irq = mc_request_event_irq, + .intx_event = EVENT_LOCAL_PM_MSI_INT_INTX, + .msi_event = EVENT_LOCAL_PM_MSI_INT_MSI, }; static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) @@ -960,7 +962,7 @@ static int plda_init_interrupts(struct platform_device *pdev, } intx_irq = irq_create_mapping(port->event_domain, - EVENT_LOCAL_PM_MSI_INT_INTX); + event->intx_event); if (!intx_irq) { dev_err(dev, "failed to map INTx interrupt\n"); return -ENXIO; @@ -970,7 +972,7 @@ static int plda_init_interrupts(struct platform_device *pdev, irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); msi_irq = irq_create_mapping(port->event_domain, - EVENT_LOCAL_PM_MSI_INT_MSI); + event->msi_event); if (!msi_irq) return -ENXIO; diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index 28ed1374e1de..fba7343f9a96 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -124,6 +124,8 @@ struct plda_pcie_rp { struct plda_event { int (*request_event_irq)(struct plda_pcie_rp *pcie, int event_irq, int event); + int intx_event; + int msi_event; }; void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, From patchwork Wed Dec 6 10:58:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174504 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4025305vqy; Wed, 6 Dec 2023 03:01:48 -0800 (PST) X-Google-Smtp-Source: AGHT+IG0XVm3AxXN2C518GsIhLJU0B/PBcNMlUqkSMlPxUCj+qk76R/9u9exYUocype2uZRObIV2 X-Received: by 2002:a17:903:2489:b0:1d0:6ffd:9e24 with SMTP id p9-20020a170903248900b001d06ffd9e24mr580498plw.118.1701860508150; Wed, 06 Dec 2023 03:01:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860508; cv=none; d=google.com; s=arc-20160816; b=fDPDjhCVOQwBjmx9JSPUnvqHA4FvTJcX4sURl0H4JJmbBwwivyVapA1Hn83bCfA9uT +yJOv2zDvk+pLQyEOw2FjwBjo+cMf8im8OCDGM7jOtwPHOhcNmpk7plUrdXk8vmKzNz9 R6ENaMXfbo86GmVrb9ZsKscwk64r/yHFMo7syPsBXtRMe8A7Nys8PJ+rU2hXeDU4xdra 1AivoHItn++LScE1RZFzFVkDSXUavkxMLYw5qF8foXNLJETV8H1ZmYU7znJrDc2Odpx7 gQZmdwhcHV241u2AOL4lhzdGN1OzndJ+lG81ogfmSynmcXiykaArQBM12Zn12M5nhrHT tHAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=jWk1morY4fTlKolUiMWVEJoJoc9D6EuKnBuQztrQFQ4=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=Yiu8vJ5tJQNOl3yCKZV13tNJwtZfazZ++P1ELUUIqe3NObiEsPd9FINvr9xwMj5Qat smeF4rsTcecxdAXW2q62bjRwMzgUZfwadNo6MPF3QmsqobFE5lEaABvCWU+VppSRI7mF eCVmEliH7FDGBSGEBNvz9ElhlqLQrBqQ8tiNreciK5BG0ZRvVGJTbh8+2D7/Y+YeC4VG 6vpH6kTC73aw1Q5TGggxZcAw/VVyBmgTkBftk1dAn9gxPKL4agpdFD5/4ZXv9rrHiDz7 AKMmkEshAQPUR+2dCKXFZU0irFJs0F7gg5m1B/sToJaj6/ydtQZ49lUfwM4+7EDxb3Kr DjxQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from pete.vger.email (pete.vger.email. [2620:137:e000::3:6]) by mx.google.com with ESMTPS id c15-20020a170902d48f00b001d06ae1f9ccsi2028369plg.606.2023.12.06.03.01.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:01:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id ED42E808598F; Wed, 6 Dec 2023 03:00:23 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378066AbjLFK74 (ORCPT + 99 others); Wed, 6 Dec 2023 05:59:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378020AbjLFK7d (ORCPT ); Wed, 6 Dec 2023 05:59:33 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F125B10E0; Wed, 6 Dec 2023 02:59:07 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 7D64124E31D; Wed, 6 Dec 2023 18:58:54 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:54 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:53 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 14/21] PCI: microchip: Add get_events() callback function Date: Wed, 6 Dec 2023 18:58:32 +0800 Message-ID: <20231206105839.25805-15-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:00:24 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530083672026190 X-GMAIL-MSGID: 1784530083672026190 PolarFire implements its own PCIe interrupts, additional to the regular PCIe interrupts, due to lack of an MSI controller, so the interrupt to event number mapping is different to the PLDA local interrupts, necessitating a custom get_events() implementation. plda_handle_events() will call the get_events() callback function pointer directly. For the robustness of codes, add checking in plda_init_interrupts(). Signed-off-by: Minda Chen Acked-by: Conor Dooley --- drivers/pci/controller/plda/pcie-microchip-host.c | 14 +++++++++++++- drivers/pci/controller/plda/pcie-plda.h | 8 ++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 2c03b0354f15..f5e7da242aec 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -657,7 +657,7 @@ static void plda_handle_event(struct irq_desc *desc) chained_irq_enter(chip, desc); - events = mc_get_events(port); + events = port->event_ops->get_events(port); for_each_set_bit(bit, &events, port->num_events) generic_handle_domain_irq(port->event_domain, bit); @@ -816,7 +816,12 @@ static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, 0, event_cause[event].sym, plda); } +static const struct plda_event_ops mc_event_ops = { + .get_events = mc_get_events, +}; + static const struct plda_event mc_event = { + .event_ops = &mc_event_ops, .request_event_irq = mc_request_event_irq, .intx_event = EVENT_LOCAL_PM_MSI_INT_INTX, .msi_event = EVENT_LOCAL_PM_MSI_INT_MSI, @@ -931,6 +936,11 @@ static int plda_init_interrupts(struct platform_device *pdev, int i, intx_irq, msi_irq, event_irq; int ret; + if (!event->event_ops || !event->event_ops->get_events) { + dev_err(dev, "no get events ops\n"); + return -EINVAL; + } + ret = plda_pcie_init_irq_domains(port); if (ret) { dev_err(dev, "failed creating IRQ domains\n"); @@ -941,6 +951,8 @@ static int plda_init_interrupts(struct platform_device *pdev, if (irq < 0) return -ENODEV; + port->event_ops = event->event_ops; + for (i = 0; i < port->num_events; i++) { event_irq = irq_create_mapping(port->event_domain, i); if (!event_irq) { diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index fba7343f9a96..df1729095952 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -102,6 +102,12 @@ #define EVENT_PM_MSI_INT_SYS_ERR 12 #define NUM_PLDA_EVENTS 13 +struct plda_pcie_rp; + +struct plda_event_ops { + u32 (*get_events)(struct plda_pcie_rp *pcie); +}; + struct plda_msi { struct mutex lock; /* Protect used bitmap */ struct irq_domain *msi_domain; @@ -117,11 +123,13 @@ struct plda_pcie_rp { struct irq_domain *event_domain; raw_spinlock_t lock; struct plda_msi msi; + const struct plda_event_ops *event_ops; void __iomem *bridge_addr; int num_events; }; struct plda_event { + const struct plda_event_ops *event_ops; int (*request_event_irq)(struct plda_pcie_rp *pcie, int event_irq, int event); int intx_event; From patchwork Wed Dec 6 10:58:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174500 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4025108vqy; Wed, 6 Dec 2023 03:01:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IHMOARjsRfFlspgrLmgAH8E8evhKEOv11GBnk5F0Ra6Zs6huOoIm0L+8V+u3Qwr5tYjBNJL X-Received: by 2002:a05:6a21:1ca6:b0:18f:a92:9152 with SMTP id sf38-20020a056a211ca600b0018f0a929152mr390191pzb.103.1701860489697; Wed, 06 Dec 2023 03:01:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860489; cv=none; d=google.com; s=arc-20160816; b=wyvErUFLdW30i1T/1siawK5AOw6cvDsDd707XTEK7qf0fD8lOoGpqhAbLcpEF6xolz FJtevyKZuVKfw2QWDfdqzDqKiA9N7vc8KcoulzHqRwz7Aotks/OBM+ONDF50LucwjX+b l6j01GXSdPqKGllkeaIi7Sgwc+cRoFd3TFLBGOssino1dxw9LefQbwCSIK0ptIrc2Oky JJ3q6F8UenMt+v/wI5OTXAdHa+EdZDiyMxiw8QI5rTiWZwUReYOFOnW4T0uNlDJ9KEu4 AwRn/t8o32jAv/mt8cNMEw+dd403TOu7AVYn4LaBmkjX/8fJAWnHRZxZ8qSwoOmQSWk5 asIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=7n0b4yZXTfGBRpewvqDIaz6B16WuBeaaREbUx1bHStU=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=BmTYpA3ZwOAUf8zsZ8z5vEgj9UI+fzekRXFDStepSPdEJWRj7AIkF1C6dNdSOtEUu1 cWd0702EzZATHTjWn7RgVCrDdX9z+YP8qRXxRlci9Ovb04AYBKZuMQytDaUsYCG4+c3y PMLUJflUK8CXH6veA3rqzR/LqOuqDcFj/oPBwyj5q3QWhCNB3cd1aMVEZgzLCLxT4peA +rmlSFsKgz2fN742Ci4hrpuQAsMII5Tr3lEi1sfUy3PCiCcanUhO0VxWf9fqDyjG4TIv tVXaCJQ1cpNDb18kwF89Lf7hPdk6Je8Kcl3a6QNKlY9TWxutm93AyTmPfgn4mkBdI9pQ ggsQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id bq10-20020a056a02044a00b005bdfd3a26a0si5842506pgb.584.2023.12.06.03.01.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:01:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 6D771809C39F; Wed, 6 Dec 2023 03:00:38 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378125AbjLFLAV (ORCPT + 99 others); Wed, 6 Dec 2023 06:00:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378030AbjLFK7f (ORCPT ); Wed, 6 Dec 2023 05:59:35 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7AEED59; Wed, 6 Dec 2023 02:59:10 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 5294F80E1; Wed, 6 Dec 2023 18:58:55 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:55 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:54 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 15/21] PCI: microchip: Add event IRQ domain ops to struct plda_event Date: Wed, 6 Dec 2023 18:58:33 +0800 Message-ID: <20231206105839.25805-16-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:00:38 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530064341767318 X-GMAIL-MSGID: 1784530064341767318 For lack of an MSI controller, The new added PCIe interrupts have to be added to global interrupt event field. PolarFire event domain ops can not be re-used. PLDA event domain ops instances will be implemented in later patch. Signed-off-by: Minda Chen Acked-by: Conor Dooley --- drivers/pci/controller/plda/pcie-microchip-host.c | 6 ++++-- drivers/pci/controller/plda/pcie-plda.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index f5e7da242aec..e6dcc572b65b 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -821,13 +821,15 @@ static const struct plda_event_ops mc_event_ops = { }; static const struct plda_event mc_event = { + .domain_ops = &mc_event_domain_ops, .event_ops = &mc_event_ops, .request_event_irq = mc_request_event_irq, .intx_event = EVENT_LOCAL_PM_MSI_INT_INTX, .msi_event = EVENT_LOCAL_PM_MSI_INT_MSI, }; -static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) +static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port, + const struct irq_domain_ops *ops) { struct device *dev = port->dev; struct device_node *node = dev->of_node; @@ -941,7 +943,7 @@ static int plda_init_interrupts(struct platform_device *pdev, return -EINVAL; } - ret = plda_pcie_init_irq_domains(port); + ret = plda_pcie_init_irq_domains(port, event->domain_ops); if (ret) { dev_err(dev, "failed creating IRQ domains\n"); return ret; diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index df1729095952..820ea16855b5 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -129,6 +129,7 @@ struct plda_pcie_rp { }; struct plda_event { + const struct irq_domain_ops *domain_ops; const struct plda_event_ops *event_ops; int (*request_event_irq)(struct plda_pcie_rp *pcie, int event_irq, int event); From patchwork Wed Dec 6 10:58:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174501 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4025110vqy; Wed, 6 Dec 2023 03:01:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IE15RQkYuXdYOXhXqqRaJPn9DafV4xda7PRy+mxulm8eyqmGSjreIYmbqTi+sm1gnFRKEIj X-Received: by 2002:a05:6a20:7b16:b0:18f:97c:9787 with SMTP id s22-20020a056a207b1600b0018f097c9787mr624760pzh.111.1701860493999; Wed, 06 Dec 2023 03:01:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860493; cv=none; d=google.com; s=arc-20160816; b=NMjG+CZFDIB+wuBT0BEZ4H1neulDSPOevE4+OwatbVKA9gdHJ3rlHdIruOCAUUFDpo aY8nkXtXyc0gAIjP5kNq2PaYWWyXddb+h+T99AQS/wbGZy2g8AHTUlkqWwyorzFZHSmx n1xLv0z0JxuOYHLByS5nDsH6XKhqFzSenFmkY4Ta5A76xp86ZRknI6ss+NmDSNzHDgIR qYUw1uJPi+7JMO1obaydjaJCMCEGJF95HVzDYBtjCoO03OfBsUblmMlgyMYpkILLgn5v T2g4G6vFbHLKJ6WZZf7gp7gld5WAXCUhZy6lRvl9RweFYqc5MVzBHJmeWpYpBOCnJfTN xa/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=MOPptIXYdyUCyLz0tN/9lSd5ph3RVSZxEzOImqOD1G8=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=I9V59uPTvP1jxywNjpoeDQbErxKZ0n+0eZ908ui8qKcI3VQ5LMdSDhawODgR54F2Aa WJz4gTP3EgaRlfmyIRYyJb/JxC55iImK8+pp1dvqII7bFa1m9qXmdx3WZylSrEHWnxhF 8YfMUJC78OAE5/rdApsu5ut/r/EesQXl3Hznn7xrpXvWgZ5LLBKKJDdEIMy+AfeLHJ6i CcYXGTHkhO4Hpk+ttl9I5Mv/Xyz25pcA0bye4WwC6OoCTQRnF4MWOtUkfAml5XI2eb/M m+N1FxZ2YdO9TF9/3y68UrQXuJNll4bvdHgUPfqusLLm8R/QKFiHZgspBMeMx94vL1NX lktw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id fb12-20020a056a002d8c00b006cddc343ceesi1851139pfb.181.2023.12.06.03.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:01:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id B029080DE983; Wed, 6 Dec 2023 03:01:10 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378151AbjLFLAj (ORCPT + 99 others); Wed, 6 Dec 2023 06:00:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378037AbjLFK7f (ORCPT ); Wed, 6 Dec 2023 05:59:35 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0228610E3; Wed, 6 Dec 2023 02:59:07 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id D2B5124E31F; Wed, 6 Dec 2023 18:58:56 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:56 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:55 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 16/21] PCI: microchip: Move IRQ functions to pcie-plda-host.c Date: Wed, 6 Dec 2023 18:58:34 +0800 Message-ID: <20231206105839.25805-17-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:01:11 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530069708842057 X-GMAIL-MSGID: 1784530069708842057 Move IRQ related functions to pcie-plda-host.c for re-use these codes. Now Refactoring codes complete. Including MSI, INTx, event interrupts and IRQ init functions. Signed-off-by: Minda Chen Acked-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 372 ----------------- drivers/pci/controller/plda/pcie-plda-host.c | 373 ++++++++++++++++++ drivers/pci/controller/plda/pcie-plda.h | 3 + 3 files changed, 376 insertions(+), 372 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index e6dcc572b65b..6995461daec7 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -318,245 +318,6 @@ static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI); } -static void plda_handle_msi(struct irq_desc *desc) -{ - struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - struct device *dev = port->dev; - struct plda_msi *msi = &port->msi; - void __iomem *bridge_base_addr = port->bridge_addr; - unsigned long status; - u32 bit; - int ret; - - chained_irq_enter(chip, desc); - - status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); - if (status & PM_MSI_INT_MSI_MASK) { - writel_relaxed(status & PM_MSI_INT_MSI_MASK, - bridge_base_addr + ISTATUS_LOCAL); - status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); - for_each_set_bit(bit, &status, msi->num_vectors) { - ret = generic_handle_domain_irq(msi->dev_domain, bit); - if (ret) - dev_err_ratelimited(dev, "bad MSI IRQ %d\n", - bit); - } - } - - chained_irq_exit(chip, desc); -} - -static void plda_msi_bottom_irq_ack(struct irq_data *data) -{ - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; - u32 bitpos = data->hwirq; - - writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); -} - -static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) -{ - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - phys_addr_t addr = port->msi.vector_phy; - - msg->address_lo = lower_32_bits(addr); - msg->address_hi = upper_32_bits(addr); - msg->data = data->hwirq; - - dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n", - (int)data->hwirq, msg->address_hi, msg->address_lo); -} - -static int plda_msi_set_affinity(struct irq_data *irq_data, - const struct cpumask *mask, bool force) -{ - return -EINVAL; -} - -static struct irq_chip plda_msi_bottom_irq_chip = { - .name = "PLDA MSI", - .irq_ack = plda_msi_bottom_irq_ack, - .irq_compose_msi_msg = plda_compose_msi_msg, - .irq_set_affinity = plda_msi_set_affinity, -}; - -static int plda_irq_msi_domain_alloc(struct irq_domain *domain, - unsigned int virq, - unsigned int nr_irqs, - void *args) -{ - struct plda_pcie_rp *port = domain->host_data; - struct plda_msi *msi = &port->msi; - unsigned long bit; - - mutex_lock(&msi->lock); - bit = find_first_zero_bit(msi->used, msi->num_vectors); - if (bit >= msi->num_vectors) { - mutex_unlock(&msi->lock); - return -ENOSPC; - } - - set_bit(bit, msi->used); - - irq_domain_set_info(domain, virq, bit, &plda_msi_bottom_irq_chip, - domain->host_data, handle_edge_irq, NULL, NULL); - - mutex_unlock(&msi->lock); - - return 0; -} - -static void plda_irq_msi_domain_free(struct irq_domain *domain, - unsigned int virq, - unsigned int nr_irqs) -{ - struct irq_data *d = irq_domain_get_irq_data(domain, virq); - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); - struct plda_msi *msi = &port->msi; - - mutex_lock(&msi->lock); - - if (test_bit(d->hwirq, msi->used)) - __clear_bit(d->hwirq, msi->used); - else - dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq); - - mutex_unlock(&msi->lock); -} - -static const struct irq_domain_ops msi_domain_ops = { - .alloc = plda_irq_msi_domain_alloc, - .free = plda_irq_msi_domain_free, -}; - -static struct irq_chip plda_msi_irq_chip = { - .name = "PLDA PCIe MSI", - .irq_ack = irq_chip_ack_parent, - .irq_mask = pci_msi_mask_irq, - .irq_unmask = pci_msi_unmask_irq, -}; - -static struct msi_domain_info plda_msi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_PCI_MSIX), - .chip = &plda_msi_irq_chip, -}; - -static int plda_allocate_msi_domains(struct plda_pcie_rp *port) -{ - struct device *dev = port->dev; - struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); - struct plda_msi *msi = &port->msi; - - mutex_init(&port->msi.lock); - - msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors, - &msi_domain_ops, port); - if (!msi->dev_domain) { - dev_err(dev, "failed to create IRQ domain\n"); - return -ENOMEM; - } - - msi->msi_domain = pci_msi_create_irq_domain(fwnode, - &plda_msi_domain_info, - msi->dev_domain); - if (!msi->msi_domain) { - dev_err(dev, "failed to create MSI domain\n"); - irq_domain_remove(msi->dev_domain); - return -ENOMEM; - } - - return 0; -} - -static void plda_handle_intx(struct irq_desc *desc) -{ - struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - struct device *dev = port->dev; - void __iomem *bridge_base_addr = port->bridge_addr; - unsigned long status; - u32 bit; - int ret; - - chained_irq_enter(chip, desc); - - status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); - if (status & PM_MSI_INT_INTX_MASK) { - status &= PM_MSI_INT_INTX_MASK; - status >>= PM_MSI_INT_INTX_SHIFT; - for_each_set_bit(bit, &status, PCI_NUM_INTX) { - ret = generic_handle_domain_irq(port->intx_domain, bit); - if (ret) - dev_err_ratelimited(dev, "bad INTx IRQ %d\n", - bit); - } - } - - chained_irq_exit(chip, desc); -} - -static void plda_ack_intx_irq(struct irq_data *data) -{ - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; - u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); - - writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); -} - -static void plda_mask_intx_irq(struct irq_data *data) -{ - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; - unsigned long flags; - u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); - u32 val; - - raw_spin_lock_irqsave(&port->lock, flags); - val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); - val &= ~mask; - writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); - raw_spin_unlock_irqrestore(&port->lock, flags); -} - -static void plda_unmask_intx_irq(struct irq_data *data) -{ - struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = port->bridge_addr; - unsigned long flags; - u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); - u32 val; - - raw_spin_lock_irqsave(&port->lock, flags); - val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); - val |= mask; - writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); - raw_spin_unlock_irqrestore(&port->lock, flags); -} - -static struct irq_chip plda_intx_irq_chip = { - .name = "PLDA PCIe INTx", - .irq_ack = plda_ack_intx_irq, - .irq_mask = plda_mask_intx_irq, - .irq_unmask = plda_unmask_intx_irq, -}; - -static int plda_pcie_intx_map(struct irq_domain *domain, unsigned int irq, - irq_hw_number_t hwirq) -{ - irq_set_chip_and_handler(irq, &plda_intx_irq_chip, handle_level_irq); - irq_set_chip_data(irq, domain->host_data); - - return 0; -} - -static const struct irq_domain_ops intx_domain_ops = { - .map = plda_pcie_intx_map, -}; - static inline u32 reg_to_event(u32 reg, struct event_map field) { return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; @@ -643,28 +404,6 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static irqreturn_t plda_event_handler(int irq, void *dev_id) -{ - return IRQ_HANDLED; -} - -static void plda_handle_event(struct irq_desc *desc) -{ - struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); - unsigned long events; - u32 bit; - struct irq_chip *chip = irq_desc_get_chip(desc); - - chained_irq_enter(chip, desc); - - events = port->event_ops->get_events(port); - - for_each_set_bit(bit, &events, port->num_events) - generic_handle_domain_irq(port->event_domain, bit); - - chained_irq_exit(chip, desc); -} - static void mc_ack_event_irq(struct irq_data *data) { struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); @@ -828,47 +567,6 @@ static const struct plda_event mc_event = { .msi_event = EVENT_LOCAL_PM_MSI_INT_MSI, }; -static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port, - const struct irq_domain_ops *ops) -{ - struct device *dev = port->dev; - struct device_node *node = dev->of_node; - struct device_node *pcie_intc_node; - - /* Setup INTx */ - pcie_intc_node = of_get_next_child(node, NULL); - if (!pcie_intc_node) { - dev_err(dev, "failed to find PCIe Intc node\n"); - return -EINVAL; - } - - port->event_domain = irq_domain_add_linear(pcie_intc_node, - port->num_events, - &mc_event_domain_ops, port); - if (!port->event_domain) { - dev_err(dev, "failed to get event domain\n"); - of_node_put(pcie_intc_node); - return -ENOMEM; - } - - irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS); - - port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, - &intx_domain_ops, port); - if (!port->intx_domain) { - dev_err(dev, "failed to get an INTx IRQ domain\n"); - of_node_put(pcie_intc_node); - return -ENOMEM; - } - - irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); - - of_node_put(pcie_intc_node); - raw_spin_lock_init(&port->lock); - - return plda_allocate_msi_domains(port); -} - static inline void mc_clear_secs(struct mc_pcie *port) { void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; @@ -929,76 +627,6 @@ static void mc_disable_interrupts(struct mc_pcie *port) writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); } -static int plda_init_interrupts(struct platform_device *pdev, - struct plda_pcie_rp *port, - const struct plda_event *event) -{ - struct device *dev = &pdev->dev; - int irq; - int i, intx_irq, msi_irq, event_irq; - int ret; - - if (!event->event_ops || !event->event_ops->get_events) { - dev_err(dev, "no get events ops\n"); - return -EINVAL; - } - - ret = plda_pcie_init_irq_domains(port, event->domain_ops); - if (ret) { - dev_err(dev, "failed creating IRQ domains\n"); - return ret; - } - - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return -ENODEV; - - port->event_ops = event->event_ops; - - for (i = 0; i < port->num_events; i++) { - event_irq = irq_create_mapping(port->event_domain, i); - if (!event_irq) { - dev_err(dev, "failed to map hwirq %d\n", i); - return -ENXIO; - } - - if (event->request_event_irq) - ret = event->request_event_irq(port, event_irq, i); - else - ret = devm_request_irq(dev, event_irq, - plda_event_handler, - 0, NULL, port); - - if (ret) { - dev_err(dev, "failed to request IRQ %d\n", event_irq); - return ret; - } - } - - intx_irq = irq_create_mapping(port->event_domain, - event->intx_event); - if (!intx_irq) { - dev_err(dev, "failed to map INTx interrupt\n"); - return -ENXIO; - } - - /* Plug the INTx chained handler */ - irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); - - msi_irq = irq_create_mapping(port->event_domain, - event->msi_event); - if (!msi_irq) - return -ENXIO; - - /* Plug the MSI chained handler */ - irq_set_chained_handler_and_data(msi_irq, plda_handle_msi, port); - - /* Plug the main event chained handler */ - irq_set_chained_handler_and_data(irq, plda_handle_event, port); - - return 0; -} - static int mc_platform_init(struct pci_config_window *cfg) { struct device *dev = cfg->parent; diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c index 19131181897f..e155d1d78627 100644 --- a/drivers/pci/controller/plda/pcie-plda-host.c +++ b/drivers/pci/controller/plda/pcie-plda-host.c @@ -18,6 +18,379 @@ #include "pcie-plda.h" +static void plda_handle_msi(struct irq_desc *desc) +{ + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct device *dev = port->dev; + struct plda_msi *msi = &port->msi; + void __iomem *bridge_base_addr = port->bridge_addr; + unsigned long status; + u32 bit; + int ret; + + chained_irq_enter(chip, desc); + + status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); + if (status & PM_MSI_INT_MSI_MASK) { + writel_relaxed(status & PM_MSI_INT_MSI_MASK, + bridge_base_addr + ISTATUS_LOCAL); + status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); + for_each_set_bit(bit, &status, msi->num_vectors) { + ret = generic_handle_domain_irq(msi->dev_domain, bit); + if (ret) + dev_err_ratelimited(dev, "bad MSI IRQ %d\n", + bit); + } + } + + chained_irq_exit(chip, desc); +} + +static void plda_msi_bottom_irq_ack(struct irq_data *data) +{ + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; + u32 bitpos = data->hwirq; + + writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); +} + +static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + phys_addr_t addr = port->msi.vector_phy; + + msg->address_lo = lower_32_bits(addr); + msg->address_hi = upper_32_bits(addr); + msg->data = data->hwirq; + + dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n", + (int)data->hwirq, msg->address_hi, msg->address_lo); +} + +static int plda_msi_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static struct irq_chip plda_msi_bottom_irq_chip = { + .name = "PLDA MSI", + .irq_ack = plda_msi_bottom_irq_ack, + .irq_compose_msi_msg = plda_compose_msi_msg, + .irq_set_affinity = plda_msi_set_affinity, +}; + +static int plda_irq_msi_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, + void *args) +{ + struct plda_pcie_rp *port = domain->host_data; + struct plda_msi *msi = &port->msi; + unsigned long bit; + + mutex_lock(&msi->lock); + bit = find_first_zero_bit(msi->used, msi->num_vectors); + if (bit >= msi->num_vectors) { + mutex_unlock(&msi->lock); + return -ENOSPC; + } + + set_bit(bit, msi->used); + + irq_domain_set_info(domain, virq, bit, &plda_msi_bottom_irq_chip, + domain->host_data, handle_edge_irq, NULL, NULL); + + mutex_unlock(&msi->lock); + + return 0; +} + +static void plda_irq_msi_domain_free(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); + struct plda_msi *msi = &port->msi; + + mutex_lock(&msi->lock); + + if (test_bit(d->hwirq, msi->used)) + __clear_bit(d->hwirq, msi->used); + else + dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq); + + mutex_unlock(&msi->lock); +} + +static const struct irq_domain_ops msi_domain_ops = { + .alloc = plda_irq_msi_domain_alloc, + .free = plda_irq_msi_domain_free, +}; + +static struct irq_chip plda_msi_irq_chip = { + .name = "PLDA PCIe MSI", + .irq_ack = irq_chip_ack_parent, + .irq_mask = pci_msi_mask_irq, + .irq_unmask = pci_msi_unmask_irq, +}; + +static struct msi_domain_info plda_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX), + .chip = &plda_msi_irq_chip, +}; + +static int plda_allocate_msi_domains(struct plda_pcie_rp *port) +{ + struct device *dev = port->dev; + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); + struct plda_msi *msi = &port->msi; + + mutex_init(&port->msi.lock); + + msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors, + &msi_domain_ops, port); + if (!msi->dev_domain) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } + + msi->msi_domain = pci_msi_create_irq_domain(fwnode, + &plda_msi_domain_info, + msi->dev_domain); + if (!msi->msi_domain) { + dev_err(dev, "failed to create MSI domain\n"); + irq_domain_remove(msi->dev_domain); + return -ENOMEM; + } + + return 0; +} + +static void plda_handle_intx(struct irq_desc *desc) +{ + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct device *dev = port->dev; + void __iomem *bridge_base_addr = port->bridge_addr; + unsigned long status; + u32 bit; + int ret; + + chained_irq_enter(chip, desc); + + status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); + if (status & PM_MSI_INT_INTX_MASK) { + status &= PM_MSI_INT_INTX_MASK; + status >>= PM_MSI_INT_INTX_SHIFT; + for_each_set_bit(bit, &status, PCI_NUM_INTX) { + ret = generic_handle_domain_irq(port->intx_domain, bit); + if (ret) + dev_err_ratelimited(dev, "bad INTx IRQ %d\n", + bit); + } + } + + chained_irq_exit(chip, desc); +} + +static void plda_ack_intx_irq(struct irq_data *data) +{ + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; + u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); + + writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); +} + +static void plda_mask_intx_irq(struct irq_data *data) +{ + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; + unsigned long flags; + u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); + u32 val; + + raw_spin_lock_irqsave(&port->lock, flags); + val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); + val &= ~mask; + writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); + raw_spin_unlock_irqrestore(&port->lock, flags); +} + +static void plda_unmask_intx_irq(struct irq_data *data) +{ + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; + unsigned long flags; + u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); + u32 val; + + raw_spin_lock_irqsave(&port->lock, flags); + val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); + val |= mask; + writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); + raw_spin_unlock_irqrestore(&port->lock, flags); +} + +static struct irq_chip plda_intx_irq_chip = { + .name = "PLDA PCIe INTx", + .irq_ack = plda_ack_intx_irq, + .irq_mask = plda_mask_intx_irq, + .irq_unmask = plda_unmask_intx_irq, +}; + +static int plda_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &plda_intx_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops intx_domain_ops = { + .map = plda_pcie_intx_map, +}; + +static irqreturn_t plda_event_handler(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static void plda_handle_event(struct irq_desc *desc) +{ + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); + unsigned long events; + u32 bit; + struct irq_chip *chip = irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + + events = port->event_ops->get_events(port); + + for_each_set_bit(bit, &events, port->num_events) + generic_handle_domain_irq(port->event_domain, bit); + + chained_irq_exit(chip, desc); +} + +static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port, + const struct irq_domain_ops *ops) +{ + struct device *dev = port->dev; + struct device_node *node = dev->of_node; + struct device_node *pcie_intc_node; + + /* Setup INTx */ + pcie_intc_node = of_get_next_child(node, NULL); + if (!pcie_intc_node) { + dev_err(dev, "failed to find PCIe Intc node\n"); + return -EINVAL; + } + + port->event_domain = irq_domain_add_linear(pcie_intc_node, + port->num_events, + ops, port); + if (!port->event_domain) { + dev_err(dev, "failed to get event domain\n"); + of_node_put(pcie_intc_node); + return -ENOMEM; + } + + irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS); + + port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, + &intx_domain_ops, port); + if (!port->intx_domain) { + dev_err(dev, "failed to get an INTx IRQ domain\n"); + of_node_put(pcie_intc_node); + return -ENOMEM; + } + + irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); + + of_node_put(pcie_intc_node); + raw_spin_lock_init(&port->lock); + + return plda_allocate_msi_domains(port); +} + +int plda_init_interrupts(struct platform_device *pdev, + struct plda_pcie_rp *port, + const struct plda_event *event) +{ + struct device *dev = &pdev->dev; + int irq; + int i, intx_irq, msi_irq, event_irq; + int ret; + + if (!event->event_ops || !event->event_ops->get_events) { + dev_err(dev, "no get events ops\n"); + return -EINVAL; + } + + ret = plda_pcie_init_irq_domains(port, event->domain_ops); + if (ret) { + dev_err(dev, "failed creating IRQ domains\n"); + return ret; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return -ENODEV; + + port->event_ops = event->event_ops; + + for (i = 0; i < port->num_events; i++) { + event_irq = irq_create_mapping(port->event_domain, i); + if (!event_irq) { + dev_err(dev, "failed to map hwirq %d\n", i); + return -ENXIO; + } + + if (event->request_event_irq) + ret = event->request_event_irq(port, event_irq, i); + else + ret = devm_request_irq(dev, event_irq, + plda_event_handler, + 0, NULL, port); + + if (ret) { + dev_err(dev, "failed to request IRQ %d\n", event_irq); + return ret; + } + } + + intx_irq = irq_create_mapping(port->event_domain, + event->intx_event); + if (!intx_irq) { + dev_err(dev, "failed to map INTx interrupt\n"); + return -ENXIO; + } + + /* Plug the INTx chained handler */ + irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); + + msi_irq = irq_create_mapping(port->event_domain, + event->msi_event); + if (!msi_irq) + return -ENXIO; + + /* Plug the MSI chained handler */ + irq_set_chained_handler_and_data(msi_irq, plda_handle_msi, port); + + /* Plug the main event chained handler */ + irq_set_chained_handler_and_data(irq, plda_handle_event, port); + + return 0; +} +EXPORT_SYMBOL_GPL(plda_init_interrupts); + void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, size_t size) diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index 820ea16855b5..ce7787aef4b7 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -137,6 +137,9 @@ struct plda_event { int msi_event; }; +int plda_init_interrupts(struct platform_device *pdev, + struct plda_pcie_rp *port, + const struct plda_event *event); void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, size_t size); 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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id t15-20020a170902e84f00b001d1d5b478dcsi397201plg.96.2023.12.06.03.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:00:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id DD0C0802AF10; Wed, 6 Dec 2023 03:00:36 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378118AbjLFLAS (ORCPT + 99 others); Wed, 6 Dec 2023 06:00:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378028AbjLFK7f (ORCPT ); Wed, 6 Dec 2023 05:59:35 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 601D010E7; Wed, 6 Dec 2023 02:59:08 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 0703424E31E; Wed, 6 Dec 2023 18:58:58 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:58 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:55 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 17/21] PCI: plda: Add event interrupt codes and host init/deinit functions Date: Wed, 6 Dec 2023 18:58:35 +0800 Message-ID: <20231206105839.25805-18-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:00:37 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530020495921338 X-GMAIL-MSGID: 1784530020495921338 PLDA implements global IRQ domain ops like Microchip's codes. Also add a struct plda_event instance to init PCIe interrupt. plda_get_events() adds interrupt register to PLDA local event num mapping codes except DMA engine interrupt events. The DMA engine interrupt events are implemented by vendors. Add PLDA host init/deinit functions and map bus function. So vendor can use it to init PLDA PCIe host core. Signed-off-by: Minda Chen Reviewed-by: Mason Huo --- drivers/pci/controller/plda/pcie-plda-host.c | 230 +++++++++++++++++-- drivers/pci/controller/plda/pcie-plda.h | 49 ++++ 2 files changed, 266 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c index e155d1d78627..10ad26216505 100644 --- a/drivers/pci/controller/plda/pcie-plda-host.c +++ b/drivers/pci/controller/plda/pcie-plda-host.c @@ -3,6 +3,7 @@ * PLDA PCIe XpressRich host controller driver * * Copyright (C) 2023 Microchip Co. Ltd + * StarFive Co. Ltd * * Author: Daire McNamara */ @@ -18,6 +19,15 @@ #include "pcie-plda.h" +void __iomem *plda_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) +{ + struct plda_pcie_rp *pcie = bus->sysdata; + + return pcie->config_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); +} +EXPORT_SYMBOL_GPL(plda_pcie_map_bus); + static void plda_handle_msi(struct irq_desc *desc) { struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); @@ -262,6 +272,107 @@ static irqreturn_t plda_event_handler(int irq, void *dev_id) return IRQ_HANDLED; } +static u32 plda_get_events(struct plda_pcie_rp *port) +{ + u32 events, val, origin; + + origin = readl_relaxed(port->bridge_addr + ISTATUS_LOCAL); + + /* Error events and doorbell events */ + events = (origin & ERROR_AND_DOORBELL_MASK) >> A_ATR_EVT_POST_ERR_SHIFT; + + /* INTx events */ + if (origin & PM_MSI_INT_INTX_MASK) + events |= BIT(EVENT_PM_MSI_INT_INTX); + + /* MSI event and sys events */ + val = (origin & SYS_AND_MSI_MASK) >> PM_MSI_INT_MSI_SHIFT; + events |= val << EVENT_PM_MSI_INT_MSI; + + return events; +} + +static u32 plda_hwirq_to_mask(int hwirq) +{ + u32 mask; + + if (hwirq < EVENT_PM_MSI_INT_INTX) + mask = BIT(hwirq + A_ATR_EVT_POST_ERR_SHIFT); + else if (hwirq == EVENT_PM_MSI_INT_INTX) + mask = PM_MSI_INT_INTX_MASK; + else + mask = BIT(hwirq + PM_MSI_TO_MASK_OFFSET); + + return mask; +} + +static void plda_ack_event_irq(struct irq_data *data) +{ + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + + writel_relaxed(plda_hwirq_to_mask(data->hwirq), + port->bridge_addr + ISTATUS_LOCAL); +} + +static void plda_mask_event_irq(struct irq_data *data) +{ + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + u32 mask, val; + + mask = plda_hwirq_to_mask(data->hwirq); + + raw_spin_lock(&port->lock); + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); + val &= ~mask; + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); + raw_spin_unlock(&port->lock); +} + +static void plda_unmask_event_irq(struct irq_data *data) +{ + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + u32 mask, val; + + mask = plda_hwirq_to_mask(data->hwirq); + + raw_spin_lock(&port->lock); + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); + val |= mask; + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); + raw_spin_unlock(&port->lock); +} + +static struct irq_chip plda_event_irq_chip = { + .name = "PLDA PCIe EVENT", + .irq_ack = plda_ack_event_irq, + .irq_mask = plda_mask_event_irq, + .irq_unmask = plda_unmask_event_irq, +}; + +static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &plda_event_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops plda_evt_dom_ops = { + .map = plda_pcie_event_map, +}; + +static const struct plda_event_ops plda_event_ops = { + .get_events = plda_get_events, +}; + +static const struct plda_event plda_default_event = { + .domain_ops = &plda_evt_dom_ops, + .event_ops = &plda_event_ops, + .intx_event = EVENT_PM_MSI_INT_INTX, + .msi_event = EVENT_PM_MSI_INT_MSI +}; + static void plda_handle_event(struct irq_desc *desc) { struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); @@ -325,8 +436,7 @@ int plda_init_interrupts(struct platform_device *pdev, const struct plda_event *event) { struct device *dev = &pdev->dev; - int irq; - int i, intx_irq, msi_irq, event_irq; + int i, event_irq; int ret; if (!event->event_ops || !event->event_ops->get_events) { @@ -340,8 +450,8 @@ int plda_init_interrupts(struct platform_device *pdev, return ret; } - irq = platform_get_irq(pdev, 0); - if (irq < 0) + port->irq = platform_get_irq(pdev, 0); + if (port->irq < 0) return -ENODEV; port->event_ops = event->event_ops; @@ -366,26 +476,26 @@ int plda_init_interrupts(struct platform_device *pdev, } } - intx_irq = irq_create_mapping(port->event_domain, - event->intx_event); - if (!intx_irq) { + port->intx_irq = irq_create_mapping(port->event_domain, + event->intx_event); + if (!port->intx_irq) { dev_err(dev, "failed to map INTx interrupt\n"); return -ENXIO; } /* Plug the INTx chained handler */ - irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); + irq_set_chained_handler_and_data(port->intx_irq, plda_handle_intx, port); - msi_irq = irq_create_mapping(port->event_domain, - event->msi_event); - if (!msi_irq) + port->msi_irq = irq_create_mapping(port->event_domain, + event->msi_event); + if (!port->msi_irq) return -ENXIO; /* Plug the MSI chained handler */ - irq_set_chained_handler_and_data(msi_irq, plda_handle_msi, port); + irq_set_chained_handler_and_data(port->msi_irq, plda_handle_msi, port); /* Plug the main event chained handler */ - irq_set_chained_handler_and_data(irq, plda_handle_event, port); + irq_set_chained_handler_and_data(port->irq, plda_handle_event, port); return 0; } @@ -451,3 +561,97 @@ int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, return 0; } EXPORT_SYMBOL_GPL(plda_pcie_setup_iomems); + +static void plda_pcie_irq_domain_deinit(struct plda_pcie_rp *pcie) +{ + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); + irq_set_chained_handler_and_data(pcie->msi_irq, NULL, NULL); + irq_set_chained_handler_and_data(pcie->intx_irq, NULL, NULL); + + irq_domain_remove(pcie->msi.msi_domain); + irq_domain_remove(pcie->msi.dev_domain); + + irq_domain_remove(pcie->intx_domain); + irq_domain_remove(pcie->event_domain); +} + +int plda_pcie_host_init(struct plda_pcie_rp *port, struct pci_ops *ops) +{ + struct device *dev = port->dev; + struct pci_host_bridge *bridge; + struct platform_device *pdev = to_platform_device(dev); + struct resource *cfg_res; + int ret; + + pdev = to_platform_device(dev); + + port->bridge_addr = + devm_platform_ioremap_resource_byname(pdev, "apb"); + + if (IS_ERR(port->bridge_addr)) + return dev_err_probe(dev, PTR_ERR(port->bridge_addr), + "failed to map reg memory\n"); + + cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + if (!cfg_res) + return dev_err_probe(dev, -ENODEV, + "failed to get config memory\n"); + + port->config_base = devm_ioremap_resource(dev, cfg_res); + if (IS_ERR(port->config_base)) + return dev_err_probe(dev, PTR_ERR(port->config_base), + "failed to map config memory\n"); + + bridge = devm_pci_alloc_host_bridge(dev, 0); + if (!bridge) + return dev_err_probe(dev, -ENOMEM, + "failed to alloc bridge\n"); + + if (port->host_ops && port->host_ops->host_init) { + ret = port->host_ops->host_init(port); + if (ret) + return ret; + } + + port->bridge = bridge; + plda_pcie_setup_window(port->bridge_addr, 0, cfg_res->start, 0, + resource_size(cfg_res)); + plda_pcie_setup_iomems(bridge, port); + plda_set_default_msi(&port->msi); + ret = plda_init_interrupts(pdev, port, &plda_default_event); + if (ret) + goto err_host; + + /* Set default bus ops */ + bridge->ops = ops; + bridge->sysdata = port; + + ret = pci_host_probe(bridge); + if (ret < 0) { + dev_err_probe(dev, ret, "failed to probe pci host\n"); + goto err_probe; + } + + return ret; + +err_probe: + plda_pcie_irq_domain_deinit(port); +err_host: + if (port->host_ops && port->host_ops->host_deinit) + port->host_ops->host_deinit(port); + + return ret; +} +EXPORT_SYMBOL_GPL(plda_pcie_host_init); + +void plda_pcie_host_deinit(struct plda_pcie_rp *port) +{ + pci_stop_root_bus(port->bridge->bus); + pci_remove_root_bus(port->bridge->bus); + + plda_pcie_irq_domain_deinit(port); + + if (port->host_ops && port->host_ops->host_deinit) + port->host_ops->host_deinit(port); +} +EXPORT_SYMBOL_GPL(plda_pcie_host_deinit); diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index ce7787aef4b7..6b29bf1f5293 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -40,6 +40,7 @@ #define P_ATR_EVT_DISCARD_ERR_SHIFT 22 #define P_ATR_EVT_DOORBELL_MASK 0x00000000u #define P_ATR_EVT_DOORBELL_SHIFT 23 +#define ERROR_AND_DOORBELL_MASK GENMASK(23, 16) #define PM_MSI_INT_INTA_MASK 0x01000000u #define PM_MSI_INT_INTA_SHIFT 24 #define PM_MSI_INT_INTB_MASK 0x02000000u @@ -58,6 +59,7 @@ #define PM_MSI_INT_EVENTS_SHIFT 30 #define PM_MSI_INT_SYS_ERR_MASK 0x80000000u #define PM_MSI_INT_SYS_ERR_SHIFT 31 +#define SYS_AND_MSI_MASK GENMASK(31, 28) #define NUM_LOCAL_EVENTS 15 #define ISTATUS_LOCAL 0x184 #define IMASK_HOST 0x188 @@ -102,12 +104,43 @@ #define EVENT_PM_MSI_INT_SYS_ERR 12 #define NUM_PLDA_EVENTS 13 +/* + * PLDA local interrupt register + * + * 31 27 23 15 7 0 + * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ + * |12|11|10|9| intx |7|6|5|4|3|2|1|0| DMA error | DMA end | + * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ + * 0: AXI post error + * 1: AXI fetch error + * 2: AXI discard error + * 3: AXI doorbell + * 4: PCIe post error + * 5: PCIe fetch error + * 6: PCIe discard error + * 7: PCIe doorbell + * 8: 4 INTx interruts + * 9: MSI interrupt + * 10: AER event + * 11: PM/LTR/Hotplug + * 12: System error + * DMA error : reserved for vendor implement + * DMA end : reserved for vendor implement + */ + +#define PM_MSI_TO_MASK_OFFSET 19 + struct plda_pcie_rp; struct plda_event_ops { u32 (*get_events)(struct plda_pcie_rp *pcie); }; +struct plda_pcie_host_ops { + int (*host_init)(struct plda_pcie_rp *pcie); + void (*host_deinit)(struct plda_pcie_rp *pcie); +}; + struct plda_msi { struct mutex lock; /* Protect used bitmap */ struct irq_domain *msi_domain; @@ -119,12 +152,18 @@ struct plda_msi { struct plda_pcie_rp { struct device *dev; + struct pci_host_bridge *bridge; struct irq_domain *intx_domain; struct irq_domain *event_domain; raw_spinlock_t lock; struct plda_msi msi; const struct plda_event_ops *event_ops; + const struct plda_pcie_host_ops *host_ops; void __iomem *bridge_addr; + void __iomem *config_base; + int irq; + int msi_irq; + int intx_irq; int num_events; }; @@ -137,6 +176,8 @@ struct plda_event { int msi_event; }; +void __iomem *plda_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port, const struct plda_event *event); @@ -145,4 +186,12 @@ void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, size_t size); int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, struct plda_pcie_rp *port); +int plda_pcie_host_init(struct plda_pcie_rp *pcie, struct pci_ops *ops); +void plda_pcie_host_deinit(struct plda_pcie_rp *pcie); + +static inline void plda_set_default_msi(struct plda_msi *msi) +{ + msi->vector_phy = IMSI_ADDR; + msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS; +} #endif From patchwork Wed Dec 6 10:58:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174506 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4025434vqy; Wed, 6 Dec 2023 03:02:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IEh9aX5P5iTolz0BAC6VHKuk5ENbCmjcUyY7U8DZY+Al+aowWMYffMri4gkksrfBicnTUu0 X-Received: by 2002:a17:90b:4f43:b0:285:9ec0:892a with SMTP id pj3-20020a17090b4f4300b002859ec0892amr496321pjb.33.1701860519836; Wed, 06 Dec 2023 03:01:59 -0800 (PST) ARC-Seal: i=1; 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[23.128.96.37]) by mx.google.com with ESMTPS id e20-20020a17090ac21400b0028865a9ac22si1248641pjt.19.2023.12.06.03.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:01:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id BD1088075933; Wed, 6 Dec 2023 03:00:53 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378118AbjLFLAd (ORCPT + 99 others); Wed, 6 Dec 2023 06:00:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378035AbjLFK7f (ORCPT ); Wed, 6 Dec 2023 05:59:35 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E4CAD7F; Wed, 6 Dec 2023 02:59:11 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id DA56780E2; Wed, 6 Dec 2023 18:58:58 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:58 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:57 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 18/21] dt-bindings: PCI: Add StarFive JH7110 PCIe controller Date: Wed, 6 Dec 2023 18:58:36 +0800 Message-ID: <20231206105839.25805-19-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:00:53 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530096103472121 X-GMAIL-MSGID: 1784530096103472121 Add StarFive JH7110 SoC PCIe controller dt-bindings. JH7110 using PLDA XpressRICH PCIe host controller IP. Signed-off-by: Minda Chen Reviewed-by: Hal Feng Reviewed-by: Conor Dooley Reviewed-by: Rob Herring --- .../bindings/pci/starfive,jh7110-pcie.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml new file mode 100644 index 000000000000..67151aaa3948 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PCIe host controller + +maintainers: + - Kevin Xie + +allOf: + - $ref: plda,xpressrich3-axi-common.yaml# + +properties: + compatible: + const: starfive,jh7110-pcie + + clocks: + items: + - description: NOC bus clock + - description: Transport layer clock + - description: AXI MST0 clock + - description: APB clock + + clock-names: + items: + - const: noc + - const: tl + - const: axi_mst0 + - const: apb + + resets: + items: + - description: AXI MST0 reset + - description: AXI SLAVE0 reset + - description: AXI SLAVE reset + - description: PCIE BRIDGE reset + - description: PCIE CORE reset + - description: PCIE APB reset + + reset-names: + items: + - const: mst0 + - const: slv0 + - const: slv + - const: brg + - const: core + - const: apb + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The phandle to System Register Controller syscon node. + + perst-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + phys: + description: + Specified PHY is attached to PCIe controller. + maxItems: 1 + +required: + - clocks + - resets + - starfive,stg-syscon + +unevaluatedProperties: false + +examples: + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@940000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x9 0x40000000 0x0 0x10000000>, + <0x0 0x2b000000 0x0 0x1000000>; + reg-names = "cfg", "apb"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; + starfive,stg-syscon = <&stg_syscon>; + bus-range = <0x0 0xff>; + interrupt-parent = <&plic>; + interrupts = <56>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; + msi-controller; + clocks = <&syscrg 86>, + <&stgcrg 10>, + <&stgcrg 8>, + <&stgcrg 9>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg 11>, + <&stgcrg 12>, + <&stgcrg 13>, + <&stgcrg 14>, + <&stgcrg 15>, + <&stgcrg 16>; + perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; From patchwork Wed Dec 6 10:58:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174503 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4025223vqy; Wed, 6 Dec 2023 03:01:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IGNpm8jeOWFCJ23DFGPQL0899lA0TYoKPj5AcxZpiTi9JYQs57h+vI5WdUT2XVQTE0+aJ9G X-Received: by 2002:a17:90b:94e:b0:287:731b:cf9 with SMTP id dw14-20020a17090b094e00b00287731b0cf9mr685955pjb.34.1701860501055; Wed, 06 Dec 2023 03:01:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860501; cv=none; d=google.com; s=arc-20160816; b=Gq4VbFY128IFTeTkE0hAyAAl2V39OVY2g5Z1rDy+GEx/9SDi+qHXWIKrvBTZtwEuo+ yvHvHn3nJeHHhBeaCZxjiSENUAhjApEv3Y3H8yohK04c6WwbqkGJVt1ICR+mVkgMuaRo U1I69yL/xKaLsunpHeZLRIuMgRf6Ot95VRWDRyCTTGjtC0taQwJ6Z8W0is3KN3x24pQH wekGsamWsHbC7d55k2C4G1+9WpQQiTODkb+sk9EQSC0v2jDlfVJQj9NcXv7dE521iRWX ppPzf2lG4v3C7yKhFAz9Uc5ylSJVU/uMBqeuDSuG8PvXeiQivTXdG4G3YUUEhNpPJOLX sTMQ== ARC-Message-Signature: i=1; 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[2620:137:e000::3:1]) by mx.google.com with ESMTPS id il6-20020a17090b164600b002747da1ef66si11470489pjb.53.2023.12.06.03.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:01:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id B26EC826E3B5; Wed, 6 Dec 2023 03:01:11 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378043AbjLFLA3 (ORCPT + 99 others); Wed, 6 Dec 2023 06:00:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378039AbjLFK7f (ORCPT ); Wed, 6 Dec 2023 05:59:35 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C910D10F1; Wed, 6 Dec 2023 02:59:11 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id AFA7880ED; Wed, 6 Dec 2023 18:58:59 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:59 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:58 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 19/21] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value Date: Wed, 6 Dec 2023 18:58:37 +0800 Message-ID: <20231206105839.25805-20-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:01:14 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530077154387051 X-GMAIL-MSGID: 1784530077154387051 From: Kevin Xie Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum waiting time between exit from a conventional reset and sending the first configuration request to the device. As described in PCI base specification r6.0, section 6.6.1 , there are two different use cases of the value: - "With a Downstream Port that does not support Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms following exit from a Conventional Reset before sending a Configuration Request to the device immediately below that Port." - "With a Downstream Port that supports Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request to the device immediately below that Port." Signed-off-by: Kevin Xie Reviewed-by: Mason Huo --- drivers/pci/pci.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 5ecbcf041179..06f1f1eb878c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -22,6 +22,22 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* + * As described in PCI base specification r6.0, section 6.6.1 , there are two different use cases of the value: + * + * - "With a Downstream Port that does not support Link speeds greater + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit + * from a Conventional Reset before sending a Configuration Request to + * the device immediately below that Port." + * + * - "With a Downstream Port that supports Link speeds greater than + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training + * completes before sending a Configuration Request to the device + * immediately below that Port." + */ +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump; From patchwork Wed Dec 6 10:58:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 174502 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp4025180vqy; Wed, 6 Dec 2023 03:01:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IHiM6jMAC+1O3LBAVkHqAkf6qEYGskQnm3OUCsRrZ1SVaEMojv2wD4bmx6LiDuiLclm9P6Q X-Received: by 2002:a05:6a00:14c4:b0:6cd:f3e9:810a with SMTP id w4-20020a056a0014c400b006cdf3e9810amr813802pfu.11.1701860498001; Wed, 06 Dec 2023 03:01:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701860497; cv=none; d=google.com; s=arc-20160816; b=a4CJTANFJpTEslXUiSg9es+RtgQrXM/R1VTr63C7O1clMs/A4QkEOxpfD5YCU4qLKX B6XYx3v5BkikhBQJ9aEX0KKzPkJdxddYrPVUUfVOdc7e9NfycaINPKZgZnSxEBwbdNoU n30gDud7e4M04kTxAtp0EgqRYkARx6ck1yxCWP7UKCypkqnJdvTh8+YlCxqx5YHlrOp8 DtOoSok2TwKf3+ZvvP8uNaxw5gsMaHgWIQJCTDvz/jRDebXu4gNFHlNWfx+cCbBqDCvd Bdrmv9ZYYLLX8xwm/RurgsTPo7DIau6TGA+MNpEKwONNhUl/+Epq+5u3OYvhierfRzYc saAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=T8pNNaZWfyHxbZSLAZwmlp2tco5bZo1NVKavivQQakE=; fh=ld3UXb1S5Y4IkunPfuj6e9Ppmc+fy6ncC+eQtrVLfK8=; b=k2cX1er9OJIebi9pz7aLSIqFMBFBTdyWS8CSdES/LjUNi9j/7pbgjEVkB4pcGwFA+1 bkvvv3iRG1fgWz4cU6V7wScL/iR9PVjVZWLMB9GzeO/GY8gBPMgUNQYaSiULo370Kjpw DEhQJo+YTmnq3ymHIxmVlFSd/gUyfZwtJfRnPhYIMeUtp3QtWLJ19XFJOWJjEpS/LsS1 U/MjyF1bX1oPhj6MichaPb+xoXFv9+VSuH7XY/2xc6kljZ8j6qhVoclR5biczfNrzqSU ifcpN8hPZjVQ2jyPV3UkkYEOFYJPG8jZB6h6Yna4JQUfK/qb9wso9LEa6j3ODBEA/xjM 20yA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id a34-20020a631a62000000b005c6b4091c32si2002162pgm.385.2023.12.06.03.01.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:01:37 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 5FBB2826E3A5; Wed, 6 Dec 2023 03:01:08 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378004AbjLFLAn (ORCPT + 99 others); Wed, 6 Dec 2023 06:00:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378038AbjLFK7f (ORCPT ); Wed, 6 Dec 2023 05:59:35 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6016410E6; Wed, 6 Dec 2023 02:59:08 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 414E124E320; Wed, 6 Dec 2023 18:59:01 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:59:01 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:58:59 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 20/21] PCI: starfive: Add JH7110 PCIe controller Date: Wed, 6 Dec 2023 18:58:38 +0800 Message-ID: <20231206105839.25805-21-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:01:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784530073660167548 X-GMAIL-MSGID: 1784530073660167548 Add StarFive JH7110 SoC PCIe controller platform driver codes, JH7110 with PLDA host PCIe core. Signed-off-by: Minda Chen Co-developed-by: Kevin Xie Reviewed-by: Mason Huo --- MAINTAINERS | 7 + drivers/pci/controller/plda/Kconfig | 12 + drivers/pci/controller/plda/Makefile | 1 + drivers/pci/controller/plda/pcie-plda.h | 71 ++- drivers/pci/controller/plda/pcie-starfive.c | 462 ++++++++++++++++++++ 5 files changed, 552 insertions(+), 1 deletion(-) create mode 100644 drivers/pci/controller/plda/pcie-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS index a034ef4cce93..7578ad250339 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16874,6 +16874,13 @@ S: Maintained F: Documentation/devicetree/bindings/pci/socionext,uniphier-pcie* F: drivers/pci/controller/dwc/pcie-uniphier* +PCIE DRIVER FOR STARFIVE JH71x0 +M: Kevin Xie +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/starfive* +F: drivers/pci/controller/plda/pcie-starfive.c + PCIE DRIVER FOR ST SPEAR13XX M: Pratyush Anand L: linux-pci@vger.kernel.org diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig index e54a82ee94f5..c0e14146d7e4 100644 --- a/drivers/pci/controller/plda/Kconfig +++ b/drivers/pci/controller/plda/Kconfig @@ -15,4 +15,16 @@ config PCIE_MICROCHIP_HOST Say Y here if you want kernel to support the Microchip AXI PCIe Host Bridge driver. +config PCIE_STARFIVE_HOST + tristate "StarFive PCIe host controller" + depends on PCI_MSI && OF + depends on ARCH_STARFIVE || COMPILE_TEST + select PCIE_PLDA_HOST + help + Say Y here if you want to support the StarFive PCIe controller in + host mode. StarFive PCIe controller uses PLDA PCIe core. + + If you choose to build this driver as module it will be dynamically + linked and module will be called pcie-starfive.ko. + endmenu diff --git a/drivers/pci/controller/plda/Makefile b/drivers/pci/controller/plda/Makefile index 4340ab007f44..0ac6851bed48 100644 --- a/drivers/pci/controller/plda/Makefile +++ b/drivers/pci/controller/plda/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_PLDA_HOST) += pcie-plda-host.o obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o +obj-$(CONFIG_PCIE_STARFIVE_HOST) += pcie-starfive.o diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index 6b29bf1f5293..80dbd34d2d51 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -10,10 +10,20 @@ #define PLDA_MAX_NUM_MSI_IRQS 32 /* PCIe Bridge Phy Regs */ +#define GEN_SETTINGS 0x80 +#define RP_ENABLE 1 +#define PCIE_PCI_IDS_DW1 0x9c +#define IDS_CLASS_CODE_SHIFT 16 +#define REVISION_ID_MASK GENMASK(7, 0) +#define CLASS_CODE_ID_MASK GENMASK(31, 8) #define PCIE_PCI_IRQ_DW0 0xa8 #define MSIX_CAP_MASK BIT(31) #define NUM_MSI_MSGS_MASK GENMASK(6, 4) #define NUM_MSI_MSGS_SHIFT 4 +#define PCI_MISC 0xb4 +#define PHY_FUNCTION_DIS BIT(15) +#define PCIE_WINROM 0xfc +#define PREF_MEM_WIN_64_SUPPORT BIT(3) #define IMASK_LOCAL 0x180 #define DMA_END_ENGINE_0_MASK 0x00000000u @@ -66,6 +76,8 @@ #define ISTATUS_HOST 0x18c #define IMSI_ADDR 0x190 #define ISTATUS_MSI 0x194 +#define PMSG_SUPPORT_RX 0x3f0 +#define PMSG_LTR_SUPPORT BIT(2) /* PCIe Master table init defines */ #define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u @@ -87,6 +99,8 @@ #define PCIE_TX_RX_INTERFACE 0x00000000u #define PCIE_CONFIG_INTERFACE 0x00000001u +#define CONFIG_SPACE_ADDR_OFFSET 0x1000u + #define ATR_ENTRY_SIZE 32 #define EVENT_A_ATR_EVT_POST_ERR 0 @@ -194,4 +208,59 @@ static inline void plda_set_default_msi(struct plda_msi *msi) msi->vector_phy = IMSI_ADDR; msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS; } -#endif + +static inline void plda_pcie_enable_root_port(struct plda_pcie_rp *plda) +{ + u32 value; + + value = readl_relaxed(plda->bridge_addr + GEN_SETTINGS); + value |= RP_ENABLE; + writel_relaxed(value, plda->bridge_addr + GEN_SETTINGS); +} + +static inline void plda_pcie_set_standard_class(struct plda_pcie_rp *plda) +{ + u32 value; + + /* set class code and reserve revision id */ + value = readl_relaxed(plda->bridge_addr + PCIE_PCI_IDS_DW1); + value &= REVISION_ID_MASK; + value |= (PCI_CLASS_BRIDGE_PCI << IDS_CLASS_CODE_SHIFT); + writel_relaxed(value, plda->bridge_addr + PCIE_PCI_IDS_DW1); +} + +static inline void plda_pcie_set_pref_win_64bit(struct plda_pcie_rp *plda) +{ + u32 value; + + value = readl_relaxed(plda->bridge_addr + PCIE_WINROM); + value |= PREF_MEM_WIN_64_SUPPORT; + writel_relaxed(value, plda->bridge_addr + PCIE_WINROM); +} + +static inline void plda_pcie_disable_ltr(struct plda_pcie_rp *plda) +{ + u32 value; + + value = readl_relaxed(plda->bridge_addr + PMSG_SUPPORT_RX); + value &= ~PMSG_LTR_SUPPORT; + writel_relaxed(value, plda->bridge_addr + PMSG_SUPPORT_RX); +} + +static inline void plda_pcie_disable_func(struct plda_pcie_rp *plda) +{ + u32 value; + + value = readl_relaxed(plda->bridge_addr + PCI_MISC); + value |= PHY_FUNCTION_DIS; + writel_relaxed(value, plda->bridge_addr + PCI_MISC); +} + +static inline void plda_pcie_write_rc_bar(struct plda_pcie_rp *plda, u64 val) +{ + void __iomem *addr = plda->bridge_addr + CONFIG_SPACE_ADDR_OFFSET; + + writel_relaxed(lower_32_bits(val), addr + PCI_BASE_ADDRESS_0); + writel_relaxed(upper_32_bits(val), addr + PCI_BASE_ADDRESS_1); +} +#endif /* _PCIE_PLDA_H */ diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c new file mode 100644 index 000000000000..441c4f5133eb --- /dev/null +++ b/drivers/pci/controller/plda/pcie-starfive.c @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PCIe host controller driver for StarFive JH7110 Soc. + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../pci.h" + +#include "pcie-plda.h" + +#define PCIE_FUNC_NUM 4 + +/* system control */ +#define STG_SYSCON_PCIE0_BASE 0x48 +#define STG_SYSCON_PCIE1_BASE 0x1f8 + +#define STG_SYSCON_AR_OFFSET 0x78 +#define STG_SYSCON_AXI4_SLVL_AR_MASK GENMASK(22, 8) +#define STG_SYSCON_AXI4_SLVL_PHY_AR(x) FIELD_PREP(GENMASK(20, 17), x) +#define STG_SYSCON_AW_OFFSET 0x7c +#define STG_SYSCON_AXI4_SLVL_AW_MASK GENMASK(14, 0) +#define STG_SYSCON_AXI4_SLVL_PHY_AW(x) FIELD_PREP(GENMASK(12, 9), x) +#define STG_SYSCON_CLKREQ BIT(22) +#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18) +#define STG_SYSCON_RP_NEP_OFFSET 0xe8 +#define STG_SYSCON_K_RP_NEP BIT(8) +#define STG_SYSCON_LNKSTA_OFFSET 0x170 +#define DATA_LINK_ACTIVE BIT(5) + +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + +struct starfive_jh7110_pcie { + struct plda_pcie_rp plda; + struct reset_control *resets; + struct clk_bulk_data *clks; + struct regmap *reg_syscon; + struct gpio_desc *power_gpio; + struct gpio_desc *reset_gpio; + struct phy *phy; + + unsigned int stg_pcie_base; + int num_clks; +}; + +/* + * The BAR0/1 of bridge should be hidden during enumeration to + * avoid the sizing and resource allocation by PCIe core. + */ +static bool starfive_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, + int offset) +{ + if (pci_is_root_bus(bus) && !devfn && + (offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1)) + return true; + + return false; +} + +static int starfive_pcie_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + if (starfive_pcie_hide_rc_bar(bus, devfn, where)) + return PCIBIOS_SUCCESSFUL; + + return pci_generic_config_write(bus, devfn, where, size, value); +} + +static int starfive_pcie_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + if (starfive_pcie_hide_rc_bar(bus, devfn, where)) { + *value = 0; + return PCIBIOS_SUCCESSFUL; + } + + return pci_generic_config_read(bus, devfn, where, size, value); +} + +static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie, + struct device *dev) +{ + int domain_nr; + + pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); + if (pcie->num_clks < 0) + return dev_err_probe(dev, pcie->num_clks, + "failed to get pcie clocks\n"); + + pcie->resets = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(pcie->resets)) + return dev_err_probe(dev, PTR_ERR(pcie->resets), + "failed to get pcie resets"); + + pcie->reg_syscon = + syscon_regmap_lookup_by_phandle(dev->of_node, + "starfive,stg-syscon"); + + if (IS_ERR(pcie->reg_syscon)) + return dev_err_probe(dev, PTR_ERR(pcie->reg_syscon), + "failed to parse starfive,stg-syscon\n"); + + pcie->phy = devm_phy_optional_get(dev, NULL); + if (IS_ERR(pcie->phy)) + return dev_err_probe(dev, PTR_ERR(pcie->phy), + "failed to get pcie phy\n"); + + domain_nr = of_get_pci_domain_nr(dev->of_node); + + if (domain_nr < 0 || domain_nr > 1) + return dev_err_probe(dev, -ENODEV, + "failed to get valid pcie domain\n"); + + if (domain_nr == 0) + pcie->stg_pcie_base = STG_SYSCON_PCIE0_BASE; + else + pcie->stg_pcie_base = STG_SYSCON_PCIE1_BASE; + + pcie->reset_gpio = devm_gpiod_get_optional(dev, "perst", + GPIOD_OUT_HIGH); + if (IS_ERR(pcie->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio), + "failed to get perst-gpio\n"); + + pcie->power_gpio = devm_gpiod_get_optional(dev, "enable", + GPIOD_OUT_LOW); + if (IS_ERR(pcie->power_gpio)) + return dev_err_probe(dev, PTR_ERR(pcie->power_gpio), + "failed to get power-gpio\n"); + + return 0; +} + +static struct pci_ops starfive_pcie_ops = { + .map_bus = plda_pcie_map_bus, + .read = starfive_pcie_config_read, + .write = starfive_pcie_config_write, +}; + +static int starfive_pcie_clk_rst_init(struct starfive_jh7110_pcie *pcie) +{ + struct device *dev = pcie->plda.dev; + int ret; + + ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); + if (ret) + return dev_err_probe(dev, ret, "failed to enable clocks\n"); + + ret = reset_control_deassert(pcie->resets); + if (ret) { + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); + dev_err_probe(dev, ret, "failed to deassert resets\n"); + } + + return ret; +} + +static void starfive_pcie_clk_rst_deinit(struct starfive_jh7110_pcie *pcie) +{ + reset_control_assert(pcie->resets); + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); +} + +static bool starfive_pcie_link_up(struct plda_pcie_rp *plda) +{ + struct starfive_jh7110_pcie *pcie = + container_of(plda, struct starfive_jh7110_pcie, plda); + int ret; + u32 stg_reg_val; + + ret = regmap_read(pcie->reg_syscon, + pcie->stg_pcie_base + STG_SYSCON_LNKSTA_OFFSET, + &stg_reg_val); + if (ret) { + dev_err(pcie->plda.dev, "failed to read link status\n"); + return false; + } + + return !!(stg_reg_val & DATA_LINK_ACTIVE); +} + +static int starfive_pcie_host_wait_for_link(struct starfive_jh7110_pcie *pcie) +{ + int retries; + + /* Check if the link is up or not */ + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (starfive_pcie_link_up(&pcie->plda)) { + dev_info(pcie->plda.dev, "port link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + + return -ETIMEDOUT; +} + +static int starfive_pcie_enable_phy(struct device *dev, + struct starfive_jh7110_pcie *pcie) +{ + int ret; + + if (!pcie->phy) + return 0; + + ret = phy_init(pcie->phy); + if (ret) + return dev_err_probe(dev, ret, + "failed to initialize pcie phy\n"); + + ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); + if (ret) { + dev_err_probe(dev, ret, "failed to set pcie mode\n"); + goto err_phy_on; + } + + ret = phy_power_on(pcie->phy); + if (ret) { + dev_err_probe(dev, ret, "failed to power on pcie phy\n"); + goto err_phy_on; + } + + return 0; + +err_phy_on: + phy_exit(pcie->phy); + return ret; +} + +static void starfive_pcie_disable_phy(struct starfive_jh7110_pcie *pcie) +{ + phy_power_off(pcie->phy); + phy_exit(pcie->phy); +} + +static void starfive_pcie_host_deinit(struct plda_pcie_rp *plda) +{ + struct starfive_jh7110_pcie *pcie = + container_of(plda, struct starfive_jh7110_pcie, plda); + + starfive_pcie_clk_rst_deinit(pcie); + if (pcie->power_gpio) + gpiod_set_value_cansleep(pcie->power_gpio, 0); + starfive_pcie_disable_phy(pcie); +} + +static int starfive_pcie_host_init(struct plda_pcie_rp *plda) +{ + struct starfive_jh7110_pcie *pcie = + container_of(plda, struct starfive_jh7110_pcie, plda); + struct device *dev = plda->dev; + int ret; + int i; + + ret = starfive_pcie_enable_phy(dev, pcie); + if (ret) + return ret; + + regmap_update_bits(pcie->reg_syscon, + pcie->stg_pcie_base + STG_SYSCON_RP_NEP_OFFSET, + STG_SYSCON_K_RP_NEP, STG_SYSCON_K_RP_NEP); + + regmap_update_bits(pcie->reg_syscon, + pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, + STG_SYSCON_CKREF_SRC_MASK, + FIELD_PREP(STG_SYSCON_CKREF_SRC_MASK, 2)); + + regmap_update_bits(pcie->reg_syscon, + pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, + STG_SYSCON_CLKREQ, STG_SYSCON_CLKREQ); + + ret = starfive_pcie_clk_rst_init(pcie); + if (ret) + return ret; + + if (pcie->power_gpio) + gpiod_set_value_cansleep(pcie->power_gpio, 1); + + if (pcie->reset_gpio) + gpiod_set_value_cansleep(pcie->reset_gpio, 1); + + /* Disable physical functions except #0 */ + for (i = 1; i < PCIE_FUNC_NUM; i++) { + regmap_update_bits(pcie->reg_syscon, + pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET, + STG_SYSCON_AXI4_SLVL_AR_MASK, + STG_SYSCON_AXI4_SLVL_PHY_AR(i)); + + regmap_update_bits(pcie->reg_syscon, + pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, + STG_SYSCON_AXI4_SLVL_AW_MASK, + STG_SYSCON_AXI4_SLVL_PHY_AW(i)); + + plda_pcie_disable_func(plda); + } + + regmap_update_bits(pcie->reg_syscon, + pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET, + STG_SYSCON_AXI4_SLVL_AR_MASK, 0); + regmap_update_bits(pcie->reg_syscon, + pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, + STG_SYSCON_AXI4_SLVL_AW_MASK, 0); + + plda_pcie_enable_root_port(plda); + plda_pcie_write_rc_bar(plda, 0); + + /* PCIe PCI Standard Configuration Identification Settings. */ + plda_pcie_set_standard_class(plda); + + /* + * The LTR message forwarding of PCIe Message Reception was set by core + * as default, but the forward id & addr are also need to be reset. + * If we do not disable LTR message forwarding here, or set a legal + * forwarding address, the kernel will get stuck after the driver probe. + * To workaround, disable the LTR message forwarding support on + * PCIe Message Reception. + */ + plda_pcie_disable_ltr(plda); + + /* Prefetchable memory window 64-bit addressing support */ + plda_pcie_set_pref_win_64bit(plda); + + /* + * Ensure that PERST has been asserted for at least 100 ms, + * the sleep value is T_PVPERL from PCIe CEM spec r2.0 (Table 2-4) + */ + msleep(100); + if (pcie->reset_gpio) + gpiod_set_value_cansleep(pcie->reset_gpio, 0); + + /* + * With a Downstream Port (<=5GT/s), software must wait a minimum + * of 100ms following exit from a conventional reset before + * sending a configuration request to the device. + */ + msleep(PCIE_RESET_CONFIG_DEVICE_WAIT_MS); + + if (starfive_pcie_host_wait_for_link(pcie)) + dev_info(dev, "port link down\n"); + + return 0; +} + +static const struct plda_pcie_host_ops sf_host_ops = { + .host_init = starfive_pcie_host_init, + .host_deinit = starfive_pcie_host_deinit, +}; + +static int starfive_pcie_probe(struct platform_device *pdev) +{ + struct starfive_jh7110_pcie *pcie; + struct device *dev = &pdev->dev; + struct plda_pcie_rp *plda; + int ret; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + plda = &pcie->plda; + plda->dev = dev; + + ret = starfive_pcie_parse_dt(pcie, dev); + if (ret) + return ret; + + plda->host_ops = &sf_host_ops; + plda->num_events = NUM_PLDA_EVENTS; + ret = plda_pcie_host_init(&pcie->plda, &starfive_pcie_ops); + if (ret) + return ret; + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + platform_set_drvdata(pdev, pcie); + + return 0; +} + +static void starfive_pcie_remove(struct platform_device *pdev) +{ + struct starfive_jh7110_pcie *pcie = platform_get_drvdata(pdev); + + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + plda_pcie_host_deinit(&pcie->plda); + platform_set_drvdata(pdev, NULL); +} + +static int starfive_pcie_suspend_noirq(struct device *dev) +{ + struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); + starfive_pcie_disable_phy(pcie); + + return 0; +} + +static int starfive_pcie_resume_noirq(struct device *dev) +{ + struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev); + int ret; + + ret = starfive_pcie_enable_phy(dev, pcie); + if (ret) + return ret; + + ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); + if (ret) { + dev_err(dev, "failed to enable clocks\n"); + starfive_pcie_disable_phy(pcie); + return ret; + } + + return 0; +} + +static const struct dev_pm_ops starfive_pcie_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(starfive_pcie_suspend_noirq, + starfive_pcie_resume_noirq) +}; + +static const struct of_device_id starfive_pcie_of_match[] = { + { .compatible = "starfive,jh7110-pcie", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, starfive_pcie_of_match); + +static struct platform_driver starfive_pcie_driver = { + .driver = { + .name = "pcie-starfive", + .of_match_table = of_match_ptr(starfive_pcie_of_match), + .pm = pm_sleep_ptr(&starfive_pcie_pm_ops), + }, + .probe = starfive_pcie_probe, + .remove_new = starfive_pcie_remove, +}; +module_platform_driver(starfive_pcie_driver); + +MODULE_DESCRIPTION("StarFive JH7110 PCIe host driver"); +MODULE_LICENSE("GPL v2"); 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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id d6-20020a170902cec600b001d09278b856si5853782plg.347.2023.12.06.03.00.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 03:00:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 1263E802B059; Wed, 6 Dec 2023 03:00:15 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378086AbjLFLAA (ORCPT + 99 others); Wed, 6 Dec 2023 06:00:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378025AbjLFK7e (ORCPT ); Wed, 6 Dec 2023 05:59:34 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE91410EB; Wed, 6 Dec 2023 02:59:08 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id E47BA24E321; Wed, 6 Dec 2023 18:59:01 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:59:01 +0800 Received: from ubuntu.localdomain (183.27.97.199) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 6 Dec 2023 18:59:00 +0800 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , "Daire McNamara" , Emil Renner Berthing , Krzysztof Kozlowski CC: , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v12 21/21] riscv: dts: starfive: add PCIe dts configuration for JH7110 Date: Wed, 6 Dec 2023 18:58:39 +0800 Message-ID: <20231206105839.25805-22-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231206105839.25805-1-minda.chen@starfivetech.com> References: <20231206105839.25805-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.199] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 06 Dec 2023 03:00:15 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784529989067754435 X-GMAIL-MSGID: 1784529989067754435 Add PCIe dts configuraion for JH7110 SoC platform. Signed-off-by: Minda Chen Reviewed-by: Hal Feng --- .../jh7110-starfive-visionfive-2.dtsi | 64 ++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ 2 files changed, 150 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index b89e9791efa7..2f8056d6f817 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -287,6 +287,22 @@ status = "okay"; }; +&pcie0 { + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; + phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + &qspi { #address-cells = <1>; #size-cells = <0>; @@ -513,6 +529,54 @@ }; }; + pcie0_pins: pcie0-0 { + clkreq-pins { + pinmux = ; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = ; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + pcie1_pins: pcie1-0 { + clkreq-pins { + pinmux = ; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = ; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + spi0_pins: spi0-0 { mosi-pins { pinmux = ; power-domains = <&pwrc JH7110_PD_VOUT>; }; + + pcie0: pcie@940000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x9 0x40000000 0x0 0x1000000>, + <0x0 0x2b000000 0x0 0x100000>; + reg-names = "cfg", "apb"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; + interrupts = <56>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; + msi-controller; + device_type = "pci"; + starfive,stg-syscon = <&stg_syscon>; + bus-range = <0x0 0xff>; + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE0_TL>, + <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE0_APB>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE0_BRG>, + <&stgcrg JH7110_STGRST_PCIE0_CORE>, + <&stgcrg JH7110_STGRST_PCIE0_APB>; + reset-names = "mst0", "slv0", "slv", "brg", + "core", "apb"; + status = "disabled"; + + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@9c0000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x9 0xc0000000 0x0 0x1000000>, + <0x0 0x2c000000 0x0 0x100000>; + reg-names = "cfg", "apb"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; + interrupts = <57>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; + msi-controller; + device_type = "pci"; + starfive,stg-syscon = <&stg_syscon>; + bus-range = <0x0 0xff>; + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE1_TL>, + <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE1_APB>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE1_BRG>, + <&stgcrg JH7110_STGRST_PCIE1_CORE>, + <&stgcrg JH7110_STGRST_PCIE1_APB>; + reset-names = "mst0", "slv0", "slv", "brg", + "core", "apb"; + status = "disabled"; + + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; }; };