From patchwork Thu Nov 10 13:45:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 18135 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp155232wru; Thu, 10 Nov 2022 05:45:54 -0800 (PST) X-Google-Smtp-Source: AMsMyM5y0CDjq7HVE/P8TDRcrMfTaHD5ksMhcKKj2hYZ3NM//adYhVeg6MiLbEmewpHQskOtnq9x X-Received: by 2002:a17:906:b050:b0:78d:99ee:4e68 with SMTP id bj16-20020a170906b05000b0078d99ee4e68mr2806164ejb.302.1668087954025; Thu, 10 Nov 2022 05:45:54 -0800 (PST) Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id wy8-20020a170906fe0800b0078334ccc570si17659592ejb.328.2022.11.10.05.45.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 05:45:54 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=iTQe34r+; arc=fail (signature failed); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 246D53858425 for ; Thu, 10 Nov 2022 13:45:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 246D53858425 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668087952; bh=BKfZ1Ph4mbuoUQe1/w0iph0J2xjKPqT6J7MB1yeiYQw=; h=Date:To:Cc:Subject:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=iTQe34r+UCJZ5Ky2yO1bHzTme5UOdtXiMb/Uyu9BM/mpDBUc9OuYRxFEAVdT4u8uf RXQTxWyG4zz8c8nCqW/WNY3MtqHwJupo2Vf6qN9VpzYsbUAZx8KI+Nbqrk06o9Qeby Wa7LkGPpAddrk2fsCabAFO6KtICzyV4xllKvjba4= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2065.outbound.protection.outlook.com [40.107.20.65]) by sourceware.org (Postfix) with ESMTPS id C777C3858C39 for ; Thu, 10 Nov 2022 13:45:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C777C3858C39 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Uehv/d9PeY2pLeJxhWzgbVy3DKHpGs+p7W8MPFtuA0WfJLRsiyu0+7mFcThVEQ/ltQZUDgMksv4c08F5JOU1V+uKcd5fb6qrGb1uOzxjzeY6UivuUUp/QT/cdfsgFfeHVPpTxEbUyFW7Q9pNoTKvm1lBwPwqGH7uThXlwr5nfu9qKN4yxp2ERsWP+z7IqcciwUAKErGMHBPTLXDmJeFArKAAZWiMtATM5IkQRz3lvrlz7RpRoymcpRINxJIhDYAIVofjTE2B5KkHHobuP5hbeSm9NbkELcT6E7oX5nNEULjFiAxtD+ri6c1x9GvI0n97yl9HMdCgdfnnmcTxytkVJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BKfZ1Ph4mbuoUQe1/w0iph0J2xjKPqT6J7MB1yeiYQw=; b=UmdbsQdgZgv1e96aDu+LCiUjxG9ypBpVC+wErhevLwQMU3Wdj/m18XWOckQOfMkZvEDMLHM4oOOe0EjhSO8ccozCtD9gvZjxAy48Dva0bAgw7AWTJZCUuRi3EL6PKKnUadmUH6qxnG8Lq9S3hqX/txkRnB7uL1RNOu8HztsCSmhQNfFv+qWaFg4AaJXJ2f1ot9t4F3LyeaJmg/SfQbkfFTIn61fLZ34ZDnaBlVzRl4kJrm6cVcWWzIcxzy/FEn6QJD0/WwSxINul3d4WzjhoicObsYnE7ISZaWv+PLLixIC0/xqKBHhFIm4BURVOs9t8/neIrJvQb5TSOpKDdnFkaQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none Received: from VE1PR04MB6560.eurprd04.prod.outlook.com (2603:10a6:803:122::25) by AM9PR04MB8633.eurprd04.prod.outlook.com (2603:10a6:20b:43c::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.22; Thu, 10 Nov 2022 13:45:31 +0000 Received: from VE1PR04MB6560.eurprd04.prod.outlook.com ([fe80::4da2:ea8b:e71e:b8d8]) by VE1PR04MB6560.eurprd04.prod.outlook.com ([fe80::4da2:ea8b:e71e:b8d8%4]) with mapi id 15.20.5791.027; Thu, 10 Nov 2022 13:45:31 +0000 Message-ID: <21665493-a9f9-3429-c9ae-ea69bc7751e2@suse.com> Date: Thu, 10 Nov 2022 14:45:30 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Content-Language: en-US To: Binutils Cc: "H.J. Lu" Subject: [PATCH] x86: fold special-operand insn attributes into a single enum X-ClientProxiedBy: FR3P281CA0077.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:1f::10) To VE1PR04MB6560.eurprd04.prod.outlook.com (2603:10a6:803:122::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VE1PR04MB6560:EE_|AM9PR04MB8633:EE_ X-MS-Office365-Filtering-Correlation-Id: ef54c021-da91-442a-351a-08dac321d5c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sD2/11gyyFK2JiUn7AlyeBPvdHO4PjuAGhXsBpJLTh3svhuXcoeL/HTggU22a1kOBy5q9Vf2yqLsVenkxk49Y6ztb9aqcljK1JbyiHPdmwZdcbyj75bGWi4wl+5BtkaP7MUmpjSzA2FLq6ptBp+bdV9tv+LH7DAA9qxxPO23Gs5YEedakE+FPfQ4XhiqQ6u38FoHnbQF/jB9ElQyqRRiqZfFld/aq0vcxrBVef0iDLuxNsEC99xIoen1yGHJFhgN7knYC3PufxaoU9PMrji3FH4w9ySiLyc3O5q0D73lLOHQqRxMZGEG6QtVaQ4zWw2pSOITM7cJzH1/j43NojFH47FqyWIWu0IikozYEO7rh2dejPrdPLcVfbfhiZTKSJcGoUSoH7cVt4LMFsxhbKS1d/BYBGiaQL7NCL9Cx2Vjd9vE/VM4bLOesOqyilFr3To2Y0oWEEqbtKnTBAroQwgDOA5PLz+03rQd1UFeJ9Z/40wP6N51+t+fH9wtV6ePCb37S0+mGumhTgdW9ygD9vLTMbsSzjEzTKTD3Jw/c4TNHNIFtf4Pbg0hwR9DxjuIOKMWyskn/giWA5lZMuhRzmM5VRH/XIy9Vm5SNC4MXYfiwtk1cyig7AtwDds//NdJE6qBQ//hOasCMokvWQvpDnlBAltJajbVShKJmnVVPGgyXvszMZdA+3T8/ALHNQZS5O6WX06xUqpLzYEYm6BCj7zzN+kTA19+Bpkh+l7cztnejrWBVJdp4HLpue9/+fzqX9VyDKaJQ1VtRK7t+j562hlBk6JbvP6eCanjGlINNJNPxKqoYLqHMlutx5UZpETS3NsC X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VE1PR04MB6560.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230022)(39860400002)(136003)(366004)(376002)(346002)(396003)(451199015)(31686004)(19627235002)(31696002)(86362001)(36756003)(2616005)(2906002)(8936002)(186003)(38100700002)(5660300002)(83380400001)(66476007)(66946007)(316002)(66556008)(4326008)(6916009)(8676002)(6506007)(26005)(6512007)(6486002)(41300700001)(478600001)(334744004)(45980500001)(43740500002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?g4yMfxzYy/CzYCKzJEERGcisZpWd?= =?utf-8?q?3mePT5wHGmkbJoduXSyWaeBxytF6VsYWcexlb5HPSZN+Jw5dF5GY1abn7d95aZIjk?= =?utf-8?q?yPietvGoMUSj9udBHSO2XO3t6jc2wFSMXPRJJiRrjoWFHyqEuqZhLXRkW1+Er1E89?= =?utf-8?q?/iK0vJCl5/CCkDAt/c38bJN3SMdzvja+Qth6g0HNfk7TTXNd8cldq4FlRK1utuOq+?= =?utf-8?q?G8egh81xuji0mPQn3TErzhnJyEJuu6IhUuMmmoYX61vXHFNvDykNhe8wFGBKgc/iL?= =?utf-8?q?BWxP29rdqRm4Cbd7G2SnGFuLpmuMGrAbA3juGADCDaiGR/yxFEd3tXF1MyjBHB5/m?= =?utf-8?q?psNdwQ1akFHHFoiIXYo/FCF2fyKf7l4T4kx3iKVQKLPwYMIPlhbBN+5YKh1UQrhKX?= =?utf-8?q?d8dP3o9Dpixs72VgWVJWTvfKBMWGus5iQLzLfrSpw5wkl5Gc5oUn03PXf5Hp5v5WA?= =?utf-8?q?vbZqdCjhK5NmfDOrAXMxIGllKEgmPhv1iCwLGYfBQtS0MCbwWd0QrLr/traUNVT/b?= =?utf-8?q?Y71uG47nYP5F6F9jT6wL8WdgN5lsmSVX0Q3JVw7Lfob/wRVzq0wIp7gg6P3vDPEHI?= =?utf-8?q?NLl6IGpSW9B9/AMVWU06lZW5ZGmC0KpHIpMBXxoPBbhu9WufZgQoIi3YMAZt2ozz+?= =?utf-8?q?MQ6p/5+vsPxi1rAieRE6bx6y4rn2mE03fniuEw2Tvf9Y5NvaoTZC+K3zqb7rYyYjo?= =?utf-8?q?1m7ySgAM11EVJ3I94OQR1YfU3ejfB37sSmga4//PyON1jVt0qfkCP/wv9bUo+rR1q?= =?utf-8?q?1ezRh5aja4wvK+MxBVhXP1aQHZcnWcEUQvOsg09TglGhfuQKw0R2AJh/E7mqRx0Db?= =?utf-8?q?NSW27w80yBMT73JQPc9WyTGC0/U+1VMYhDbzlGuq50WN7/OxcKoiuJARO2z4u5sqn?= =?utf-8?q?Lzkby5p7RWuZzev4WScvjJRyatYzHCM946Oe11jay2dMgSHVEvLcXTSxhKh+QtQgA?= =?utf-8?q?U6Y60KJYKJqX8OPZ0Kch5fgTS+e2Le0x59f1vgOqY23dEEk317NsppS1nrCRY9WXQ?= =?utf-8?q?Vo/CGhIZLyZocFLh+jnhdRqPf+qjIVag8P0QrpX9R3Zfvj9mz4dDJHya8GW6cIvBl?= =?utf-8?q?YnUnsnFsG+KWAa/YIVNznPadC8wLDFMjCwExKvcDPO3gLH10Ij6fC58UstBpTuk3n?= =?utf-8?q?duXz4gCIWQS2YApaqiHY0YU6wVtTukvR6kBYjkFMP4NlMI+UALQJ0bq3zEz8gw3E6?= =?utf-8?q?IHZtVqHiPfx4dpjwXGDYlDGDlCs+6e70JzyWroZQtpopE5dc/kDId1iKqjrcgO6h8?= =?utf-8?q?06Phvh4lZmgdb/BngAEVvXdZfcSEOU91UZKhsnIK1o97ov8495YIccGJpT7Iy7OZW?= =?utf-8?q?tx+1S8q74/ZKTVT1X9rLfIa7B1V7+b7oOg7NgR2JYwyT+X5e4CglhykXfJBfTUkwp?= =?utf-8?q?eqyoQYz4YNUX+UtqqC1Md+O3d0TEtM3X1QSU8jYFqY8IGXQYidlrPeWcPpekvggW+?= =?utf-8?q?i6gK+/PT3ZA+5QODYXURlT/K3LXzzdcZJIJj/fzVndslp+hAWzrKfv9n+6GAMc8az?= =?utf-8?q?nIUeSpeQjMr4?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: ef54c021-da91-442a-351a-08dac321d5c5 X-MS-Exchange-CrossTenant-AuthSource: VE1PR04MB6560.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2022 13:45:31.5248 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FfgCwjCe5g4oQio9aDkjuTxUopfmIS8O2LPS8AH8tL0R6p+le5wWSNdDo5cRQe3/cB+qKAz4QMCtq7yI8CDepQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB8633 X-Spam-Status: No, score=-3029.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jan Beulich via Binutils From: Jan Beulich Reply-To: Jan Beulich Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749116994554360439?= X-GMAIL-MSGID: =?utf-8?q?1749116994554360439?= Attributes which aren't used together in any single insn template can be converted from individual booleans to a single enum, as was done for a few other attributes before. This is more space efficient. Collect together all attributes which express special operand constraints (and which fit the criteria for folding). --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2071,7 +2071,7 @@ operand_size_match (const insn_template { if (i.types[j].bitfield.class != Reg && i.types[j].bitfield.class != RegSIMD - && t->opcode_modifier.anysize) + && t->opcode_modifier.operandconstraint == ANY_SIZE) continue; if (t->operand_types[j].bitfield.class == Reg @@ -4518,7 +4518,7 @@ load_insn_p (void) { /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu, bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */ - if (i.tm.opcode_modifier.anysize) + if (i.tm.opcode_modifier.operandconstraint == ANY_SIZE) return 0; /* pop. */ @@ -5107,7 +5107,7 @@ md_assemble (char *line) if (!process_operands ()) return; } - else if (!quiet_warnings && i.tm.opcode_modifier.ugh) + else if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) { /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ as_warn (_("translating to `%sp'"), i.tm.name); @@ -6020,7 +6020,7 @@ check_VecOperands (const insn_template * } /* Check if default mask is allowed. */ - if (t->opcode_modifier.nodefmask + if (t->opcode_modifier.operandconstraint == NO_DEFAULT_MASK && (!i.mask.reg || i.mask.reg->reg_num == 0)) { i.error = no_default_mask; @@ -6102,7 +6102,7 @@ check_VecOperands (const insn_template * /* For some special instructions require that destination must be distinct from source registers. */ - if (t->opcode_modifier.distinctdest) + if (t->opcode_modifier.operandconstraint == DISTINCT_DEST) { unsigned int dest_reg = i.operands - 1; @@ -7047,7 +7047,7 @@ process_suffix (void) i.suffix = QWORD_MNEM_SUFFIX; else if (i.reg_operands && (i.operands > 1 || i.types[0].bitfield.class == Reg) - && !i.tm.opcode_modifier.addrprefixopreg) + && i.tm.opcode_modifier.operandconstraint != ADDR_PREFIX_OP_REG) { unsigned int numop = i.operands; @@ -7414,7 +7414,7 @@ process_suffix (void) break; } - if (i.tm.opcode_modifier.addrprefixopreg) + if (i.tm.opcode_modifier.operandconstraint == ADDR_PREFIX_OP_REG) { gas_assert (!i.suffix); gas_assert (i.reg_operands); @@ -7808,7 +7808,7 @@ process_operands (void) } } } - else if (i.tm.opcode_modifier.implicit1stxmm0) + else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0) { gas_assert ((MAX_OPERANDS - 1) > dupl && (i.tm.opcode_modifier.vexsources @@ -7876,7 +7876,7 @@ process_operands (void) i.reg_operands--; i.tm.operands--; } - else if (i.tm.opcode_modifier.implicitquadgroup) + else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_QUAD_GROUP) { unsigned int regnum, first_reg_in_group, last_reg_in_group; @@ -7893,7 +7893,7 @@ process_operands (void) register_prefix, i.op[1].regs->reg_name, last_reg_in_group, i.tm.name); } - else if (i.tm.opcode_modifier.regkludge) + else if (i.tm.opcode_modifier.operandconstraint == REG_KLUDGE) { /* The imul $imm, %reg instruction is converted into imul $imm, %reg, %reg, and the clr %reg instruction @@ -7963,7 +7963,7 @@ process_operands (void) i.tm.base_opcode |= i.op[op].regs->reg_num; if ((i.op[op].regs->reg_flags & RegRex) != 0) i.rex |= REX_B; - if (!quiet_warnings && i.tm.opcode_modifier.ugh) + if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) { /* Warn about some common errors, but press on regardless. The first case can be generated by gcc (<= 2.8.1). */ @@ -8190,7 +8190,7 @@ build_modrm_byte (void) unsigned int vvvv; /* Swap two source operands if needed. */ - if (i.tm.opcode_modifier.swapsources) + if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES) { vvvv = source; source = dest; --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -729,9 +729,8 @@ static bitfield opcode_modifiers[] = BITFIELD (FloatR), BITFIELD (Size), BITFIELD (CheckRegSize), - BITFIELD (DistinctDest), + BITFIELD (OperandConstraint), BITFIELD (MnemonicSize), - BITFIELD (Anysize), BITFIELD (No_bSuf), BITFIELD (No_wSuf), BITFIELD (No_lSuf), @@ -742,14 +741,10 @@ static bitfield opcode_modifiers[] = BITFIELD (IsString), BITFIELD (RegMem), BITFIELD (BNDPrefixOk), - BITFIELD (RegKludge), - BITFIELD (Implicit1stXmm0), BITFIELD (PrefixOk), - BITFIELD (AddrPrefixOpReg), BITFIELD (IsPrefix), BITFIELD (ImmExt), BITFIELD (NoRex64), - BITFIELD (Ugh), BITFIELD (Vex), BITFIELD (VexVVVV), BITFIELD (VexW), @@ -764,9 +759,6 @@ static bitfield opcode_modifiers[] = BITFIELD (StaticRounding), BITFIELD (SAE), BITFIELD (Disp8MemShift), - BITFIELD (NoDefMask), - BITFIELD (ImplicitQuadGroup), - BITFIELD (SwapSources), BITFIELD (Optimize), BITFIELD (ATTMnemonic), BITFIELD (ATTSyntax), --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -495,17 +495,35 @@ enum Size, /* check register size. */ CheckRegSize, + /* any memory size */ +#define ANY_SIZE 1 + /* fake an extra reg operand for clr, imul and special register + processing for some instructions. */ +#define REG_KLUDGE 2 + /* deprecated fp insn, gets a warning */ +#define UGH 3 + /* An implicit xmm0 as the first operand */ +#define IMPLICIT_1ST_XMM0 4 + /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. + It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). + */ +#define IMPLICIT_QUAD_GROUP 5 + /* Two source operands are swapped. */ +#define SWAP_SOURCES 6 + /* Default mask isn't allowed. */ +#define NO_DEFAULT_MASK 7 + /* Address prefix changes register operand */ +#define ADDR_PREFIX_OP_REG 8 /* Instrucion requires that destination must be distinct from source registers. */ - DistinctDest, +#define DISTINCT_DEST 9 + OperandConstraint, /* instruction ignores operand size prefix and in Intel mode ignores mnemonic size suffix check. */ #define IGNORESIZE 1 /* default insn size depends on mode */ #define DEFAULTSIZE 2 MnemonicSize, - /* any memory size */ - Anysize, /* b suffix on instruction illegal */ No_bSuf, /* w suffix on instruction illegal */ @@ -533,11 +551,6 @@ enum RegMem, /* quick test if branch instruction is MPX supported */ BNDPrefixOk, - /* fake an extra reg operand for clr, imul and special register - processing for some instructions. */ - RegKludge, - /* An implicit xmm0 as the first operand */ - Implicit1stXmm0, #define PrefixNone 0 #define PrefixRep 1 #define PrefixHLERelease 2 /* Okay with an XRELEASE (0xf3) prefix. */ @@ -548,16 +561,12 @@ enum #define PrefixHLELock 5 /* Okay with a LOCK prefix. */ #define PrefixHLEAny 6 /* Okay with or without a LOCK prefix. */ PrefixOk, - /* Address prefix changes register operand */ - AddrPrefixOpReg, /* opcode is a prefix */ IsPrefix, /* instruction has extension in 8 bit imm */ ImmExt, /* instruction don't need Rex64 prefix. */ NoRex64, - /* deprecated fp insn, gets a warning */ - Ugh, /* insn has VEX prefix: 1: 128bit VEX prefix (or operand dependent). 2: 256bit VEX prefix. @@ -700,17 +709,6 @@ enum #define DISP8_SHIFT_VL 7 Disp8MemShift, - /* Default mask isn't allowed. */ - NoDefMask, - - /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. - It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). - */ - ImplicitQuadGroup, - - /* Two source operands are swapped. */ - SwapSources, - /* Support encoding optimization. */ Optimize, @@ -745,9 +743,8 @@ typedef struct i386_opcode_modifier unsigned int floatr:1; unsigned int size:2; unsigned int checkregsize:1; - unsigned int distinctdest:1; + unsigned int operandconstraint:4; unsigned int mnemonicsize:2; - unsigned int anysize:1; unsigned int no_bsuf:1; unsigned int no_wsuf:1; unsigned int no_lsuf:1; @@ -758,14 +755,10 @@ typedef struct i386_opcode_modifier unsigned int isstring:2; unsigned int regmem:1; unsigned int bndprefixok:1; - unsigned int regkludge:1; - unsigned int implicit1stxmm0:1; unsigned int prefixok:3; - unsigned int addrprefixopreg:1; unsigned int isprefix:1; unsigned int immext:1; unsigned int norex64:1; - unsigned int ugh:1; unsigned int vex:2; unsigned int vexvvvv:2; unsigned int vexw:2; @@ -780,9 +773,6 @@ typedef struct i386_opcode_modifier unsigned int staticrounding:1; unsigned int sae:1; unsigned int disp8memshift:3; - unsigned int nodefmask:1; - unsigned int implicitquadgroup:1; - unsigned int swapsources:1; unsigned int optimize:1; unsigned int attmnemonic:1; unsigned int attsyntax:1; --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -75,6 +75,17 @@ #define Size32 Size=SIZE32 #define Size64 Size=SIZE64 +#define AddrPrefixOpReg OperandConstraint=ADDR_PREFIX_OP_REG | \ + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf +#define Anysize OperandConstraint=ANY_SIZE +#define DistinctDest OperandConstraint=DISTINCT_DEST +#define Implicit1stXmm0 OperandConstraint=IMPLICIT_1ST_XMM0 +#define ImplicitQuadGroup OperandConstraint=IMPLICIT_QUAD_GROUP +#define NoDefMask OperandConstraint=NO_DEFAULT_MASK +#define RegKludge OperandConstraint=REG_KLUDGE +#define SwapSources OperandConstraint=SWAP_SOURCES +#define Ugh OperandConstraint=UGH + #define IgnoreSize MnemonicSize=IGNORESIZE #define DefaultSize MnemonicSize=DEFAULTSIZE @@ -91,8 +102,6 @@ #define HLEPrefixRelease PrefixOk=PrefixHLERelease #define NoTrackPrefixOk PrefixOk=PrefixNoTrack -#define AddrPrefixOpReg AddrPrefixOpReg|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf - #define Space0F OpcodeSpace=SPACE_0F #define Space0F38 OpcodeSpace=SPACE_0F38 #define Space0F3A OpcodeSpace=SPACE_0F3A