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[178.235.179.97]) by smtp.gmail.com with ESMTPSA id ay22-20020a170906d29600b009efe6fdf615sm5241373ejb.150.2023.12.04.04.55.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 04:55:37 -0800 (PST) From: Konrad Dybcio Date: Mon, 04 Dec 2023 13:55:20 +0100 Subject: [PATCH v2 1/6] dt-bindings: arm-smmu: Document SM8[45]50 GPU SMMU MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v2-1-2a437588e563@linaro.org> References: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701694533; l=2754; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1ykSmvOZZDjJjgZpitbyB4XwAgvbWrZhIXxM64S4nPE=; b=lj3IMiwPIJxgczSTOsCkVKkVF04JuQ2p6btaSUMQQGimuIK9Sqsb4x4moWx+oYn8OzCWFpfam br91WBeade2BjmO2oLO7ObprbqxSPbY8KcKz1j29Mnt3F70tYkAnC9D X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Mon, 04 Dec 2023 04:55:59 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784356077429666814 X-GMAIL-MSGID: 1784356077429666814 SM8450 and SM8550 both use a Qualcomm-modified MMU500 for their GPU. In both cases, it requires a set of clocks to be enabled. Describe that. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/iommu/arm,smmu.yaml | 48 +++++++++++++++++++++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index aa9e1c0895a5..19dba93a7654 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -89,6 +89,8 @@ properties: - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 + - qcom,sm8450-smmu-500 + - qcom,sm8550-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -453,6 +455,50 @@ allOf: - description: Voter clock required for HLOS SMMU access - description: Interface clock required for register access + - if: + properties: + compatible: + const: qcom,sm8450-smmu-500 + then: + properties: + clock-names: + items: + - const: gmu + - const: hub + - const: hlos + - const: bus + - const: iface + - const: ahb + + clocks: + items: + - description: GMU clock + - description: GPU HUB clock + - description: HLOS vote clock + - description: GPU memory bus clock + - description: GPU SNoC bus clock + - description: GPU AHB clock + + - if: + properties: + compatible: + const: qcom,sm8550-smmu-500 + then: + properties: + clock-names: + items: + - const: hlos + - const: bus + - const: iface + - const: ahb + + clocks: + items: + - description: HLOS vote clock + - description: GPU memory bus clock + - description: GPU SNoC bus clock + - description: GPU AHB clock + # Disallow clocks for all other platforms with specific compatibles - if: properties: @@ -473,8 +519,6 @@ allOf: - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8350-smmu-500 - - qcom,sm8450-smmu-500 - - qcom,sm8550-smmu-500 then: properties: clock-names: false From patchwork Mon Dec 4 12:55:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 173282 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp2739893vqy; Mon, 4 Dec 2023 04:56:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IGcq5M6rh+RDhpJtLlyodZ+kviif9oaUMV/I/V4k/g2PIE0A3R/LQWV05iviCQ5761goDbg X-Received: by 2002:a05:6a00:2284:b0:6ce:5630:1c77 with SMTP id f4-20020a056a00228400b006ce56301c77mr1139370pfe.57.1701694574294; Mon, 04 Dec 2023 04:56:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701694574; cv=none; d=google.com; s=arc-20160816; b=ZSYiMJBNMCR56mo/QMYfMeLBL0yedEmsKi4oQLR9vFB02JRhAOXKlZZi3U9Vkc4ohs UDelH1zMLi6mZOi6mziR+3gPh0LXDbCO2yYV/RPIPVxiOqiBsDN0WJY3G2eIUfSxmluK DAjUx0mGxBYTJQb/kjSzWLdbIUH9Az7xOzGz+DAoQZKFUiMV1IOinO26Vh8CYiGRDr3H LhbQ4NUinVHCTYfRhioE09uzchACd49Q0AYa++67deRpZFPw3MWSfyhL/6wTiAt9gTs6 l5mY/ZXd+av4n0J4MgU8RnbdF8bngbBWTDARJDshLbWWipXPc6NbkcSTvVYbrG5zUUdx ETlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=m/scYT3hZ9U86e3nTrsd4m2SOrNBxrMSkO8yKXa3OKg=; fh=zzYSWXNBsU2oipz3/KLm28IOiO9aOMgcMqtn4vFvWpY=; b=MQL8Nq9uk0QUBfpmLjKVix2h9anwxa5emrSimYxbr2q6cMhgZbmhQgI/GD775SIM4A Um5jBNP6ouS9jcLvt5NgGm79ND4GVLUZtP5KYxqFV7KHJD7nY+g4dc6BOFGuWJjgQuka NQ8l49oz4yJPZaUczPW6gNtUePFUdM5v0vhcWnOeYlDdz+HRCrfa1DVLybBMlc5GfMDz rzFI9H+rvkUVSaYyUfRPKkYWH/Jys1zGscivTD92Snee71FeOXvmSuNDPJYcy+d2iGId QkhblRzRg41jZ6dri0nwKMdViKbCmPoSUvAOIQaI16nhqhlDUlRHl/O4hKHYvsOgW9bs hHZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b4yzsUly; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from snail.vger.email (snail.vger.email. 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[178.235.179.97]) by smtp.gmail.com with ESMTPSA id ay22-20020a170906d29600b009efe6fdf615sm5241373ejb.150.2023.12.04.04.55.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 04:55:39 -0800 (PST) From: Konrad Dybcio Date: Mon, 04 Dec 2023 13:55:21 +0100 Subject: [PATCH v2 2/6] arm64: dts: qcom: sm8450: Add GPU nodes MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v2-2-2a437588e563@linaro.org> References: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701694533; l=7180; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=CUEgyrTkc+PFJXmRHVyPymkBE71IGdpDnV6mBH5mDlk=; b=n/rpi+cAz5c+c7My2pM/6gxPtCAGoHdn8etrFChtq1Bj5x6pQ+VpirxUWAfL7AKSqCrbCDW1B MDeIcK0Nc4cDs8VvMw9em4hxU1F8Aw3mOmGPTLhFz1rkYdDfl1KMdxa X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 04 Dec 2023 04:56:03 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784356090233964695 X-GMAIL-MSGID: 1784356090233964695 Add the required nodes to support the A730 GPU. Reviewed-by: Neil Armstrong Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 202 +++++++++++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index bde9c1093384..e9664672c160 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -2019,6 +2021,206 @@ tcsr: syscon@1fc0000 { reg = <0x0 0x1fc0000 0x0 0x30000>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-730.1", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x400>, + <&adreno_smmu 1 0x400>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-818000000 { + opp-hz = /bits/ 64 <818000000>; + opp-level = ; + }; + + opp-791000000 { + opp-hz = /bits/ 64 <791000000>; + opp-level = ; + }; + + opp-734000000 { + opp-hz = /bits/ 64 <734000000>; + opp-level = ; + }; + + opp-640000000 { + opp-hz = /bits/ 64 <640000000>; + opp-level = ; + }; + + opp-599000000 { + opp-hz = /bits/ 64 <599000000>; + opp-level = ; + }; + + opp-545000000 { + opp-hz = /bits/ 64 <545000000>; + opp-level = ; + }; + + opp-492000000 { + opp-hz = /bits/ 64 <492000000>; + opp-level = ; + }; + + opp-421000000 { + opp-hz = /bits/ 64 <421000000>; + opp-level = ; + }; + + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-level = ; + }; + + opp-317000000 { + opp-hz = /bits/ 64 <317000000>; + opp-level = ; + }; + + opp-285000000 { + opp-hz = /bits/ 64 <285000000>; + opp-level = ; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x400>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8450-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "gmu", + "hub", + "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8450-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; 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[178.235.179.97]) by smtp.gmail.com with ESMTPSA id ay22-20020a170906d29600b009efe6fdf615sm5241373ejb.150.2023.12.04.04.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 04:55:42 -0800 (PST) From: Konrad Dybcio Date: Mon, 04 Dec 2023 13:55:22 +0100 Subject: [PATCH v2 3/6] arm64: dts: qcom: sm8550: Add GPU nodes MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v2-3-2a437588e563@linaro.org> References: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v2-0-2a437588e563@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701694533; l=5785; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Yb/XfhNkL2cLIAdC0dUOyswve2maY47HKpIqukNc+Dw=; b=+ZJ6RcBAQK3p+vlX7qkHyaNJMOXR8PuT98SWByMX2AACmjrt6djSkhi7s17leLWxtGuCl8B08 GnLAZ6WRhcSDP2pQODQG518pS5mvV/1fivdrLm8ASD2BwZhW66PFKro X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 04 Dec 2023 05:12:52 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784356159019195828 X-GMAIL-MSGID: 1784357137807723637 Add the required nodes to support the A740 GPU. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 166 +++++++++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7bafb3d88d69..8f59085c804d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1984,6 +1984,128 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43050a01", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-615000000 { + opp-hz = /bits/ 64 <615000000>; + opp-level = ; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = ; + }; + + opp-475000000 { + opp-hz = /bits/ 64 <475000000>; + opp-level = ; + }; + + opp-401000000 { + opp-hz = /bits/ 64 <401000000>; + opp-level = ; + }; + + opp-348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-level = ; + }; + + opp-295000000 { + opp-hz = /bits/ 64 <295000000>; + opp-level = ; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8550-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -1995,6 +2117,50 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8550-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; From patchwork Mon Dec 4 12:55:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 173298 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp2751641vqy; Mon, 4 Dec 2023 05:12:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IGpEK6qy7YisK4u11w8nnlKxQmNwYUu4lfz2Z0w81KOZ/sNHWgLEO3nh4O95JXXOyDzK+Oq X-Received: by 2002:a05:6a21:788e:b0:18f:5f5b:c0f with SMTP id bf14-20020a056a21788e00b0018f5f5b0c0fmr1695805pzc.36.1701695579111; Mon, 04 Dec 2023 05:12:59 -0800 (PST) ARC-Seal: i=1; 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Reviewed-by: Neil Armstrong Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index eef811def39b..9fe51d308675 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -596,6 +596,14 @@ &gcc { <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio17"; From patchwork Mon Dec 4 12:55:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 173301 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp2751898vqy; Mon, 4 Dec 2023 05:13:21 -0800 (PST) X-Google-Smtp-Source: AGHT+IFDUlRWwLOdNWRKij8QZ2h5GyfCfPPnEDEPXgLGXGrpb9Rm1sz1+yoRlkm9DELfPAz3x8s0 X-Received: by 2002:a17:902:e543:b0:1d0:8a8c:56ad with SMTP id n3-20020a170902e54300b001d08a8c56admr3316258plf.102.1701695601121; Mon, 04 Dec 2023 05:13:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701695601; cv=none; d=google.com; s=arc-20160816; b=pcGqhbI4x0EPjcRRj0uGYqOo6Y6+iEKK1jOQRsjzDpkQbwpnirNw7a/UaaYMHbCDlL MHH6SG3VwhHe4ZgWzsbstZDwjqtUMnfUYS4UvWu3/ioAijuRFKNF8kkNYl3sCgInoKmf et7fOAFtRZ7pA5iIKApqVc7L/AETDEEa6wHKkQEifmrJc0b0kleH+1sOXf+AG954k3zb YaK5dkLFFOR16JQQIgf7tRvjVA5zgJZHMgLmJrt9msYjLrLLyKHtDAr5dQGPjra5Aq64 nsBgA5v5oQG6IpGn1sv/oLGddUNoaWqKMTRS8Sv68d1s14nXe5emmccCUNH+6+k7RRGk +pMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=AYBJZvf16al31yAEkvLrTZBLEk08fvZeDLHzDDQHdx0=; fh=zzYSWXNBsU2oipz3/KLm28IOiO9aOMgcMqtn4vFvWpY=; b=bDRW4J6geBnCHWZfu7LUAOCTklDTRKTbu5Tun0qldEccQs/wJhpUU1G+Ho5JGbd+yO 6pTRhYc24ZOKd3v0BVP+OY2PJGRxrm9iIseVwegBem2bz6+2f905LQt4BEoogFXNpOlB OCEhMdRDxztYHH80nDhZytQ/7vrlGVzxmz2LecuXSxUI4pUaTKOsOhmnke3MuOlT0GzR IhKCnkYMSCmwLeElytsL4GxXidYiXUZ8aVeMCbchPvGNxBqvvd7pMDePdsYpguRKAnrF qSgPk32aCa4SdPE1YtWyE94ERsge90K++QnJ/kOYiJeis/jnJe0EDcxKAdP4rTXBtL7S eo9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I88nEEOK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from howler.vger.email (howler.vger.email. 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Reviewed-by: Neil Armstrong Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 9a70875028b7..52244e9bfdee 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -512,6 +512,14 @@ vreg_l3g_1p2: ldo3 { }; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; + }; +}; + &i2c_master_hub_0 { status = "okay"; }; From patchwork Mon Dec 4 12:55:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 173300 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp2751860vqy; Mon, 4 Dec 2023 05:13:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IFF0evLaQde0DrHM3qL3CGmEc19r7HwjEwqAOKWohZV41B9JzAtNMhzfdpsN3XXIod7Bhko X-Received: by 2002:a05:6a20:734e:b0:185:d125:ea70 with SMTP id v14-20020a056a20734e00b00185d125ea70mr4655450pzc.19.1701695597805; Mon, 04 Dec 2023 05:13:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701695597; cv=none; d=google.com; s=arc-20160816; b=A3ZOj4jY9YH2sleNFU8zxHIJRqTRyFZtLhObriQGaptJjua7TO6cgQwe4JBisZmYTP IZiqmpFBWQd37+MBSM7GXyoZWoywfIx6+jiwpeqoZR8mWVaZ4JMCDjuE+JTCRzEeMdSF lfdXfI0o8nMJoS+4Z6N0ju5gx8gAiab+26imIkoaBpVPykm/RAjdrbflJfM1HqxpRwY/ /MaYA6R1NjgDQSaWgT7noc1qS9Hy4NeVyTFO0AAmFQHhvU1RekZkj+tFQikALbkYnUAw FgCO2Tb1eZ77bL3FKictR8fKY3guSCgWJsqn1/KgpIW3+e+o60hXPI1nQtGYHTSiAwN9 aANw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=rNQ9eoIjbihkMBids/A7yvSvLEz/1dSNBCDwED7GiWA=; fh=zzYSWXNBsU2oipz3/KLm28IOiO9aOMgcMqtn4vFvWpY=; b=VWwlxrFAFWAikKgR6B19W3t5Slj2mvlHuPJ72dEPA15EFAbsn+Ff9F55nueXFWL+7u kV5dxwTJZWNVOZ2eaG1/XFiF9tVCTssFgNzl9dRkSWO/k/AeS0MDhdlLpvXkVg/vS+w3 m4Qa7JmSrHtcFZJJ5G75V2KdVZtBDKdngbd5m8KlhY9equgFogJJPIsiuVvKYLdikWFA n0naIuJvNKdVVIWCLLnaAo3jk1JTBHriG2J8U5W+Wb+gMV/3AQINKbAHgwNFKkjO+fQt nRne0eUtIBkFlJxCyip9u10+pnyqfRCyWzVxRs0RlYMWvV7T+Lj1Np4eukjbizmTaLJP 9vzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HaPsjEty; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from fry.vger.email (fry.vger.email. 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Reviewed-by: Neil Armstrong Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 20153d08edde..a20d5d76af35 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -580,6 +580,14 @@ &dispcc { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8450/a730_zap.mbn"; + }; +}; + &i2c9 { clock-frequency = <400000>; status = "okay";