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server2.sourceware.org X-QQ-mid: bizesmtp63t1701643663t5yd53k1 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 04 Dec 2023 06:47:42 +0800 (CST) X-QQ-SSF: 01400000002000G0V000B00A0000000 X-QQ-FEAT: NzZVSmv0f+lXnt8bb4+g3B+mGSz3k13HPWwfUXfD2zObfH6yhMaX9H+ZfwtjU iO+GHYL+tzFBIaRgBKcfEXjjxrJlQIeUUjPS1VpSR0Jj3RybhhnaCsehMrE3LnAy0EPXjrB 8tAo2O9oq1XFek2Bt+3XfzXSFV+phJOG664sv7ORElhuiUcpkYFhLWWQ0cvLoe7cNzVStFf RDGFoRu6m1ti95TCVWTPCU2jDYRhTUbCcdJUcnOD044AlF/cHNJY6/n7/HwSED5rHbIbYcR tfuqj2gQXtPH9MeyAu6g5v3rjsSWK7taXYJ8Cl7tZWK35/x+IEfJqvSKzlXXjZVtK2zyjnx MLOHOj908i2OMP8rrCAp5PmbTyw0TiiwSfJBEEI X-QQ-GoodBg: 2 X-BIZMAIL-ID: 14818414965865278380 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Robostify the W43, W86, W87 constraint enabled attribute Date: Mon, 4 Dec 2023 06:47:41 +0800 Message-Id: <20231203224741.3438009-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784302743715484555 X-GMAIL-MSGID: 1784302743715484555 Committed as it is obvious fix. gcc/ChangeLog: * config/riscv/riscv.md: Rostify the constraints. --- gcc/config/riscv/riscv.md | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 4c6f63677df..ff521454876 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -515,13 +515,28 @@ (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 2")) (const_string "no") - (and (eq_attr "group_overlap" "W42,W43") + (and (eq_attr "group_overlap" "W42") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 4")) (const_string "no") - (and (eq_attr "group_overlap" "W84,W86,W87") + (and (eq_attr "group_overlap" "W84") (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 8")) (const_string "no") + + ;; According to RVV ISA: + ;; The destination EEW is greater than the source EEW, the source EMUL is at least 1, + ;; and the overlap is in the highest-numbered part of the destination register group + ;; (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not). + ;; So the source operand should have LMUL >= 1. + (and (eq_attr "group_overlap" "W43") + (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 4 + && riscv_get_v_regno_alignment (GET_MODE (operands[3])) >= 1")) + (const_string "no") + + (and (eq_attr "group_overlap" "W86,W87") + (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 8 + && riscv_get_v_regno_alignment (GET_MODE (operands[3])) >= 1")) + (const_string "no") ] (const_string "yes")))