From patchwork Fri Dec 1 10:40:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 172408 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp1023711vqy; Fri, 1 Dec 2023 02:40:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IFDmBOUXK8J2gzm8K+ZypHAPXTCrsDAAWB9WO4PA+skApWDrYrEYsOizw+LukcjRXNvwh1L X-Received: by 2002:a05:6358:4407:b0:16d:abc7:bfab with SMTP id z7-20020a056358440700b0016dabc7bfabmr29713663rwc.15.1701427249495; Fri, 01 Dec 2023 02:40:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701427249; cv=none; d=google.com; s=arc-20160816; b=axmHTRBT3Yr4CktNkaMIJWureI2XynGxsxZo4FPtFgQCZusXsL54DVCjH7bzhRopfs lRVEcaGdO3FD0J4wAy/Qsceky5IWZREiM/T7jvrMN2LyNa5NtPyouEp5kXW6ScEYwWd1 LisQPKBbkxqFY4o00U5JZJ0py+uk1Y4cnLt5OkX5QFPdpSoD/IzWk+QogUlrAGwSYvJD rovUf/QKi/jLdu9ybgMynHyLpw7iBm8OKyudgF9m4j+pYmBa3VPVY/hFi7Nkpn9+Hov9 L7RNI2M2zYlYOelNZ/6icGTa9JTRHGOBN1z4GvBThFPXRBqskj2xqmcrh6DJs0iygCXE X3vQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cB3mfzZEf189YNWWwDvr3l8knGHxkOsFPnRstSCbdJw=; fh=VZHXHo+vwBqT7vOg4dFYBUvOBDmtIVtwH9XG5mvsu+Q=; b=m9bS2iigxRK+imaIX8fdfw7H2WoG7N2ldy3+mlmRIpycogrc3oGZfCss2dcQSpjK6H jJNteqBTa+HYZTuhewNpxAKF5XLCTp6168l1vIcM3kY+OVzkaSRZCT7f3rzP/R+CbgRs l8K7vu1zmcD6JwwTJeGmpPyJsY8/ImNe58wv8Nw48QFZAUZpg+B8+OhyXJL03dBRNV86 //8+SKrOhTNiQPwpm6nOpMbAO2a2sJxFuFY6YvOnGubL+h77Nvk7wZLpuQIVur1f3heQ 7J2O0rNLd+U+tSU3j3eMkWjgmR43LK44cWYFa3HtZ+kpCa/AlQETin4U9X/M1ctwNOuK IAdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=TcZPEQmP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from agentk.vger.email (agentk.vger.email. [23.128.96.32]) by mx.google.com with ESMTPS id x2-20020a654542000000b005c648edd16csi533137pgr.884.2023.12.01.02.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Dec 2023 02:40:49 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=TcZPEQmP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id C1DDA80F648F; Fri, 1 Dec 2023 02:40:44 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378326AbjLAKka (ORCPT + 99 others); Fri, 1 Dec 2023 05:40:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378239AbjLAKk3 (ORCPT ); Fri, 1 Dec 2023 05:40:29 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3716D4A for ; Fri, 1 Dec 2023 02:40:35 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A31F6660739D; Fri, 1 Dec 2023 10:40:33 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1701427234; bh=UdqAnQyqUpZF3YGNOviQ2mxK+3TR9j8a8/SIDFRzpkA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TcZPEQmPQ3RJ9k95K1YM75cPXqO5FMKLgLedx0yqCugFsRH7QTEDL2+jJFBOmWuyW xLWJ3/uez5Cj4VrqYfqCWhFrqLJjn2qcPtdgPJ6cL7Exvk3jMJXrvMJESZuyzhWVhY +/9VUcMasAnbvibVG1GIlrmZ9WehDXpXQ5faC+V0XhGog0CjYfryMieThrR+z/tXjT ZjSl6B9m3qo3RrYAMH/wJWyqqTQPIh5yGCjyxKjVf49UhaNBO8gsjRmJ5srNv+2BJF 1U5M8lBY7EjkDqUmvds3BzKEQ9WUw2deb2WsgVHLuFKafX/js4SJHCOy/e2xnrjsFt 26V3cp06vH5Pw== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, kernel@collabora.com, m.szyprowski@samsung.com, krzysztof.kozlowski@linaro.org Subject: [PATCH v3 1/3] drm/panfrost: Ignore core_mask for poweroff and disable PWRTRANS irq Date: Fri, 1 Dec 2023 11:40:25 +0100 Message-ID: <20231201104027.35273-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231201104027.35273-1-angelogioacchino.delregno@collabora.com> References: <20231201104027.35273-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Fri, 01 Dec 2023 02:40:45 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784075779575957706 X-GMAIL-MSGID: 1784075779575957706 Some SoCs may be equipped with a GPU containing two core groups and this is exactly the case of Samsung's Exynos 5422 featuring an ARM Mali-T628 MP6 GPU: the support for this GPU in Panfrost is partial, as this driver currently supports using only one core group and that's reflected on all parts of it, including the power on (and power off, previously to this patch) function. The issue with this is that even though executing the soft reset operation should power off all cores unconditionally, on at least one platform we're seeing a crash that seems to be happening due to an interrupt firing which may be because we are calling power transition only on the first core group, leaving the second one unchanged, or because ISR execution was pending before entering the panfrost_gpu_power_off() function and executed after powering off the GPU cores, or all of the above. Finally, solve this by: - Avoid to enable the power transition interrupt on reset; and - Ignoring the core_mask and ask the GPU to poweroff both core groups Fixes: 22aa1a209018 ("drm/panfrost: Really power off GPU cores in panfrost_gpu_power_off()") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Boris Brezillon Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_gpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c index 09f5e1563ebd..bd41617c5e4b 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -78,7 +78,12 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) } gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL); - gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL); + + /* Only enable the interrupts we care about */ + gpu_write(pfdev, GPU_INT_MASK, + GPU_IRQ_MASK_ERROR | + GPU_IRQ_PERFCNT_SAMPLE_COMPLETED | + GPU_IRQ_CLEAN_CACHES_COMPLETED); /* * All in-flight jobs should have released their cycle @@ -425,11 +430,10 @@ void panfrost_gpu_power_on(struct panfrost_device *pfdev) void panfrost_gpu_power_off(struct panfrost_device *pfdev) { - u64 core_mask = panfrost_get_core_mask(pfdev); int ret; u32 val; - gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present & core_mask); + gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present); ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO, val, !val, 1, 1000); if (ret) @@ -441,7 +445,7 @@ void panfrost_gpu_power_off(struct panfrost_device *pfdev) if (ret) dev_err(pfdev->dev, "tiler power transition timeout"); - gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present & core_mask); + gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present); ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO, val, !val, 0, 1000); if (ret) From patchwork Fri Dec 1 10:40:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 172409 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp1024004vqy; Fri, 1 Dec 2023 02:41:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IGwqJhHZB3+/uKalmkSPprhT2nFLJXcSLWN7vUgkLdhwXOqcU33S7T8dGaVWZkOfmeTVKer X-Received: by 2002:a05:6a20:158b:b0:18b:985e:8035 with SMTP id h11-20020a056a20158b00b0018b985e8035mr26748071pzj.12.1701427303177; Fri, 01 Dec 2023 02:41:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701427303; cv=none; d=google.com; s=arc-20160816; b=p7TgktnyEjc8NVYZ2uc9PlUAhbocMOGGfk2bkCOfrp/bW5sJ90QCDtzVHk5DOqFTRN vp25vThLodSR8TgqbDez5nDHrkHEuV3bkuQ7OY/6MCF2UXnvvgPuS5EjQiopF1hN0eIY gVwGlVDUeQGE0ppTKQ/8h/kjdGHAEL0TdsmWCrzfu3D3iegtVRqtNcHdhyo8rEjI5Lb4 xg9qGHH8iP+DdP1W3gVRDp0eERuqJ3WUyc5gtMpPDkzrJ0qYp2Gnpcg5/mRn6ksojcfi TkW9eOP6EubuSGoGsvuWovZUDZvbl4rk3ZsDMwOV46J6NaD+zL3Vcfa0zNx1dB70uGei kN4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tq7jyXCQ1MNbvNfmmtcieSqarVmMjHZsZF8RzV8rRW0=; fh=VZHXHo+vwBqT7vOg4dFYBUvOBDmtIVtwH9XG5mvsu+Q=; b=Jmepii6k9EqXXZFxzCLKWvIP7rW270Fg9mCJbWikysglr1F0ADvk9MYuYDd4ncYFKB SEHdVLdegsNm1jEKplr2RyvrruU46B7746qqh/cRGzfmCUhwMUD/tBq6z/M0HnUGjowt AG99tkjHZdmCwYhOZNrtsXphUuzuPiWROTNcleDjNG36Xy6+D0l9n3N2Vzi8E65+fKx9 MXHndAvvuYFytCrtbJDlprS+22xG9vWjqncqacAV2z7Tb0BjZGLJIjbNWRld9rq5x6Js ezTq8vJCKTrL/pNYgCcCTqqi0f1RKd+OPg/xBMNF57bntKZVypkW4JoH4+q+kbvkH4Kd omsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=E2Hspznz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id pb17-20020a17090b3c1100b00285874cccb7si3433932pjb.119.2023.12.01.02.41.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Dec 2023 02:41:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=E2Hspznz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 220B88083AE0; Fri, 1 Dec 2023 02:40:55 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378341AbjLAKkf (ORCPT + 99 others); Fri, 1 Dec 2023 05:40:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378327AbjLAKka (ORCPT ); Fri, 1 Dec 2023 05:40:30 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A6C1F4 for ; Fri, 1 Dec 2023 02:40:37 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id D36D2660739E; Fri, 1 Dec 2023 10:40:34 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1701427235; bh=UHGGjWyb9Jp3JfckcC+Y+MAj83qpLoBpUbGcBQKDZUc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E2HspznzDqvZveaKtQCiSgbNtBfMVi5xErnFeKQeQWsKSAcFYgQ7R5SOSX3QxSkDY y8WkRuiZ+oZLA2YRoeh2XpgT2Eho8+nCejD6C37b1+KnyOUVMWRXUhNROxOehZ9h6y Ezto/k+yNQqDVxNe8S6COFqRLXDBDhvJJX4kOah/jHPpjp5NgdO7qQU8vAb/8AI0sy F5v6eQeoBIewKj7CuNmNO4QdIJHjs2f+6FZHu/ZMFfcaWB7ESXxZ60cHmn29ohyAnn AGuluZZViuEzmc4zQx1X2lhLGz9HG59Q7Lf1bz0v/L2nkNMvnQBqzeDw3111D4vM5j LZEeWjlX0DWYw== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, kernel@collabora.com, m.szyprowski@samsung.com, krzysztof.kozlowski@linaro.org Subject: [PATCH v3 2/3] drm/panfrost: Add gpu_irq, mmu_irq to struct panfrost_device Date: Fri, 1 Dec 2023 11:40:26 +0100 Message-ID: <20231201104027.35273-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231201104027.35273-1-angelogioacchino.delregno@collabora.com> References: <20231201104027.35273-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Fri, 01 Dec 2023 02:40:55 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784075835896472950 X-GMAIL-MSGID: 1784075835896472950 In preparation for adding a IRQ synchronization mechanism for PM suspend add gpu_irq and mmu_irq variables to struct panfrost_device and change functions panfrost_gpu_init() and panfrost_mmu_init() to use those. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Boris Brezillon Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_device.h | 2 ++ drivers/gpu/drm/panfrost/panfrost_gpu.c | 10 +++++----- drivers/gpu/drm/panfrost/panfrost_mmu.c | 10 +++++----- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h index 0fc558db6bfd..54a8aad54259 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -94,6 +94,8 @@ struct panfrost_device { struct device *dev; struct drm_device *ddev; struct platform_device *pdev; + int gpu_irq; + int mmu_irq; void __iomem *iomem; struct clk *clock; diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c index bd41617c5e4b..7adc4441fa14 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -454,7 +454,7 @@ void panfrost_gpu_power_off(struct panfrost_device *pfdev) int panfrost_gpu_init(struct panfrost_device *pfdev) { - int err, irq; + int err; err = panfrost_gpu_soft_reset(pfdev); if (err) @@ -469,11 +469,11 @@ int panfrost_gpu_init(struct panfrost_device *pfdev) dma_set_max_seg_size(pfdev->dev, UINT_MAX); - irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu"); - if (irq < 0) - return irq; + pfdev->gpu_irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu"); + if (pfdev->gpu_irq < 0) + return pfdev->gpu_irq; - err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler, + err = devm_request_irq(pfdev->dev, pfdev->gpu_irq, panfrost_gpu_irq_handler, IRQF_SHARED, KBUILD_MODNAME "-gpu", pfdev); if (err) { dev_err(pfdev->dev, "failed to request gpu irq"); diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c index 846dd697c410..ac4296c1e54b 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -753,13 +753,13 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) int panfrost_mmu_init(struct panfrost_device *pfdev) { - int err, irq; + int err; - irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "mmu"); - if (irq < 0) - return irq; + pfdev->mmu_irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "mmu"); + if (pfdev->mmu_irq < 0) + return pfdev->mmu_irq; - err = devm_request_threaded_irq(pfdev->dev, irq, + err = devm_request_threaded_irq(pfdev->dev, pfdev->mmu_irq, panfrost_mmu_irq_handler, panfrost_mmu_irq_handler_thread, IRQF_SHARED, KBUILD_MODNAME "-mmu", From patchwork Fri Dec 1 10:40:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 172410 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp1024060vqy; Fri, 1 Dec 2023 02:41:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IEoTfaxLEGQZ8c3ZeRhvaf+M5qwH2wZGIlVWKoCjopF6knoBH1Pn+yKw0GMrbXLWJ/lflLu X-Received: by 2002:a05:6870:2013:b0:1fa:f094:5a03 with SMTP id o19-20020a056870201300b001faf0945a03mr1083281oab.12.1701427310900; Fri, 01 Dec 2023 02:41:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701427310; cv=none; d=google.com; s=arc-20160816; b=c1dY+tOoAhhHU1bvW//Ak9XZT81bEmNWr/TTqelhZaVBNJg9foQevgueAx82JFHgv9 ren/PjMcD+4nDANUm7S8zoWFDaC6cELravg87Z0XjD7a1iLDBVBvAVaRXUFsUyUibIQb 30p4L71TNnSoIystkn4HcNsfTo4GipaoZGsFs0Px+i9QioFaYF5dWTOO279LYwR5Pryl wqpKmkZk1ojfbf5jMoGoQr1xaJtbAbWOoE0hzGH0EM8QRIaPzAfslNgzrVPVsarOzylj eBJiXh7ZK/xtHJUpUahY+Ji9g1g6IgZzi8NyittVnjpHGJiGXsz32cpQzMNH/3blpo+J O8jA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dhm1GGlhKpiWQ+o6KniLenw8bjRuDSMMvOfcqDVHw+Q=; fh=VZHXHo+vwBqT7vOg4dFYBUvOBDmtIVtwH9XG5mvsu+Q=; b=ML37+VuRkWZtLqD8+w1WcGqNDfLVIgD9sf+6mLCzNlsYsk3WJ2l/fxO8YBIOUZaFIk DPgHcngud+zHt9KcUcO30ClI87WrckPR7SYm92Om4syqyL1OgmSkRGDC+DrwuOREQzyO Q4urPj77wB+zlYRybx0afZntg0rOBDQCJJ3h93/sbNKBZhJ1nwg9VzQLUMInYZxmSHhT bnveUesjhff8/g2H0VtRQFQIKBxiwzA0BcrhWixnI4GbnSuwVG7GW02GNxxxQMRCQeHV 2QKDsrabbAg3exKmsIgvJNw8f1KenJksOzOXvz7rPbAGZiyu6PbDDKE5OXfj4eF98y4W x8vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=CWDHP6b9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id m3-20020a632603000000b005644a9be955si3414104pgm.179.2023.12.01.02.41.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Dec 2023 02:41:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=CWDHP6b9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 14C6B8116796; Fri, 1 Dec 2023 02:40:55 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378339AbjLAKkh (ORCPT + 99 others); Fri, 1 Dec 2023 05:40:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378331AbjLAKkc (ORCPT ); Fri, 1 Dec 2023 05:40:32 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2DE3D196 for ; Fri, 1 Dec 2023 02:40:38 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0F27366073A1; Fri, 1 Dec 2023 10:40:36 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1701427237; bh=wOTpUlQBP0Wz+C7WaVT6lK/X5bsrLH5yCuWqUmWzM2k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CWDHP6b9nc60lfgaH0lqBRbkfJoUd3Jm1YNNYwMKzwTT70IZDn2Gu5dmwzyOd3s+U uHZwtsyMdu7dAamyvmoBL/IzZz3W24vGfnA2E+iQ9TOrD3+QUmMxYGZilZkh8CWay9 clOBIzE2FbSdt97Y0y0snl0UcBMIJbdoUlmkgifjRxy9H4iyUa//Ux2EfPj9DgcMxR 76aH4WPbyEmhox+DrKHkbGya7vIn072qQcGG/UNqrxBZneMEAtckP8384gZTEXsLiO wyDpPK9fpre2LgtAewhKq9VwQOoe6s2ptpCwLg1tOpHVl2UxKpHu1/QUSnGjz5NRov l/kMtDj7mOXWg== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, kernel@collabora.com, m.szyprowski@samsung.com, krzysztof.kozlowski@linaro.org Subject: [PATCH v3 3/3] drm/panfrost: Synchronize and disable interrupts before powering off Date: Fri, 1 Dec 2023 11:40:27 +0100 Message-ID: <20231201104027.35273-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231201104027.35273-1-angelogioacchino.delregno@collabora.com> References: <20231201104027.35273-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Fri, 01 Dec 2023 02:40:55 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784075844165694843 X-GMAIL-MSGID: 1784075844165694843 To make sure that we don't unintentionally perform any unclocked and/or unpowered R/W operation on GPU registers, before turning off clocks and regulators we must make sure that no GPU, JOB or MMU ISR execution is pending: doing that required to add a mechanism to synchronize the interrupts on suspend. Add functions panfrost_{gpu,job,mmu}_suspend_irq() which will perform interrupts masking and ISR execution synchronization, and then call those in the panfrost_device_runtime_suspend() handler in the exact sequence of job (may require mmu!) -> mmu -> gpu. As a side note, JOB and MMU suspend_irq functions needed some special treatment: as their interrupt handlers will unmask interrupts, it was necessary to add a bitmap for `is_suspended` which is used to address the possible corner case of unintentional IRQ unmasking because of ISR execution after a call to synchronize_irq(). At resume, clear each is_suspended bit in the reset path of JOB/MMU to allow unmasking the interrupts. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panfrost/panfrost_device.c | 3 +++ drivers/gpu/drm/panfrost/panfrost_device.h | 7 +++++++ drivers/gpu/drm/panfrost/panfrost_gpu.c | 6 ++++++ drivers/gpu/drm/panfrost/panfrost_gpu.h | 1 + drivers/gpu/drm/panfrost/panfrost_job.c | 20 +++++++++++++++++--- drivers/gpu/drm/panfrost/panfrost_job.h | 1 + drivers/gpu/drm/panfrost/panfrost_mmu.c | 19 ++++++++++++++++--- drivers/gpu/drm/panfrost/panfrost_mmu.h | 1 + 8 files changed, 52 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c index c90ad5ee34e7..a45e4addcc19 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -421,6 +421,9 @@ static int panfrost_device_runtime_suspend(struct device *dev) return -EBUSY; panfrost_devfreq_suspend(pfdev); + panfrost_job_suspend_irq(pfdev); + panfrost_mmu_suspend_irq(pfdev); + panfrost_gpu_suspend_irq(pfdev); panfrost_gpu_power_off(pfdev); return 0; diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h index 54a8aad54259..5c24f01f8904 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -25,6 +25,12 @@ struct panfrost_perfcnt; #define NUM_JOB_SLOTS 3 #define MAX_PM_DOMAINS 5 +enum panfrost_drv_comp_bits { + PANFROST_COMP_BIT_MMU, + PANFROST_COMP_BIT_JOB, + PANFROST_COMP_BIT_MAX +}; + /** * enum panfrost_gpu_pm - Supported kernel power management features * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend @@ -109,6 +115,7 @@ struct panfrost_device { struct panfrost_features features; const struct panfrost_compatible *comp; + DECLARE_BITMAP(is_suspended, PANFROST_COMP_BIT_MAX); spinlock_t as_lock; unsigned long as_in_use_mask; diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c index 7adc4441fa14..3a6a4fe7aca1 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -452,6 +452,12 @@ void panfrost_gpu_power_off(struct panfrost_device *pfdev) dev_err(pfdev->dev, "l2 power transition timeout"); } +void panfrost_gpu_suspend_irq(struct panfrost_device *pfdev) +{ + gpu_write(pfdev, GPU_INT_MASK, 0); + synchronize_irq(pfdev->gpu_irq); +} + int panfrost_gpu_init(struct panfrost_device *pfdev) { int err; diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.h b/drivers/gpu/drm/panfrost/panfrost_gpu.h index 876fdad9f721..d841b86504ea 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.h +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.h @@ -15,6 +15,7 @@ u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev); int panfrost_gpu_soft_reset(struct panfrost_device *pfdev); void panfrost_gpu_power_on(struct panfrost_device *pfdev); void panfrost_gpu_power_off(struct panfrost_device *pfdev); +void panfrost_gpu_suspend_irq(struct panfrost_device *pfdev); void panfrost_cycle_counter_get(struct panfrost_device *pfdev); void panfrost_cycle_counter_put(struct panfrost_device *pfdev); diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c index f9446e197428..7600e7741211 100644 --- a/drivers/gpu/drm/panfrost/panfrost_job.c +++ b/drivers/gpu/drm/panfrost/panfrost_job.c @@ -405,6 +405,8 @@ void panfrost_job_enable_interrupts(struct panfrost_device *pfdev) int j; u32 irq_mask = 0; + clear_bit(PANFROST_COMP_BIT_JOB, pfdev->is_suspended); + for (j = 0; j < NUM_JOB_SLOTS; j++) { irq_mask |= MK_JS_MASK(j); } @@ -413,6 +415,14 @@ void panfrost_job_enable_interrupts(struct panfrost_device *pfdev) job_write(pfdev, JOB_INT_MASK, irq_mask); } +void panfrost_job_suspend_irq(struct panfrost_device *pfdev) +{ + set_bit(PANFROST_COMP_BIT_JOB, pfdev->is_suspended); + + job_write(pfdev, JOB_INT_MASK, 0); + synchronize_irq(pfdev->js->irq); +} + static void panfrost_job_handle_err(struct panfrost_device *pfdev, struct panfrost_job *job, unsigned int js) @@ -792,9 +802,13 @@ static irqreturn_t panfrost_job_irq_handler_thread(int irq, void *data) struct panfrost_device *pfdev = data; panfrost_job_handle_irqs(pfdev); - job_write(pfdev, JOB_INT_MASK, - GENMASK(16 + NUM_JOB_SLOTS - 1, 16) | - GENMASK(NUM_JOB_SLOTS - 1, 0)); + + /* Enable interrupts only if we're not about to get suspended */ + if (!test_bit(PANFROST_COMP_BIT_JOB, pfdev->is_suspended)) + job_write(pfdev, JOB_INT_MASK, + GENMASK(16 + NUM_JOB_SLOTS - 1, 16) | + GENMASK(NUM_JOB_SLOTS - 1, 0)); + return IRQ_HANDLED; } diff --git a/drivers/gpu/drm/panfrost/panfrost_job.h b/drivers/gpu/drm/panfrost/panfrost_job.h index 17ff808dba07..ec581b97852b 100644 --- a/drivers/gpu/drm/panfrost/panfrost_job.h +++ b/drivers/gpu/drm/panfrost/panfrost_job.h @@ -47,6 +47,7 @@ int panfrost_job_get_slot(struct panfrost_job *job); int panfrost_job_push(struct panfrost_job *job); void panfrost_job_put(struct panfrost_job *job); void panfrost_job_enable_interrupts(struct panfrost_device *pfdev); +void panfrost_job_suspend_irq(struct panfrost_device *pfdev); int panfrost_job_is_idle(struct panfrost_device *pfdev); #endif diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c index ac4296c1e54b..d79d41fe22fe 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -231,6 +231,8 @@ void panfrost_mmu_reset(struct panfrost_device *pfdev) { struct panfrost_mmu *mmu, *mmu_tmp; + clear_bit(PANFROST_COMP_BIT_MMU, pfdev->is_suspended); + spin_lock(&pfdev->as_lock); pfdev->as_alloc_mask = 0; @@ -744,9 +746,12 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) status = mmu_read(pfdev, MMU_INT_RAWSTAT) & ~pfdev->as_faulty_mask; } - spin_lock(&pfdev->as_lock); - mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask); - spin_unlock(&pfdev->as_lock); + /* Enable interrupts only if we're not about to get suspended */ + if (!test_bit(PANFROST_COMP_BIT_MMU, pfdev->is_suspended)) { + spin_lock(&pfdev->as_lock); + mmu_write(pfdev, MMU_INT_MASK, ~pfdev->as_faulty_mask); + spin_unlock(&pfdev->as_lock); + } return IRQ_HANDLED; }; @@ -777,3 +782,11 @@ void panfrost_mmu_fini(struct panfrost_device *pfdev) { mmu_write(pfdev, MMU_INT_MASK, 0); } + +void panfrost_mmu_suspend_irq(struct panfrost_device *pfdev) +{ + set_bit(PANFROST_COMP_BIT_MMU, pfdev->is_suspended); + + mmu_write(pfdev, MMU_INT_MASK, 0); + synchronize_irq(pfdev->mmu_irq); +} diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.h b/drivers/gpu/drm/panfrost/panfrost_mmu.h index cc2a0d307feb..022a9a74a114 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.h +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.h @@ -14,6 +14,7 @@ void panfrost_mmu_unmap(struct panfrost_gem_mapping *mapping); int panfrost_mmu_init(struct panfrost_device *pfdev); void panfrost_mmu_fini(struct panfrost_device *pfdev); void panfrost_mmu_reset(struct panfrost_device *pfdev); +void panfrost_mmu_suspend_irq(struct panfrost_device *pfdev); u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu); void panfrost_mmu_as_put(struct panfrost_device *pfdev, struct panfrost_mmu *mmu);