From patchwork Thu Nov 10 11:16:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 18076 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp82320wru; Thu, 10 Nov 2022 03:18:02 -0800 (PST) X-Google-Smtp-Source: AMsMyM7IdBy88/7rdq3BQ+0BwA6ZxR/7BpL2cqsYPLoeBSrSQ5WgUGnfi0AzmU4Y0H3RHteyyvEn X-Received: by 2002:a17:907:983:b0:77b:6e40:8435 with SMTP id bf3-20020a170907098300b0077b6e408435mr56366005ejc.570.1668079081866; Thu, 10 Nov 2022 03:18:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668079081; cv=none; d=google.com; s=arc-20160816; b=G9LCDAVu64mAwkxpbYame8E1TcqcqZ7fi+KZS+vB8paqCnLITUTqiKGJYAg++Y2UpO sRegujrrCi4gQQSTiXZ6t264kkzX2BnZuE2hXsczZtK42S0GF1SZC42cayUfKUT1yTGV RkYMWcWyzrXKGb6klZinas2uY4UawOEcqCYtaZ3kDVmuk3pf/dfql+pWlc4w912ttKVu xCiVlvJX8LeLmbTx/oHNb7DZblmJ7KFlIirrx4G/i/oHOupqluY9FNUz7qTK7VAH2BMc qJk4473I/TcWtmTvJXapOAN977YZdqaOHaPROs1VHOh4LxqmlgEWElU7zWnFNCTHT4fm 80mQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence:subject:cc:to :content-language:user-agent:mime-version:date:message-id :dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=To3VR1vROvsl/bCnvrDtNgbj5S8TteyMmq42T9MwrLk=; b=Cw+fJ+dWLeHodX0X1m5LlSplnqt29zcmW1JMb/BGPpmyS2h9BOznv+pGTPowWefbDw Xi/M3/gEchs8+psNj7rj4PFONKbpZMu6ULMPOK7R/eAlx3P7jO+v09RgCk2aofGE02Rn nYHlL103VvVEELt8Iftou4yYY509xABVTGcSsdgKpnprKdhIEWXyNAM8AS+mKOQzNYbH piKzXDrFL1bIX06UkKdQ4earklCMqHHx/MHgcrm8UVut/QxKhjaoBRPyCJGoaMbvDOWa YAfBzaA0IKBq+uLDn7QHvVsGf/YEAJ/sc4IGP1nXRrNpIOj4zuwAG2Fulnpg2QLVhawk MBUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=H+tC+jHP; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id b26-20020a170906151a00b007ae1874c142si13320470ejd.446.2022.11.10.03.18.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 03:18:01 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=H+tC+jHP; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 68DA538438AB for ; Thu, 10 Nov 2022 11:17:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 68DA538438AB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668079071; bh=To3VR1vROvsl/bCnvrDtNgbj5S8TteyMmq42T9MwrLk=; h=Date:To:Cc:Subject:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=H+tC+jHPaL1SEyij6VITH9COZTjVZCqEsrf6A9VW421C21DAKfWh2BXwRThPmzp5b KDF13LUbEjIFy+XJPujtt3OdtPmhw/4K8mzriHKt/GFUiC6Rt92rh4s8aXvQqz6YJz b1veaHEWaOL10LhLxKtTAXttijjGTukxCQRtIKA4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 200723858D3C for ; Thu, 10 Nov 2022 11:17:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 200723858D3C Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A6A01FB; Thu, 10 Nov 2022 03:17:08 -0800 (PST) Received: from [10.57.4.81] (unknown [10.57.4.81]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A13383F534; Thu, 10 Nov 2022 03:17:01 -0800 (PST) Message-ID: Date: Thu, 10 Nov 2022 11:16:55 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Cc: Kyrylo Tkachov , Richard Earnshaw , Richard Sandiford Subject: [PATCH 1/2] aarch64: Enable the use of LDAPR for load-acquire semantics X-Spam-Status: No, score=-16.5 required=5.0 tests=BAYES_00, BODY_8BITS, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Andre Vieira \(lists\) via Gcc-patches" From: "Andre Vieira (lists)" Reply-To: "Andre Vieira \(lists\)" Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749107691008016699?= X-GMAIL-MSGID: =?utf-8?q?1749107691008016699?= Hello, This patch enables the use of LDAPR for load-acquire semantics. After some internal investigation based on the work published by Podkopaev et al. (https://dl.acm.org/doi/10.1145/3290382) we can confirm that using LDAPR for the C++ load-acquire semantics is a correct relaxation. Bootstrapped and regression tested on aarch64-none-linux-gnu. OK for trunk? 2022-11-09  Andre Vieira              Kyrylo Tkachov  gcc/ChangeLog:         * config/aarch64/aarch64.h (AARCH64_ISA_RCPC): New Macro.         (TARGET_RCPC): New Macro.         * config/aarch64/atomics.md (atomic_load): Change into         an expand.         (aarch64_atomic_load_rcpc): New define_insn for ldapr.         (aarch64_atomic_load): Rename of old define_insn for ldar.         * config/aarch64/iterators.md (UNSPEC_LDAP): New unspec enum value.         * doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst         (rcpc): Ammend documentation to mention the effects on code generation. gcc/testsuite/ChangeLog:         * gcc.target/aarch64/ldapr.c: New test.         * lib/target-supports.exp (add_options_for_aarch64_rcpc): New options procedure.         (check_effective_target_aarch64_rcpc_ok_nocache): New check-effective-target.         (check_effective_target_aarch64_rcpc_ok): Likewise. diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index e60f9bce023b2cd5e7233ee9b8c61fc93c1494c2..51a8aa02a5850d5c79255dbf7e0764ffdec73ccd 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -221,6 +221,7 @@ enum class aarch64_feature : unsigned char { #define AARCH64_ISA_V9_3A (aarch64_isa_flags & AARCH64_FL_V9_3A) #define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS) #define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64) +#define AARCH64_ISA_RCPC (aarch64_isa_flags & AARCH64_FL_RCPC) /* Crypto is an optional extension to AdvSIMD. */ #define TARGET_CRYPTO (AARCH64_ISA_CRYPTO) @@ -328,6 +329,9 @@ enum class aarch64_feature : unsigned char { /* SB instruction is enabled through +sb. */ #define TARGET_SB (AARCH64_ISA_SB) +/* RCPC loads from Armv8.3-a. */ +#define TARGET_RCPC (AARCH64_ISA_RCPC) + /* Apply the workaround for Cortex-A53 erratum 835769. */ #define TARGET_FIX_ERR_A53_835769 \ ((aarch64_fix_a53_err835769 == 2) \ diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index bc95f6d9d15f190a3e33704b4def2860d5f339bd..801a62bf2ba432f35ae1931beb8c4405b77b36c3 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -657,7 +657,42 @@ } ) -(define_insn "atomic_load" +(define_expand "atomic_load" + [(match_operand:ALLI 0 "register_operand" "=r") + (match_operand:ALLI 1 "aarch64_sync_memory_operand" "Q") + (match_operand:SI 2 "const_int_operand")] + "" + { + /* If TARGET_RCPC and this is an ACQUIRE load, then expand to a pattern + using UNSPECV_LDAP. */ + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + if (TARGET_RCPC + && (is_mm_acquire (model) + || is_mm_acq_rel (model))) + { + emit_insn (gen_aarch64_atomic_load_rcpc (operands[0], operands[1], + operands[2])); + } + else + { + emit_insn (gen_aarch64_atomic_load (operands[0], operands[1], + operands[2])); + } + DONE; + } +) + +(define_insn "aarch64_atomic_load_rcpc" + [(set (match_operand:ALLI 0 "register_operand" "=r") + (unspec_volatile:ALLI + [(match_operand:ALLI 1 "aarch64_sync_memory_operand" "Q") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_LDAP))] + "TARGET_RCPC" + "ldapr\t%0, %1" +) + +(define_insn "aarch64_atomic_load" [(set (match_operand:ALLI 0 "register_operand" "=r") (unspec_volatile:ALLI [(match_operand:ALLI 1 "aarch64_sync_memory_operand" "Q") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index a8ad4e5ff215ade06c3ca13a24ef18d259afcb6c..d8c2f9d6c32d6f188d584c2e9d8fb36511624de6 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -988,6 +988,7 @@ UNSPECV_LX ; Represent a load-exclusive. UNSPECV_SX ; Represent a store-exclusive. UNSPECV_LDA ; Represent an atomic load or load-acquire. + UNSPECV_LDAP ; Represent an atomic acquire load with RCpc semantics. UNSPECV_STL ; Represent an atomic store or store-release. UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap. UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange. diff --git a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst index c2b23a6ee97ef2b7c74119f22c1d3e3d85385f4d..25d609238db7d45845dbc446ac21d12dddcf8eac 100644 --- a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst +++ b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst @@ -437,9 +437,9 @@ the following and their inverses no :samp:`{feature}` : floating-point instructions. This option is enabled by default for :option:`-march=armv8.4-a`. Use of this option with architectures prior to Armv8.2-A is not supported. :samp:`rcpc` - Enable the RcPc extension. This does not change code generation from GCC, - but is passed on to the assembler, enabling inline asm statements to use - instructions from the RcPc extension. + Enable the RcPc extension. This enables the use of the LDAPR instructions for + load-acquire atomic semantics, and passes it on to the assembler, enabling + inline asm statements to use instructions from the RcPc extension. :samp:`dotprod` Enable the Dot Product extension. This also enables Advanced SIMD instructions. diff --git a/gcc/testsuite/gcc.target/aarch64/ldapr.c b/gcc/testsuite/gcc.target/aarch64/ldapr.c new file mode 100644 index 0000000000000000000000000000000000000000..c36edfcd79a9ee41434ab09ac47d257a692a8606 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldapr.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -std=c99" } */ +/* { dg-require-effective-target aarch64_rcpc_ok } */ +/* { dg-add-options aarch64_rcpc } */ +#include + +atomic_ullong u64; +atomic_llong s64; +atomic_uint u32; +atomic_int s32; +atomic_ushort u16; +atomic_short s16; +atomic_uchar u8; +atomic_schar s8; + +#define TEST(size, rettype) \ +rettype \ +test_##size (void) \ +{ \ + return atomic_load_explicit (&size, memory_order_acquire); \ +} \ + +TEST(u64, unsigned long long) +TEST(s64, long long) +TEST(u32, unsigned int) +TEST(s32, int) +TEST(u16, unsigned short) +TEST(s16, short) +TEST(u8, unsigned char) +TEST(s8, signed char) + +/* { dg-final { scan-assembler-times "ldapr\tx" 2 } } */ +/* { dg-final { scan-assembler-times "ldapr\tw" 2 } } */ +/* { dg-final { scan-assembler-times "ldaprh\tw" 2 } } */ +/* { dg-final { scan-assembler-times "ldaprb\tw" 2 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index c7f583d6d1498401a7c106ed3f539dcd04f95451..262665a78dfb58f1e63b629829c5112789b7abd9 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -11819,6 +11819,42 @@ proc check_effective_target_glibc { } { }] } +proc add_options_for_aarch64_rcpc { flags } { + if { ! [check_effective_target_aarch64_rcpc_ok] } { + return "$flags" + } + global et_aarch64_rcpc_flags + return "$flags $et_aarch64_rcpc_flags" +} + +# Return 1 if the toolchain supports the RCPC extension. +proc check_effective_target_aarch64_rcpc_ok_nocache { } { + global et_aarch64_rcpc_flags + set et_aarch64_rcpc_flags "" + if { ![istarget aarch64*-*-*] } { + return 0 + } + + foreach flags {"" "-march=armv8.2-a+rcpc"} { + if { [check_no_compiler_messages_nocache aarch64_rcpc_ok object { + int main (void) { + asm volatile ("ldapr x0, [x0]":::"memory"); + return 0; + } + } $flags ] } { + set et_aarch64_rcpc_flags $flags + return 1 + } + } + return 0 +} + +proc check_effective_target_aarch64_rcpc_ok { } { + return [check_cached_effective_target aarch64_rcpc_ok \ + check_effective_target_aarch64_rcpc_ok_nocache] +} + + # Return 1 if the target plus current options supports a vector # complex addition with rotate of half and single float modes, 0 otherwise. # From patchwork Thu Nov 10 11:20:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 18077 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp83527wru; Thu, 10 Nov 2022 03:20:56 -0800 (PST) X-Google-Smtp-Source: AMsMyM6JQmfA2/dN34haD24+XD2KfBGEL4otS5ektd86gWHbDZs+42jcAYI/X6aQ2KQO4AOXMe14 X-Received: by 2002:a05:6402:b67:b0:464:1296:d5d4 with SMTP id cb7-20020a0564020b6700b004641296d5d4mr1842830edb.83.1668079256756; Thu, 10 Nov 2022 03:20:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668079256; cv=none; d=google.com; s=arc-20160816; b=PBLjSfOWSUuFBheY+hY9BXTW4tuCnBCKqcQvvHIpAs46/4/ZDw3T5ZoewK9VsQS7m1 eu5iexSit5nFy8lawfpUX681KW7XaRQQL8WR0u7+PD8H+zGrdpAMAIjfxpfeQEz309i6 Nrh2qjlR2Vr2M7H+QAzmt7jQTaJoU3Q0XQLdHTnn251IvDgH/ycfXa0Di2N7hKHb8BFj +JUAkyK3Ip6RI29wp7UJ7sjdZ18q3dnI4jJSeHu/pKaFfFpP05lbyZE0Z89NV4e2R4tn 2+fk5310p8ZDRzNLw1QD0pjVmB67rp3MnsFDZz9JX6wB4fGr55Zk4T2dY5yx73G2O1gZ wBig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence:in-reply-to :references:cc:to:content-language:subject:user-agent:mime-version :date:message-id:dmarc-filter:delivered-to:dkim-signature :dkim-filter; bh=Itxr0i/22m7afyvxb8nIOVKnxTyxf/gGFvAldHLkaY0=; b=tx9J9NkN8GzBu4WtqhnxRmf3qmO6oNAwuH/MjwTYL4m2APMb7YH/VGRk2h8n9vP7EA Ow5B6XfqMlfFjtFj0+zy2UCJbWt1oiBXP5O2tQ63BwjNiyH28W/n3wwtLRU/IWLKGlQH ZOZKlFP2y3BzzBgfhj0PpqK6TndW5KSTGZQM2X+Yvv0goYyPmaJUzb5vkmfRftY8ek2O q5oQCnjPWqpNXnhs+qpwu45C43oIsCeenQHzGd0aDD33BBqI1FLd//FkjOHLrqanNYxO GzrC/Vih86dkI9H2bYEvyRYFegD84/bfcPYrIBh0W/t397/pA+qwzJISk9hMGi19xT5h QEpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Ubc7ri1W; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id j11-20020aa7c40b000000b00459f9c3d02bsi15569764edq.22.2022.11.10.03.20.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 03:20:56 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Ubc7ri1W; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6B6143857C51 for ; Thu, 10 Nov 2022 11:20:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6B6143857C51 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668079255; bh=Itxr0i/22m7afyvxb8nIOVKnxTyxf/gGFvAldHLkaY0=; h=Date:Subject:To:Cc:References:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=Ubc7ri1W4aeAZsERMA0wWfH++LimbvHt5XV7K/AMjsevQ+640WlHwojQok0ZChpmH 7VlhXX8Eb8cbfO/QP5X78Zrpk07FgDuYKq6xdtwXTwvXaZhvkuoBnPbru0CFaMOha8 t8SDBgMuKPPedvR4QOSQE5LUBm0Yws8/gM69d7/w= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 3FD853858D20 for ; Thu, 10 Nov 2022 11:20:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3FD853858D20 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1F7581FB; Thu, 10 Nov 2022 03:20:14 -0800 (PST) Received: from [10.57.4.81] (unknown [10.57.4.81]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3D9C93F534; Thu, 10 Nov 2022 03:20:07 -0800 (PST) Message-ID: Date: Thu, 10 Nov 2022 11:20:01 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: [PATCH 2/2] aarch64: Add support for widening LDAPR instructions Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Cc: Kyrylo Tkachov , Richard Earnshaw , Richard Sandiford References: In-Reply-To: X-Spam-Status: No, score=-16.6 required=5.0 tests=BAYES_00, BODY_8BITS, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Andre Vieira \(lists\) via Gcc-patches" From: "Andre Vieira (lists)" Reply-To: "Andre Vieira \(lists\)" Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749107874752755981?= X-GMAIL-MSGID: =?utf-8?q?1749107874752755981?= Hi, This patch adds support for the widening LDAPR instructions. Bootstrapped and regression tested on aarch64-none-linux-gnu. OK for trunk? 2022-11-09  Andre Vieira              Kyrylo Tkachov  gcc/ChangeLog:         * config/aarch64/atomics.md (*aarch64_atomic_load_rcpc_zext): New pattern.         (*aarch64_atomic_load_rcpc_zext): Likewise. gcc/testsuite/ChangeLog:         * gcc.target/aarch64/ldapr-ext.c: New test. diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index 9a9a30945c6e482a81a1bf446fe05d5efc462d32..77e5b29ad2c41215aa1ca904efb990b087010cef 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -691,6 +691,28 @@ } ) +(define_insn "*aarch64_atomic_load_rcpc_zext" + [(set (match_operand:GPI 0 "register_operand" "=r") + (zero_extend:GPI + (unspec_volatile:ALLX + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_LDAP)))] + "TARGET_RCPC" + "ldapr\t%0, %1" +) + +(define_insn "*aarch64_atomic_load_rcpc_sext" + [(set (match_operand:GPI 0 "register_operand" "=r") + (sign_extend:GPI + (unspec_volatile:ALLX + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_LDAP)))] + "TARGET_RCPC" + "ldaprs\t%0, %1" +) + (define_insn "atomic_store" [(set (match_operand:ALLI 0 "aarch64_rcpc_memory_operand" "=Q,Ust") (unspec_volatile:ALLI diff --git a/gcc/testsuite/gcc.target/aarch64/ldapr-ext.c b/gcc/testsuite/gcc.target/aarch64/ldapr-ext.c new file mode 100644 index 0000000000000000000000000000000000000000..5a788ffb8787291d43fe200d1d7803b901186912 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldapr-ext.c @@ -0,0 +1,94 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -std=c99" } */ +/* { dg-require-effective-target aarch64_rcpc_ok } */ +/* { dg-add-options aarch64_rcpc } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ +#include + +atomic_ullong u64; +atomic_llong s64; +atomic_uint u32; +atomic_int s32; +atomic_ushort u16; +atomic_short s16; +atomic_uchar u8; +atomic_schar s8; + +#define TEST(name, ldsize, rettype) \ +rettype \ +test_##name (void) \ +{ \ + return atomic_load_explicit (&ldsize, memory_order_acquire); \ +} + +/* +**test_u8_u64: +**... +** ldaprb x0, \[x[0-9]+\] +** ret +*/ + +TEST(u8_u64, u8, unsigned long long) + +/* +**test_s8_s64: +**... +** ldaprsb x0, \[x[0-9]+\] +** ret +*/ + +TEST(s8_s64, s8, long long) + +/* +**test_u16_u64: +**... +** ldaprh x0, \[x[0-9]+\] +** ret +*/ + +TEST(u16_u64, u16, unsigned long long) + +/* +**test_s16_s64: +**... +** ldaprsh x0, \[x[0-9]+\] +** ret +*/ + +TEST(s16_s64, s16, long long) + +/* +**test_u8_u32: +**... +** ldaprb w0, \[x[0-9]+\] +** ret +*/ + +TEST(u8_u32, u8, unsigned) + +/* +**test_s8_s32: +**... +** ldaprsb w0, \[x[0-9]+\] +** ret +*/ + +TEST(s8_s32, s8, int) + +/* +**test_u16_u32: +**... +** ldaprh w0, \[x[0-9]+\] +** ret +*/ + +TEST(u16_u32, u16, unsigned) + +/* +**test_s16_s32: +**... +** ldaprsh w0, \[x[0-9]+\] +** ret +*/ + +TEST(s16_s32, s16, int)