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server2.sourceware.org Received: from loongson.cn (unknown [10.2.6.5]) by gateway (Coremail) with SMTP id _____8AxJuhdbmhlH+c9AA--.64503S3; Thu, 30 Nov 2023 19:13:33 +0800 (CST) Received: from 5.5.5 (unknown [10.2.6.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bx3y9abmhlt7VQAA--.48055S3; Thu, 30 Nov 2023 19:13:32 +0800 (CST) From: mengqinggang To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, liuzhensong@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, maskray@google.com, cailulu@loongson.cn, luweining@loongson.cn, wanglei@loongson.cn, hejinyang@loongson.cn, mengqinggang Subject: [PATCH v1 1/2] LoongArch: Add new relocation R_LARCH_CALL36 Date: Thu, 30 Nov 2023 19:13:27 +0800 Message-Id: <20231130111328.3236602-2-mengqinggang@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231130111328.3236602-1-mengqinggang@loongson.cn> References: <20231130111328.3236602-1-mengqinggang@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bx3y9abmhlt7VQAA--.48055S3 X-CM-SenderInfo: 5phqw15lqjwttqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBj93XoWxtF4xtFW5Kr47tF4kXr18JFc_yoWfCw4rpw nxZw1YkF48CFnrWF9xKry5ZFs8Ww4xGrW2vaySq3WS9r4DJryUXF4ktrW3ZF45Jw4jqr4I qF1Fqw1UZF48J3cCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07UMpBfUUUUU= X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783987253284096576 X-GMAIL-MSGID: 1783987253284096576 R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and these two instructions must adjacent. The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs. --- bfd/bfd-in2.h | 1 + bfd/elfnn-loongarch.c | 19 ++++++++++----- bfd/elfxx-loongarch.c | 24 +++++++++++++++++++ bfd/libbfd.h | 1 + bfd/reloc.c | 3 +++ gas/config/tc-loongarch.c | 6 ++++- gas/testsuite/gas/loongarch/medium-call.d | 15 ++++++++++++ gas/testsuite/gas/loongarch/medium-call.s | 6 +++++ include/elf/loongarch.h | 2 ++ .../ld-loongarch-elf/ld-loongarch-elf.exp | 12 ++++++++++ ld/testsuite/ld-loongarch-elf/medium-call.s | 7 ++++++ 11 files changed, 89 insertions(+), 7 deletions(-) create mode 100644 gas/testsuite/gas/loongarch/medium-call.d create mode 100644 gas/testsuite/gas/loongarch/medium-call.s create mode 100644 ld/testsuite/ld-loongarch-elf/medium-call.s diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 040d5560cdf..73459a689ae 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -7460,6 +7460,7 @@ enum bfd_reloc_code_real BFD_RELOC_LARCH_ADD_ULEB128, BFD_RELOC_LARCH_SUB_ULEB128, BFD_RELOC_LARCH_64_PCREL, + BFD_RELOC_LARCH_CALL36, BFD_RELOC_UNUSED }; typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c index 024c5d4cd96..aa88ee8f928 100644 --- a/bfd/elfnn-loongarch.c +++ b/bfd/elfnn-loongarch.c @@ -780,6 +780,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, case R_LARCH_B16: case R_LARCH_B21: case R_LARCH_B26: + case R_LARCH_CALL36: if (h != NULL) { h->needs_plt = 1; @@ -1884,20 +1885,24 @@ loongarch_check_offset (const Elf_Internal_Rela *rel, ret; \ }) +/* Write immediate to instructions. */ + static bfd_reloc_status_type loongarch_reloc_rewrite_imm_insn (const Elf_Internal_Rela *rel, const asection *input_section ATTRIBUTE_UNUSED, reloc_howto_type *howto, bfd *input_bfd, bfd_byte *contents, bfd_vma reloc_val) { - int bits = bfd_get_reloc_size (howto) * 8; - uint32_t insn = bfd_get (bits, input_bfd, contents + rel->r_offset); - + /* Adjust the immediate based on alignment and + its position in the instruction. */ if (!loongarch_adjust_reloc_bitsfield (input_bfd, howto, &reloc_val)) return bfd_reloc_overflow; - insn = (insn & (uint32_t)howto->src_mask) - | ((insn & (~(uint32_t)howto->dst_mask)) | reloc_val); + int bits = bfd_get_reloc_size (howto) * 8; + uint64_t insn = bfd_get (bits, input_bfd, contents + rel->r_offset); + + /* Write immediate to instruction. */ + insn = (insn & ~howto->dst_mask) | (reloc_val & howto->dst_mask); bfd_put (bits, input_bfd, insn, contents + rel->r_offset); @@ -2120,6 +2125,7 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, case R_LARCH_TLS_GD_PC_HI20: case R_LARCH_TLS_GD_HI20: case R_LARCH_PCREL20_S2: + case R_LARCH_CALL36: r = loongarch_check_offset (rel, input_section); if (r != bfd_reloc_ok) break; @@ -3127,9 +3133,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, break; /* New reloc types. */ + case R_LARCH_B16: case R_LARCH_B21: case R_LARCH_B26: - case R_LARCH_B16: + case R_LARCH_CALL36: unresolved_reloc = false; if (is_undefweak) { diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c index 7f298c08fd3..d93b79043ce 100644 --- a/bfd/elfxx-loongarch.c +++ b/bfd/elfxx-loongarch.c @@ -1547,6 +1547,24 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = NULL, /* adjust_reloc_bits */ NULL), /* larch_reloc_type_name */ + /* Used for medium code model function call pcaddu18i+jirl, + these two instructions must adjacent. */ + LOONGARCH_HOWTO (R_LARCH_CALL36, /* type (110). */ + 2, /* rightshift. */ + 8, /* size. */ + 36, /* bitsize. */ + true, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_LARCH_CALL36", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0x03fffc0001ffffe0, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_CALL36, /* bfd_reloc_code_real_type. */ + reloc_sign_bits, /* adjust_reloc_bits. */ + "call36"), /* larch_reloc_type_name. */ }; reloc_howto_type * @@ -1726,6 +1744,12 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) /* Perform insn bits field. 15:0<<10, 20:16>>16. */ val = ((val & 0xffff) << 10) | ((val >> 16) & 0x1f); break; + case R_LARCH_CALL36: + /* 0x8000: If low 16-bit immediate greater than 0x7fff, + it become to a negative number due to sign-extended, + so the high part need to add 0x8000. */ + val = (((val + 0x8000) >> 16) << 5) | (((val & 0xffff) << 10) << 32); + break; default: val <<= howto->bitpos; break; diff --git a/bfd/libbfd.h b/bfd/libbfd.h index cc432677a81..399b1f688bb 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -3599,6 +3599,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_LARCH_ADD_ULEB128", "BFD_RELOC_LARCH_SUB_ULEB128", "BFD_RELOC_LARCH_64_PCREL", + "BFD_RELOC_LARCH_CALL36", "@@overflow: BFD_RELOC_UNUSED@@", }; #endif diff --git a/bfd/reloc.c b/bfd/reloc.c index 93ebad879e0..4d3ac4c1096 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -8292,6 +8292,9 @@ ENUMX ENUMX BFD_RELOC_LARCH_64_PCREL +ENUMX + BFD_RELOC_LARCH_CALL36 + ENUMDOC LARCH relocations. diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c index 59232832cf7..367a0b6c5a4 100644 --- a/gas/config/tc-loongarch.c +++ b/gas/config/tc-loongarch.c @@ -682,7 +682,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, esc_ch1, esc_ch2, bit_field, arg); if (ip->reloc_info[0].type >= BFD_RELOC_LARCH_B16 - && ip->reloc_info[0].type < BFD_RELOC_LARCH_64_PCREL) + && ip->reloc_info[0].type < BFD_RELOC_UNUSED) { /* As we compact stack-relocs, it is no need for pop operation. But break out until here in order to check the imm field. @@ -956,6 +956,10 @@ move_insn (struct loongarch_cl_insn *insn, fragS *frag, long where) static void append_fixed_insn (struct loongarch_cl_insn *insn) { + /* Ensure the jirl is emitted to the same frag as the pcaddu18i. */ + if (BFD_RELOC_LARCH_CALL36 == insn->reloc_info[0].type) + frag_grow (8); + char *f = frag_more (insn->insn_length); move_insn (insn, frag_now, f - frag_now->fr_literal); } diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/gas/loongarch/medium-call.d new file mode 100644 index 00000000000..4183818cb4f --- /dev/null +++ b/gas/testsuite/gas/loongarch/medium-call.d @@ -0,0 +1,15 @@ +#as: +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +.* <.text>: +[ ]+0:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0 +[ ]+0: R_LARCH_CALL36[ ]+a +[ ]+4:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 +[ ]+8:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0 +[ ]+8: R_LARCH_CALL36[ ]+a +[ ]+c:[ ]+4c000180[ ]+jr[ ]+\$t0 diff --git a/gas/testsuite/gas/loongarch/medium-call.s b/gas/testsuite/gas/loongarch/medium-call.s new file mode 100644 index 00000000000..f2977d1c6d7 --- /dev/null +++ b/gas/testsuite/gas/loongarch/medium-call.s @@ -0,0 +1,6 @@ + # call .L1, r1(ra) temp register, r1(ra) return register. + pcaddu18i $r1, %call36(a) + jirl $r1, $r1, 0 + # tail .L1, r12(t0) temp register, r0(zero) return register. + pcaddu18i $r12, %call36(a) + jirl $r0, $r12, 0 diff --git a/include/elf/loongarch.h b/include/elf/loongarch.h index e31395e13d5..34719ee8b8c 100644 --- a/include/elf/loongarch.h +++ b/include/elf/loongarch.h @@ -251,6 +251,8 @@ RELOC_NUMBER (R_LARCH_SUB_ULEB128, 108) RELOC_NUMBER (R_LARCH_64_PCREL, 109) +RELOC_NUMBER (R_LARCH_CALL36, 110) + END_RELOC_NUMBERS (R_LARCH_count) /* Processor specific flags for the ELF header e_flags field. */ diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp index b95cc53e597..1fc70d0a61e 100644 --- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp @@ -55,4 +55,16 @@ if [istarget "loongarch64-*-*"] { "64_pcrel" \ ] \ ] + + run_ld_link_tests \ + [list \ + [list \ + "medium code model call" \ + "-e 0x0" "" \ + "" \ + {medium-call.s} \ + {} \ + "medium-call" \ + ] \ + ] } diff --git a/ld/testsuite/ld-loongarch-elf/medium-call.s b/ld/testsuite/ld-loongarch-elf/medium-call.s new file mode 100644 index 00000000000..4d1888b76a0 --- /dev/null +++ b/ld/testsuite/ld-loongarch-elf/medium-call.s @@ -0,0 +1,7 @@ +.L1: + # call .L1, r1(ra) temp register, r1(ra) return register. + pcaddu18i $r1, %call36(.L1) + jirl $r1, $r1, 0 + # tail .L1, r12(t0) temp register, r0(zero) return register. + pcaddu18i $r12, %call36(.L1) + jirl $r0, $r12, 0 From patchwork Thu Nov 30 11:13:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: mengqinggang X-Patchwork-Id: 171831 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp306121vqy; Thu, 30 Nov 2023 03:13:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IH1y5e3MPlCfFROSH35VPSUZxOkqDkHKxXVexLM75TOwIMIXwz3zyipkRrGn6oD8foFw27Q X-Received: by 2002:ad4:504e:0:b0:67a:1f8c:9157 with SMTP id m14-20020ad4504e000000b0067a1f8c9157mr20405202qvq.17.1701342829739; Thu, 30 Nov 2023 03:13:49 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1701342829; cv=pass; d=google.com; s=arc-20160816; b=xFllgLheTxrUNJj3RkNoI167WETSELRQMeovloTiwGzxtgNGNC60luoEG6jdl8o/i+ evjlCCxHFmLSAcuVDC1si25M530bd9WjlMCVuIVx/17WeIFNU57WEZXEh8Mo+MNAzENi snAOXcgMu2JB8tBJHp1WEQh+KDUhYlsmjwgGrOCHzQtusDJSdZLG8CoT5EORpQH284nL hunV4oCMGebULZj+IuFYEOG68vyAUNI7wnhuVUd98JtH4wc5BfDD1JqM0sUQLRtZtsly i/SuGFq7jZR/2+bfZxdbfVjC+zDP2WGrPdztwZ3r85lfypOWVgQ+O7JD6h+T1OyLK9Hw DnPA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=aHtOPwCYX9R1dd4MhMReRP4C81aBW4LsdOk9GOQock4=; fh=2A5WQKu3s0HSbOm+KO3Aq9miX1cvZu/zz3ANfE2bsGo=; b=U9VubZnVQSM0d/D7cigVDjIaUKWYouFLnL5dEm3QNOU0k8XIw5hr1jkR50T4rZ4Aen YU7MmoFhgNqEWNr84jnUUOmkDCkZtyRh/Md/8MXNCx0RMz8jfuvmUBzt3aCHGKnc3uP9 5R/9nZQl87b/zvQEF8Ga9RxvBQyFN2j1//aWTCtvU0TRTdf0XTru/CvKRmKOQzckc9oJ NCUBohlPVPX5Yen/b/izSzhMf6D+2Fxxp7MecA2OuhMkC5aysuEhjcJcim2WT2SAWKIr vlTlPMxy4Ay+QDxwkUX+Qej9IPQOAoPa8z7zpGEHb1EP5fbWd9bFLEt/ta1DlU/40z3P FBRQ== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (server2.sourceware.org. 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b=X05oRSeDQ/DsDth8SBg0DQv/vP0vuXNRerBogovZrwB6+rRkvGjfQVOFT6U9ibIeqw0eQwjMQSvjQgxi4kPDO5eIQxYglXSvurI9sX5jNo8VbNwutxZKTQZNhXOJxXHE3jT8vnDQNcinmM5DAeP5XQ4V4NBBa8up44Jb/cD/yMw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.2.6.5]) by gateway (Coremail) with SMTP id _____8DxFehebmhlJOc9AA--.64838S3; Thu, 30 Nov 2023 19:13:34 +0800 (CST) Received: from 5.5.5 (unknown [10.2.6.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bx3y9abmhlt7VQAA--.48055S4; Thu, 30 Nov 2023 19:13:34 +0800 (CST) From: mengqinggang To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, liuzhensong@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, maskray@google.com, cailulu@loongson.cn, luweining@loongson.cn, wanglei@loongson.cn, hejinyang@loongson.cn, mengqinggang Subject: [PATCH v1 2/2] LoongArch: Add call and tail pseudo instructions Date: Thu, 30 Nov 2023 19:13:28 +0800 Message-Id: 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binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783987259257525927 X-GMAIL-MSGID: 1783987259257525927 --- gas/testsuite/gas/loongarch/medium-call.d | 10 ++++++++-- gas/testsuite/gas/loongarch/medium-call.s | 2 ++ ld/testsuite/ld-loongarch-elf/medium-call.s | 2 ++ opcodes/loongarch-opc.c | 11 +++++++++++ 4 files changed, 23 insertions(+), 2 deletions(-) diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/gas/loongarch/medium-call.d index 4183818cb4f..3491760b96a 100644 --- a/gas/testsuite/gas/loongarch/medium-call.d +++ b/gas/testsuite/gas/loongarch/medium-call.d @@ -10,6 +10,12 @@ Disassembly of section .text: [ ]+0:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0 [ ]+0: R_LARCH_CALL36[ ]+a [ ]+4:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 -[ ]+8:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0 +[ ]+8:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0 [ ]+8: R_LARCH_CALL36[ ]+a -[ ]+c:[ ]+4c000180[ ]+jr[ ]+\$t0 +[ ]+c:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 +[ ]+10:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0 +[ ]+10: R_LARCH_CALL36[ ]+a +[ ]+14:[ ]+4c000180[ ]+jr[ ]+\$t0 +[ ]+18:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0 +[ ]+18: R_LARCH_CALL36[ ]+a +[ ]+1c:[ ]+4c000180[ ]+jr[ ]+\$t0 diff --git a/gas/testsuite/gas/loongarch/medium-call.s b/gas/testsuite/gas/loongarch/medium-call.s index f2977d1c6d7..55a2fc6ffff 100644 --- a/gas/testsuite/gas/loongarch/medium-call.s +++ b/gas/testsuite/gas/loongarch/medium-call.s @@ -1,6 +1,8 @@ # call .L1, r1(ra) temp register, r1(ra) return register. + call a pcaddu18i $r1, %call36(a) jirl $r1, $r1, 0 # tail .L1, r12(t0) temp register, r0(zero) return register. + tail a pcaddu18i $r12, %call36(a) jirl $r0, $r12, 0 diff --git a/ld/testsuite/ld-loongarch-elf/medium-call.s b/ld/testsuite/ld-loongarch-elf/medium-call.s index 4d1888b76a0..31d4c2c1c75 100644 --- a/ld/testsuite/ld-loongarch-elf/medium-call.s +++ b/ld/testsuite/ld-loongarch-elf/medium-call.s @@ -1,7 +1,9 @@ .L1: # call .L1, r1(ra) temp register, r1(ra) return register. + call .L1 pcaddu18i $r1, %call36(.L1) jirl $r1, $r1, 0 # tail .L1, r12(t0) temp register, r0(zero) return register. + tail .L1 pcaddu18i $r12, %call36(.L1) jirl $r0, $r12, 0 diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c index 15c7da6340c..1d02f020686 100644 --- a/opcodes/loongarch-opc.c +++ b/opcodes/loongarch-opc.c @@ -293,6 +293,15 @@ const char *const loongarch_x_normal_name[32] = &LARCH_opts.ase_lp64, \ &LARCH_opts.ase_gpcr +#define INSN_LA_CALL \ + "pcaddu18i $ra,%%call36(%1);" \ + "jirl $ra,$ra,0;", \ + &LARCH_opts.ase_lp64, 0 + +#define INSN_LA_TAIL \ + "pcaddu18i $t0,%%call36(%1);" \ + "jirl $zero,$t0,0;", \ + &LARCH_opts.ase_lp64, 0 static struct loongarch_opcode loongarch_macro_opcodes[] = { @@ -340,6 +349,8 @@ static struct loongarch_opcode loongarch_macro_opcodes[] = { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64, 0 }, { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64_LARGE_ABS, 0 }, { 0, 0, "la.tls.gd", "r,r,l", INSN_LA_TLS_GD64_LARGE_PCREL, 0 }, + { 0, 0, "call", "la", INSN_LA_CALL, 0 }, + { 0, 0, "tail", "la", INSN_LA_TAIL, 0 }, { 0, 0, "pcaddi", "r,la", "pcaddi %1, %%pcrel_20(%2)", &LARCH_opts.ase_ilp32, 0, 0 }, { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ };