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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id q19-20020a05620a0d9300b0077da5d169bfsi517765qkl.362.2023.11.29.23.21.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 23:21:38 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bJ6YFgIx; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4C3443857C42 for ; Thu, 30 Nov 2023 07:21:38 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id AB91A3858D32 for ; Thu, 30 Nov 2023 07:21:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AB91A3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AB91A3858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.100 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701328874; cv=none; b=Da17QotvX3pGaZjduqZi7K8yxZFs1tqKHioukAY4yAoqMDsz8HEr55t8lRyjoWgyL1xEjSEMFrJCTLhY9VmV23zcTG8Jj7DNCZaFwpCZfpLDYpu2Q8cI2ak3fozYETZ/cInxMQbNjwXjrMyYxU4j291HizN9At5sFD259Ac1jhw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701328874; c=relaxed/simple; bh=HFpf05SaYV0Hh89fAODiI2i5p1NLof87rzQqna+Ju/w=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=Bk1YOMT7armrqVVgCnAwrL2Bvvr9yk//zNB/I1OF988gZ3PJr4MUgRh+vrG5VmVTrm3r9+AF2HWjWtJPTkqNAGWHk2sO0xsVrmDGIJCJ4ykUjw4vFT2jAYZVN5qSZtLRhPnXWPpPdH1cHb8Z7mQHmCywPqa+4A+dHUzjK/DTKhc= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701328872; x=1732864872; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=HFpf05SaYV0Hh89fAODiI2i5p1NLof87rzQqna+Ju/w=; b=bJ6YFgIxihbjyKB11Jb6b+Mnz5TPawihMjgH12LTZgaCma5BdXvRjpUH 4er0DluzpQ5fT0906UB4DoZVUa1yB21lGgwnsiLD+GAjmlCgmMKljis6+ tgp9fAMQUR9ClO8VkG1RhJqGcG8o2R4in0wx4Azwp2ZOPTgrgEyjaHlqL lA5hDbVqaP+6vJLH32nmFbaYA5bkM5ioUVGFN7VAzEYW8jz9cREi5x0W8 1pTs+uzHWKaJwOyjIwvCa69+J6x56pjNt1tDmTJ7fJWDtI8c27lt1tSOh b7m53ABQpip5qilSv/iaOTfvmvUqzp38l6G94zMi5NmAUYeobyIIUGI0K A==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="459774962" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="459774962" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 23:21:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="839712964" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="839712964" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 29 Nov 2023 23:21:07 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id B21F11005705; Thu, 30 Nov 2023 15:21:06 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Bugfix for legitimize move when get vec mode in zve32f Date: Thu, 30 Nov 2023 15:21:05 +0800 Message-Id: <20231130072105.2462309-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783972650873595611 X-GMAIL-MSGID: 1783972650873595611 From: Pan Li When require mode after get_vec_mode in riscv_legitimize_move, there will be precondition that the mode is exists. Or we will have E_VOIDMode and of course have ICE when required. Typically we should first check the mode exists or not before require, or more friendly like leverage exist (U *mode) to get the expected mode if exists and unchanged if not. This patch would like to fix this by exist (U *mode) for requiring a mode after get_vec_mode. PR target/112743 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_move): Take the exist (U *mode) instead of directly require (). gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112743-2.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 47 ++++++++++------- .../gcc.target/riscv/rvv/base/pr112743-2.c | 52 +++++++++++++++++++ 2 files changed, 79 insertions(+), 20 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index a4fc858fb50..19413b2c976 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2615,32 +2615,39 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) smode = SImode; nunits = nunits * 2; } - vmode = riscv_vector::get_vector_mode (smode, nunits).require (); - rtx v = gen_lowpart (vmode, SUBREG_REG (src)); - for (unsigned int i = 0; i < num; i++) + opt_machine_mode opt_mode = riscv_vector::get_vector_mode (smode, nunits); + + if (opt_mode.exists (&vmode)) { - rtx result; - if (num == 1) - result = dest; - else if (i == 0) - result = gen_lowpart (smode, dest); - else - result = gen_reg_rtx (smode); - riscv_vector::emit_vec_extract (result, v, index + i); + rtx v = gen_lowpart (vmode, SUBREG_REG (src)); - if (i == 1) + for (unsigned int i = 0; i < num; i++) { - rtx tmp - = expand_binop (Pmode, ashl_optab, gen_lowpart (Pmode, result), - gen_int_mode (32, Pmode), NULL_RTX, 0, - OPTAB_DIRECT); - rtx tmp2 = expand_binop (Pmode, ior_optab, tmp, dest, NULL_RTX, 0, - OPTAB_DIRECT); - emit_move_insn (dest, tmp2); + rtx result; + if (num == 1) + result = dest; + else if (i == 0) + result = gen_lowpart (smode, dest); + else + result = gen_reg_rtx (smode); + + riscv_vector::emit_vec_extract (result, v, index + i); + + if (i == 1) + { + rtx tmp = expand_binop (Pmode, ashl_optab, + gen_lowpart (Pmode, result), + gen_int_mode (32, Pmode), NULL_RTX, 0, + OPTAB_DIRECT); + rtx tmp2 = expand_binop (Pmode, ior_optab, tmp, dest, + NULL_RTX, 0, + OPTAB_DIRECT); + emit_move_insn (dest, tmp2); + } } + return true; } - return true; } /* Expand (set (reg:QI target) (mem:QI (address))) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c new file mode 100644 index 00000000000..fdb35fd70f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112743-2.c @@ -0,0 +1,52 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zve32f_zvfh_zfh -mabi=lp64 -O2" } */ + +#include + +union double_union +{ + double d; + __uint32_t i[2]; +}; + +#define word0(x) (x.i[1]) +#define word1(x) (x.i[0]) + +#define P 53 +#define Exp_shift 20 +#define Exp_msk1 ((__uint32_t)0x100000L) +#define Exp_mask ((__uint32_t)0x7ff00000L) + +double ulp (double _x) +{ + union double_union x, a; + register int L; + + x.d = _x; + L = (word0 (x) & Exp_mask) - (P - 1) * Exp_msk1; + + if (L > 0) + { + L |= Exp_msk1 >> 4; + word0 (a) = L; + word1 (a) = 0; + } + else + { + L = -L >> Exp_shift; + if (L < Exp_shift) + { + word0 (a) = 0x80000 >> L; + word1 (a) = 0; + } + else + { + word0 (a) = 0; + L -= Exp_shift; + word1 (a) = L >= 31 ? 1 : 1 << (31 - L); + } + } + + return a.d; +}