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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id dn11-20020a17090794cb00b0073d888f8c4fsi6598353ejc.236.2022.08.29.23.15.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 23:15:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3C8803AA801D for ; Tue, 30 Aug 2022 06:14:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id C4DD538425B3 for ; Tue, 30 Aug 2022 06:14:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C4DD538425B3 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp76t1661840036tr49rwnp Received: from server1.localdomain ( [42.247.22.66]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Aug 2022 14:13:54 +0800 (CST) X-QQ-SSF: 01400000000000C0I000000A0000000 X-QQ-FEAT: tODuP8JSt8jTyX0ghxcI5VeiiI8sT2wgeCHH/JMHGyDoHyoVU29rDsVYQXEFx KRlZF0sUymX/medEaHrlu9SQkuQu0GDFvRToQ8AD8v6cJaDPG0UbaI4Vda2118M3rVFNTjK XqdVYO/74x9wkTvNHnWXZnBnCLMWm2AIitS+trerzYw0qR1QHdo/y2xs2/4noJlhVOX1HQV ojcy2Ysup7wyDT69y76vKa1DC+25zcTbnDmp3rMjEpb7VIyJOrH1SuXO2K5a2ve5OOH4hL2 itcwg16j6nzqXIIR8vsCuHvycM2TqK7FC+90DFiTfcAlMmRYFHKQ/6Usr7d2AKUUjozHwrV oDgYURmUy8I4AxGPaBS9nN5Pny6PnqwkjFD05hEnOjhcXl1A3XzEBTuqu1cPQ== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Add RVV constraints. Date: Tue, 30 Aug 2022 14:13:51 +0800 Message-Id: <20220830061351.19655-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, zhongjuzhe Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1742565669446187742?= X-GMAIL-MSGID: =?utf-8?q?1742565669446187742?= From: zhongjuzhe gcc/ChangeLog: * config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Add "vr" constraint. (TARGET_VECTOR ? VD_REGS : NO_REGS): Add "vd" constraint. (TARGET_VECTOR ? VM_REGS : NO_REGS): Add "vm" constraint. (vp): Add poly constraint. --- gcc/config/riscv/constraints.md | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 2873d533cb5..669e5ed734b 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -108,3 +108,23 @@ A constant @code{move_operand}." (and (match_operand 0 "move_operand") (match_test "CONSTANT_P (op)"))) + +;; Vector constraints. + +(define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" + "A vector register (if available).") + +(define_register_constraint "vd" "TARGET_VECTOR ? VD_REGS : NO_REGS" + "A vector register except mask register (if available).") + +(define_register_constraint "vm" "TARGET_VECTOR ? VM_REGS : NO_REGS" + "A vector mask register (if available).") + +;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov". +;; VLENB is a run-time constant which represent the vector register length in bytes. +;; BYTES_PER_RISCV_VECTOR represent runtime invariant of vector register length in bytes. +;; We should only allow the poly equal to BYTES_PER_RISCV_VECTOR. +(define_constraint "vp" + "POLY_INT" + (and (match_code "const_poly_int") + (match_test "known_eq (rtx_to_poly_int64 (op), BYTES_PER_RISCV_VECTOR)"))) \ No newline at end of file