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Wed, 29 Nov 2023 05:29:34 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Wed, 29 Nov 2023 03:29:34 -0800 Received: from xsjarunbala50.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Wed, 29 Nov 2023 05:29:33 -0600 From: Jay Buddhabhatti To: , , , CC: , , , Jay Buddhabhatti Subject: [PATCH RESEND v2 1/2] drivers: clk: zynqmp: calculate closest mux rate Date: Wed, 29 Nov 2023 03:29:15 -0800 Message-ID: <20231129112916.23125-2-jay.buddhabhatti@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231129112916.23125-1-jay.buddhabhatti@amd.com> References: <20231129112916.23125-1-jay.buddhabhatti@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A108:EE_|PH0PR12MB8008:EE_ X-MS-Office365-Filtering-Correlation-Id: 075c65b6-6cbf-486d-2730-08dbf0ce7702 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Wed, 29 Nov 2023 03:29:46 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783897666312936255 X-GMAIL-MSGID: 1783897666312936255 Currently zynqmp clock driver is not calculating closest mux rate and because of that Linux is not setting proper frequency for CPU and not able to set given frequency for dynamic frequency scaling. E.g., In current logic initial acpu clock parent and frequency as below apll1 0 0 0 2199999978 0 0 50000 Y acpu0_mux 0 0 0 2199999978 0 0 50000 Y acpu0_idiv1 0 0 0 2199999978 0 0 50000 Y acpu0 0 0 0 2199999978 0 0 50000 Y After changing acpu frequency to 549999994 Hz using CPU freq scaling its selecting incorrect parent which is not closest frequency. rpll_to_xpd 0 0 0 1599999984 0 0 50000 Y acpu0_mux 0 0 0 1599999984 0 0 50000 Y acpu0_div1 0 0 0 533333328 0 0 50000 Y acpu0 0 0 0 533333328 0 0 50000 Y Parent should remain same since 549999994 = 2199999978 / 4. So use __clk_mux_determine_rate_closest() generic function to calculate closest rate for mux clock. After this change its selecting correct parent and correct clock rate. apll1 0 0 0 2199999978 0 0 50000 Y acpu0_mux 0 0 0 2199999978 0 0 50000 Y acpu0_div1 0 0 0 549999995 0 0 50000 Y acpu0 0 0 0 549999995 0 0 50000 Y Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by: Jay Buddhabhatti --- drivers/clk/zynqmp/clk-mux-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c index 60359333f26d..9b5d3050b742 100644 --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -89,7 +89,7 @@ static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) static const struct clk_ops zynqmp_clk_mux_ops = { .get_parent = zynqmp_clk_mux_get_parent, .set_parent = zynqmp_clk_mux_set_parent, - .determine_rate = __clk_mux_determine_rate, + .determine_rate = __clk_mux_determine_rate_closest, }; static const struct clk_ops zynqmp_clk_mux_ro_ops = { From patchwork Wed Nov 29 11:29:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Buddhabhatti, Jay" X-Patchwork-Id: 171285 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a5a7:0:b0:403:3b70:6f57 with SMTP id d7csp270542vqn; Wed, 29 Nov 2023 03:29:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IEIIEjzCDhLt9X5FESx+HCOZ6E4Iubfbfv6Z0GVyUEeYxMQKK47U/mFQXWni6Ny0wB7WYhE X-Received: by 2002:a05:6a20:3d13:b0:18c:177d:2122 with SMTP id y19-20020a056a203d1300b0018c177d2122mr17040505pzi.2.1701257391766; Wed, 29 Nov 2023 03:29:51 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1701257391; cv=pass; d=google.com; s=arc-20160816; b=V9rePKk5IDCc+O1PLsVT+40iFH3HTL9iOrIrjNhZRXKIYCdop+Ikp8nSgiYJlhD8DV E5WJFEKbRTsPuJO5r3ctvuAFgSMNbq9SCfbI+91f5KJAfBz7AnG0+pker4wi2Wc+gVxF mxbZC+ypoChgSQqEV5L194aSYfbLJEVKuLX7NebpGSMDvSf/pKSxtLowNdGpucu+xIQy weGneQxKSmjXuX0A98rbXyHChZln69RSwh/bKq27sxuKl0iBke4/Atz20hZIyXRoyvUQ Cfbd5bbk0qk7skfG66NORngeFABUW9rMEEcmR0UuK9RWEMPLsgHhl1KKWxCgRJNRWJno wUSA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=zlRqJg2qMSFYAUx4SKubFDFhDCiP2ETTgr8I2+g+9bI=; fh=qCcxsu78JX1vSL37zs8P77C3eTFXBRDXf6T38mSfIPo=; b=DlExwA/xOcxK9VaGP7pcYsHynWnVBsEk/7J+nEqQKV5qYuq0g9PrawUces8QNTOgoS gROFUM/0NzSx0qowa0slyZ2Qay+dFiJB7UqW6MWzT24QVm7xoU+8/mFAY7yl6xp2t6tD bOAHAV0e/OAYSJuMxpmGkYTiSj0h1F4QRy2JLzWpyvPBzLE07okqb8IFerYpycRC5H6I EHNIFWnglwS+9rw3cJxWvJxkd1tqRV8PQ96sUKFdP0+hsqUv7drlLLdxiIF/9nMvkOyE TlxxMF0FYz1LaI78wc6EdgROi95koMeMs5DdRQ5eWJ5O2mu4qWauPeaO4GaU8ORKJwt6 kxmw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=jgpDcQUe; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from snail.vger.email (snail.vger.email. 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Wed, 29 Nov 2023 05:29:35 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Wed, 29 Nov 2023 03:29:35 -0800 Received: from xsjarunbala50.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Wed, 29 Nov 2023 05:29:34 -0600 From: Jay Buddhabhatti To: , , , CC: , , , Jay Buddhabhatti Subject: [PATCH RESEND v2 2/2] drivers: clk: zynqmp: update divider round rate logic Date: Wed, 29 Nov 2023 03:29:16 -0800 Message-ID: <20231129112916.23125-3-jay.buddhabhatti@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231129112916.23125-1-jay.buddhabhatti@amd.com> References: <20231129112916.23125-1-jay.buddhabhatti@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FD:EE_|MN0PR12MB6127:EE_ X-MS-Office365-Filtering-Correlation-Id: a921c8ee-9181-4c7f-70bf-08dbf0ce774d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Wed, 29 Nov 2023 03:29:50 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783897670725191997 X-GMAIL-MSGID: 1783897670725191997 Currently zynqmp divider round rate is considering single parent and calculating rate and parent rate accordingly. But if divider clock flag is set to SET_RATE_PARENT then its not trying to traverse through all parent rate and not selecting best parent rate from that. So use common divider_round_rate() which is traversing through all clock parents and its rate and calculating proper parent rate. Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by: Jay Buddhabhatti --- drivers/clk/zynqmp/divider.c | 66 +++--------------------------------- 1 file changed, 5 insertions(+), 61 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 33a3b2a22659..5a00487ae408 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -110,52 +110,6 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, return DIV_ROUND_UP_ULL(parent_rate, value); } -static void zynqmp_get_divider2_val(struct clk_hw *hw, - unsigned long rate, - struct zynqmp_clk_divider *divider, - u32 *bestdiv) -{ - int div1; - int div2; - long error = LONG_MAX; - unsigned long div1_prate; - struct clk_hw *div1_parent_hw; - struct zynqmp_clk_divider *pdivider; - struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw); - - if (!div2_parent_hw) - return; - - pdivider = to_zynqmp_clk_divider(div2_parent_hw); - if (!pdivider) - return; - - div1_parent_hw = clk_hw_get_parent(div2_parent_hw); - if (!div1_parent_hw) - return; - - div1_prate = clk_hw_get_rate(div1_parent_hw); - *bestdiv = 1; - for (div1 = 1; div1 <= pdivider->max_div;) { - for (div2 = 1; div2 <= divider->max_div;) { - long new_error = ((div1_prate / div1) / div2) - rate; - - if (abs(new_error) < abs(error)) { - *bestdiv = div2; - error = new_error; - } - if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) - div2 = div2 << 1; - else - div2++; - } - if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO) - div1 = div1 << 1; - else - div1++; - } -} - /** * zynqmp_clk_divider_round_rate() - Round rate of divider clock * @hw: handle between common and hardware-specific interfaces @@ -174,6 +128,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, u32 div_type = divider->div_type; u32 bestdiv; int ret; + u8 width; /* if read only, just return current value */ if (divider->flags & CLK_DIVIDER_READ_ONLY) { @@ -193,23 +148,12 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); } - bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); - - /* - * In case of two divisors, compute best divider values and return - * divider2 value based on compute value. div1 will be automatically - * set to optimum based on required total divider value. - */ - if (div_type == TYPE_DIV2 && - (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { - zynqmp_get_divider2_val(hw, rate, divider, &bestdiv); - } + width = fls(divider->max_div); - if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) - bestdiv = rate % *prate ? 1 : bestdiv; + rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags); - bestdiv = min_t(u32, bestdiv, divider->max_div); - *prate = rate * bestdiv; + if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate)) + *prate = rate; return rate; }