From patchwork Wed Nov 29 09:27:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 171187 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a5a7:0:b0:403:3b70:6f57 with SMTP id d7csp219060vqn; Wed, 29 Nov 2023 01:27:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IFWudwTmrloynzmMTQyiNFdMZzTLOExf+es2MWH4lmW4TxY3VAVLtbj0glDUQpds6q/r3el X-Received: by 2002:a17:903:2585:b0:1cc:45d0:470b with SMTP id jb5-20020a170903258500b001cc45d0470bmr19214851plb.7.1701250074227; Wed, 29 Nov 2023 01:27:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701250074; cv=none; d=google.com; s=arc-20160816; b=AhJp4ioJBQxD7MAqRp1HH9+Mi7oF3zqIHl2gQOoemj/oWnAA6E6q279p1D8Zox/Zp7 GrotfMMOrO23BAsuY4ZtYF8g5wZhYAgzt3T/yYNBopQ1gYfNhxXZzon+LW6NXSduDClS 9yQRlYB5rOrPEovFxGT6dfkDiEIhJGooRc1GdjJ685v/UGrDoGH4EtviQo5vdT0tUr/0 D8RqDTDgz61Sn/ZVOpN7v1MHGh4kL/AHKvRqOVdGDRVYGrF9TbheGBUJXMvh5BdeBA1U NVDrIzGUJE35sE1d3VYpQz+gci8prboSD/7d1wVo1QXyw0aUCqkYy6xhZuWHK68uFJn+ dBgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Q01kL7q/pf4jfrmJjOUn5eBseDYnynjHGzTbX75ul9o=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=qRbeqoX9y6+XMUc4M7eoxjEAO5slTxOgtoV6LRk9QbXKaJ80XCY/Egym4UsU/aWLQT +OkAkZddUkklSoTN/JtrVy2gtZGZTq7HpsyYideLd2SPFyApF1XFiN6Xs4nWAnw/umOw X9jexA/rsE5h11iGZr3RXBr8Df6RSBtyZ99Pk33FrVECXYKInjXtyntXcmKyKGtjuHaz s8wAbz+nMtVjcrZHSayp7iR2dkK784VuCFa/nec72pNc8hgmwID5jQu3cuWCCbw0HS2T gVzo6SbAqHz1F0yzPAi59vzZTDGVAYDlj8r4YRBiinp1wIKJb4ccFXfQQTu+d2f7npmW dSlQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id 21-20020a170902c11500b001cc282684c6si1843663pli.278.2023.11.29.01.27.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 01:27:54 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 845C180A97A2; Wed, 29 Nov 2023 01:27:49 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229892AbjK2J1k convert rfc822-to-8bit (ORCPT + 99 others); Wed, 29 Nov 2023 04:27:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229561AbjK2J1j (ORCPT ); Wed, 29 Nov 2023 04:27:39 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EE25120; Wed, 29 Nov 2023 01:27:37 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 19EBF24E2D8; Wed, 29 Nov 2023 17:27:35 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 29 Nov 2023 17:27:34 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 29 Nov 2023 17:27:33 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v8 1/4] dt-bindings: pwm: Add bindings for OpenCores PWM Controller Date: Wed, 29 Nov 2023 17:27:29 +0800 Message-ID: <20231129092732.43387-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129092732.43387-1-william.qiu@starfivetech.com> References: <20231129092732.43387-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 29 Nov 2023 01:27:49 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783889998195892392 X-GMAIL-MSGID: 1783889998195892392 Add bindings for OpenCores PWM Controller. Signed-off-by: William Qiu Reviewed-by: Hal Feng --- .../bindings/pwm/opencores,pwm.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml new file mode 100644 index 000000000000..133f2cd417f0 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OpenCores PWM controller + +maintainers: + - William Qiu + +description: + OpenCores PTC ip core contains a PWM controller. When operating in PWM mode, + the PTC core generates binary signal with user-programmable low and high + periods. All PTC counters and registers are 32-bit. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - starfive,jh7100-pwm + - starfive,jh7110-pwm + - const: opencores,pwm-v1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm@12490000 { + compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg = <0x12490000 0x10000>; + clocks = <&clkgen 181>; + resets = <&rstgen 109>; + #pwm-cells = <3>; + }; From patchwork Wed Nov 29 09:27:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 171189 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a5a7:0:b0:403:3b70:6f57 with SMTP id d7csp219214vqn; Wed, 29 Nov 2023 01:28:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IE8lsj8NKaPu5IR7kTvn+R+FxX1ha1JKZkoMCNniXY4LwaM/uHvAP+13L4ZFhAoUAauKMGs X-Received: by 2002:a05:6a20:a10a:b0:18b:826c:411f with SMTP id q10-20020a056a20a10a00b0018b826c411fmr23142500pzk.44.1701250092768; Wed, 29 Nov 2023 01:28:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701250092; cv=none; d=google.com; s=arc-20160816; b=WdNlryuhoQQzco70HKRELegtzf22Arm51H41zX1qKrX/aeyaLkw/hX3yN73VXVQw6X GVsS28GdXT7Qac/05rOH2uCTFtNMpbOQwJ++gxejaJeX6cj44/sxlJRDSmP2KWdTDUZ3 5i5l7Bu6VL1en0tjru8u3nXZx1GCAxuVHZtPOZtoo6lLy2b2T5DbiV6Fm8Yg1EBdUIOx ltMAyQbxdzVECLfpHcHUzP1J5Icg9QIBiNZ591WCdhSku8s9Br9oMof/N7FIDcTIGhvU KcdrpWVXhRe2R4CptxubxV0nQrPyg0ZnDgxOUOo8HWlORv86zAzSLhClZaqBRBppy6fv B/cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=D8U6qX2BQNjGD1BzxUv4zjb/7U22T482YkzbVuITaMk=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=DYkIauPodT41jcapsrTMXTYUyOHIbdPkKQQTxDwRBUxPEz9uiqgrHgFL+ExY7S5cSg zkqAwVBEnfIBx5TksRSNWVuxLGlrCpBi5Zmqh4pQ8gorKQICQAQn7qkRsKN6b3/meRS2 vLQNSP1EEDT+3kerUGaYxXqP9tLh1eSwEucZ/nKr9pdEVpMmm0DxOgWOZA7JfJc1P3Uj jWRl5bHKX65yAjNJtVtISGFPyHkrbuyMqzJ/6HEWTjMEC0BjdQ64hH/oojDlPkIAbj0e 0Q61I0hK6qiCOReIfRoFmRn6lDMe8HDrKzWvCCFEcSxa1wS84CjkRMv6H1apjxv2DNBR +nSQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id q12-20020a170902eb8c00b001bdca6456c3si14616193plg.46.2023.11.29.01.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 01:28:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 550A580C034D; Wed, 29 Nov 2023 01:28:11 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229561AbjK2J16 convert rfc822-to-8bit (ORCPT + 99 others); Wed, 29 Nov 2023 04:27:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230233AbjK2J1q (ORCPT ); Wed, 29 Nov 2023 04:27:46 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 234EE1707; Wed, 29 Nov 2023 01:27:47 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 43C717FDC; Wed, 29 Nov 2023 17:27:36 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 29 Nov 2023 17:27:35 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 29 Nov 2023 17:27:34 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v8 2/4] pwm: opencores: Add PWM driver support Date: Wed, 29 Nov 2023 17:27:30 +0800 Message-ID: <20231129092732.43387-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129092732.43387-1-william.qiu@starfivetech.com> References: <20231129092732.43387-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 29 Nov 2023 01:28:11 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783890017445378623 X-GMAIL-MSGID: 1783890017445378623 Add driver for OpenCores PWM Controller. And add compatibility code which based on StarFive SoC. Co-developed-by: Hal Feng Signed-off-by: Hal Feng Signed-off-by: William Qiu --- MAINTAINERS | 7 ++ drivers/pwm/Kconfig | 12 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ocores.c | 232 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 252 insertions(+) create mode 100644 drivers/pwm/pwm-ocores.c diff --git a/MAINTAINERS b/MAINTAINERS index 012df8ccf34e..ae6a7be47bc9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16206,6 +16206,13 @@ F: Documentation/i2c/busses/i2c-ocores.rst F: drivers/i2c/busses/i2c-ocores.c F: include/linux/platform_data/i2c-ocores.h +OPENCORES PWM DRIVER +M: William Qiu +M: Hal Feng +S: Supported +F: Documentation/devicetree/bindings/pwm/opencores,pwm.yaml +F: drivers/pwm/pwm-ocores.c + OPENRISC ARCHITECTURE M: Jonas Bonn M: Stefan Kristiansson diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 4b956d661755..d87e1bb350ba 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -444,6 +444,18 @@ config PWM_NTXEC controller found in certain e-book readers designed by the original design manufacturer Netronix. +config PWM_OCORES + tristate "OpenCores PWM support" + depends on HAS_IOMEM && OF + depends on COMMON_CLK && RESET_CONTROLLER + depends on ARCH_STARFIVE || COMPILE_TEST + help + If you say yes to this option, support will be included for the + OpenCores PWM. For details see https://opencores.org/projects/ptc. + + To compile this driver as a module, choose M here: the module + will be called pwm-ocores. + config PWM_OMAP_DMTIMER tristate "OMAP Dual-Mode Timer PWM support" depends on OF diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c5ec9e168ee7..517c4f643058 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o obj-$(CONFIG_PWM_MXS) += pwm-mxs.o obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o +obj-$(CONFIG_PWM_OCORES) += pwm-ocores.o obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c new file mode 100644 index 000000000000..d96318b18570 --- /dev/null +++ b/drivers/pwm/pwm-ocores.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OpenCores PWM Driver + * + * https://opencores.org/projects/ptc + * + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd. + * + * Limitations: + * - The hardware only do inverted polarity. + * - The hardware minimum period / duty_cycle is (1 / pwm_apb clock frequency) ns. + * - The hardware maximum period / duty_cycle is (U32_MAX / pwm_apb clock frequency) ns. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* OCPWM_CTRL register bits*/ +#define REG_OCPWM_EN BIT(0) +#define REG_OCPWM_ECLK BIT(1) +#define REG_OCPWM_NEC BIT(2) +#define REG_OCPWM_OE BIT(3) +#define REG_OCPWM_SIGNLE BIT(4) +#define REG_OCPWM_INTE BIT(5) +#define REG_OCPWM_INT BIT(6) +#define REG_OCPWM_CNTRRST BIT(7) +#define REG_OCPWM_CAPTE BIT(8) + +struct ocores_pwm_device { + struct pwm_chip chip; + struct clk *clk; + struct reset_control *rst; + const struct ocores_pwm_data *data; + void __iomem *regs; + u32 clk_rate; /* PWM APB clock frequency */ +}; + +struct ocores_pwm_data { + void __iomem *(*get_ch_base)(void __iomem *base, unsigned int channel); +}; + +static inline u32 ocores_readl(struct ocores_pwm_device *ddata, + unsigned int channel, + unsigned int offset) +{ + void __iomem *base = ddata->data->get_ch_base ? + ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs; + + return readl(base + offset); +} + +static inline void ocores_writel(struct ocores_pwm_device *ddata, + unsigned int channel, + unsigned int offset, u32 val) +{ + void __iomem *base = ddata->data->get_ch_base ? + ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs; + + writel(val, base + offset); +} + +static inline struct ocores_pwm_device *chip_to_ocores(struct pwm_chip *chip) +{ + return container_of(chip, struct ocores_pwm_device, chip); +} + +static void __iomem *starfive_jh71x0_get_ch_base(void __iomem *base, + unsigned int channel) +{ + unsigned int offset = (channel > 3 ? 1 << 15 : 0) + (channel & 3) * 0x10; + + return base + offset; +} + +static int ocores_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct ocores_pwm_device *ddata = chip_to_ocores(chip); + u32 period_data, duty_data, ctrl_data; + + period_data = ocores_readl(ddata, pwm->hwpwm, 0x8); + duty_data = ocores_readl(ddata, pwm->hwpwm, 0x4); + ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC); + + state->period = DIV_ROUND_UP_ULL((u64)period_data * NSEC_PER_SEC, ddata->clk_rate); + state->duty_cycle = DIV_ROUND_UP_ULL((u64)duty_data * NSEC_PER_SEC, ddata->clk_rate); + state->polarity = PWM_POLARITY_INVERSED; + state->enabled = (ctrl_data & REG_OCPWM_EN) ? true : false; + + return 0; +} + +static int ocores_pwm_apply(struct pwm_chip *chip, + struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ocores_pwm_device *ddata = chip_to_ocores(chip); + u32 ctrl_data = 0; + u64 period_data, duty_data; + + if (state->polarity != PWM_POLARITY_INVERSED) + return -EINVAL; + + ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC); + ocores_writel(ddata, pwm->hwpwm, 0xC, 0); + + period_data = DIV_ROUND_DOWN_ULL(state->period * ddata->clk_rate, NSEC_PER_SEC); + if (period_data <= U32_MAX) + ocores_writel(ddata, pwm->hwpwm, 0x8, (u32)period_data); + else + return -EINVAL; + + duty_data = DIV_ROUND_DOWN_ULL(state->duty_cycle * ddata->clk_rate, NSEC_PER_SEC); + if (duty_data <= U32_MAX) + ocores_writel(ddata, pwm->hwpwm, 0x4, (u32)duty_data); + else + return -EINVAL; + + ocores_writel(ddata, pwm->hwpwm, 0xC, 0); + + if (state->enabled) { + ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC); + ocores_writel(ddata, pwm->hwpwm, 0xC, ctrl_data | REG_OCPWM_EN | REG_OCPWM_OE); + } + + return 0; +} + +static const struct pwm_ops ocores_pwm_ops = { + .get_state = ocores_pwm_get_state, + .apply = ocores_pwm_apply, +}; + +static const struct ocores_pwm_data jh7100_pwm_data = { + .get_ch_base = starfive_jh71x0_get_ch_base, +}; + +static const struct ocores_pwm_data jh7110_pwm_data = { + .get_ch_base = starfive_jh71x0_get_ch_base, +}; + +static const struct of_device_id ocores_pwm_of_match[] = { + { .compatible = "opencores,pwm-v1" }, + { .compatible = "starfive,jh7100-pwm", .data = &jh7100_pwm_data}, + { .compatible = "starfive,jh7110-pwm", .data = &jh7110_pwm_data}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ocores_pwm_of_match); + +static int ocores_pwm_probe(struct platform_device *pdev) +{ + const struct of_device_id *id; + struct device *dev = &pdev->dev; + struct ocores_pwm_device *ddata; + struct pwm_chip *chip; + int ret; + + id = of_match_device(ocores_pwm_of_match, dev); + if (!id) + return -EINVAL; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->data = id->data; + chip = &ddata->chip; + chip->dev = dev; + chip->ops = &ocores_pwm_ops; + chip->npwm = 8; + chip->of_pwm_n_cells = 3; + + ddata->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ddata->regs)) + return dev_err_probe(dev, PTR_ERR(ddata->regs), + "Unable to map IO resources\n"); + + ddata->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(ddata->clk)) + return dev_err_probe(dev, PTR_ERR(ddata->clk), + "Unable to get pwm's clock\n"); + + ddata->rst = devm_reset_control_get_optional_exclusive(dev, NULL); + reset_control_deassert(ddata->rst); + + ddata->clk_rate = clk_get_rate(ddata->clk); + if (ddata->clk_rate <= 0) + return dev_err_probe(dev, ddata->clk_rate, + "Unable to get clock's rate\n"); + + ret = devm_pwmchip_add(dev, chip); + if (ret < 0) { + reset_control_assert(ddata->rst); + clk_disable_unprepare(ddata->clk); + return dev_err_probe(dev, ret, "Could not register PWM chip\n"); + } + + platform_set_drvdata(pdev, ddata); + + return ret; +} + +static void ocores_pwm_remove(struct platform_device *dev) +{ + struct ocores_pwm_device *ddata = platform_get_drvdata(dev); + + reset_control_assert(ddata->rst); + clk_disable_unprepare(ddata->clk); +} + +static struct platform_driver ocores_pwm_driver = { + .probe = ocores_pwm_probe, + .remove_new = ocores_pwm_remove, + .driver = { + .name = "ocores-pwm", + .of_match_table = ocores_pwm_of_match, + }, +}; +module_platform_driver(ocores_pwm_driver); + +MODULE_AUTHOR("Jieqin Chen"); +MODULE_AUTHOR("Hal Feng "); +MODULE_DESCRIPTION("OpenCores PWM PTC driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Nov 29 09:27:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 171190 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a5a7:0:b0:403:3b70:6f57 with SMTP id d7csp219366vqn; Wed, 29 Nov 2023 01:28:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IGfNPqAD3GIQr+YctCoWZdfpA8jmgoetmglMJ41NeNcpuLzUO/AB3XajidjyuWiBs0aQrIp X-Received: by 2002:a05:6808:1642:b0:3b6:4ee:49c8 with SMTP id az2-20020a056808164200b003b604ee49c8mr19983668oib.54.1701250120966; Wed, 29 Nov 2023 01:28:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701250120; cv=none; d=google.com; s=arc-20160816; b=wChu/HCvJ71uTUrqcwogA7dGJnlLfj2GYyHIgpux4Gu0xE9VT70fZ9Vxu4Xoj9Pa/T Isf2URuHTKi8pMVk33B0tKrZU7SVSHO4vqdCdO/KRQ8vQQDwZj8DhwK1phdbGxDJEHFn hDSi38KDyhZp6K/uwa0iuXM6PitWkkSmNZFsv3bq7m3BY8cx3jeJobEh4vdD1o6n7oyg sQpl9YefkDYEqXH9a+cm46JjABk6bjdD9wZNTQKb6f8R8B88/Iwdp43tB4r69z4yUg8E TbA1lnqnvlizGc/SAkKJ7dejujfWrqo9iDjQ8sbhfSL/85lGoOGrdyuU8TFyJq1MFdj9 n4lA== ARC-Message-Signature: i=1; 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[23.128.96.36]) by mx.google.com with ESMTPS id m11-20020a056a00080b00b006cc86fef8f7si8949127pfk.87.2023.11.29.01.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 01:28:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 184C08051633; Wed, 29 Nov 2023 01:28:36 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229599AbjK2J14 convert rfc822-to-8bit (ORCPT + 99 others); Wed, 29 Nov 2023 04:27:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230163AbjK2J1m (ORCPT ); Wed, 29 Nov 2023 04:27:42 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCA501A5; Wed, 29 Nov 2023 01:27:43 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 25EC324DC0A; Wed, 29 Nov 2023 17:27:37 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 29 Nov 2023 17:27:36 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 29 Nov 2023 17:27:35 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v8 3/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration Date: Wed, 29 Nov 2023 17:27:31 +0800 Message-ID: <20231129092732.43387-4-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129092732.43387-1-william.qiu@starfivetech.com> References: <20231129092732.43387-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 29 Nov 2023 01:28:36 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783890047074948733 X-GMAIL-MSGID: 1783890047074948733 Add OpenCores PWM controller node and add PWM pins configuration on VisionFive 1 board. Signed-off-by: William Qiu --- .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++ 2 files changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..11876906cc05 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN, }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = , + ; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + uart3_pins: uart3-0 { rx-pins { pinmux = ; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index e68cafe7545f..4f5eb2f60856 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -280,6 +280,15 @@ watchdog@12480000 { <&rstgen JH7100_RSTN_WDT>; }; + pwm: pwm@12490000 { + compatible = "starfive,jh7100-pwm", "opencores,pwm-v1"; + reg = <0x0 0x12490000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_PWM_APB>; + resets = <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + sfctemp: temperature-sensor@124a0000 { compatible = "starfive,jh7100-temp"; reg = <0x0 0x124a0000 0x0 0x10000>; From patchwork Wed Nov 29 09:27:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 171188 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a5a7:0:b0:403:3b70:6f57 with SMTP id d7csp219155vqn; Wed, 29 Nov 2023 01:28:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IGMJpeNHS2qHEnv9mNXa+GCeIlrESAOVavBHZgytdY5gMV3pER1+Q6WGGEIoWcTM8DqlE9R X-Received: by 2002:a05:6a20:7d90:b0:18c:159b:7f9 with SMTP id v16-20020a056a207d9000b0018c159b07f9mr17309109pzj.9.1701250085199; Wed, 29 Nov 2023 01:28:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701250085; cv=none; d=google.com; s=arc-20160816; b=qokRnL81XoUvj/ENX1ZHV7f/M0+gIgkNUr7y0y3xJrvFra//BRSdFSUdvEvKLBRumM 4s4srzvmkwjm6UFGCZPmyWvTZF7wzmmJDVh8gOVH84tg49T9kOUwOvkXt+0eAYmetQ96 03TJKCfiV6xs6++lC+DD4zjv4XDDVtg+GPCuJFmXNQKztndUaQr+TkMdNChwjTevrfl7 yoGIRqNT9CUQtkDAasT1dO7L+DcdxlK57YKAE0yDJ+qwM0NLoMojj/T1tZJ6va0G43jv p1dBQnXkDFWJDl0vK5T1728a55pluX72Bs9WHB/KNSTzMfKKh1eYxjg6eog5kPzAVRWa 76ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=pZ6wJDMpO7lokIcqTnU5AocL1c0UXVteL64YGZUE0yA=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=r1eyW0yflfU8bObeW+/ONw+DCLlpluTo0SmYxkxxmq/MmHi4E+PSJ/AI6Y0BCVpGx1 7LAKglln9DE6pSFUmjUtO4HRTAvuxlp0QWour+1vKR4RDP5fOjapxgYZ74E9ODcDAZ6x p419XmHpRKxWeb0YoS5sqtMn37Hck39LBC0xoEb56sK0QidlU6wSawyfbOZVHHTykNp0 byLp1AzscpY4U9C6sCdJkCQVdO6kOI0v+FEtliuXz8F0uISTyoRvUnBAD1XUYMPLF3Mv Tg5yJt+gYxlGJubXv4quG0Q4BBZ6ZncYpgq4pOt72PZsp6jiNGp4cHp8R3TC2wYHvzBM yBhA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id me4-20020a17090b17c400b002854774e56bsi969236pjb.15.2023.11.29.01.28.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 01:28:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id B765F80C034D; Wed, 29 Nov 2023 01:28:03 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230205AbjK2J1q convert rfc822-to-8bit (ORCPT + 99 others); Wed, 29 Nov 2023 04:27:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230111AbjK2J1l (ORCPT ); Wed, 29 Nov 2023 04:27:41 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B28401BCC; Wed, 29 Nov 2023 01:27:39 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 0DC8424E32E; Wed, 29 Nov 2023 17:27:38 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 29 Nov 2023 17:27:37 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 29 Nov 2023 17:27:36 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v8 4/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration Date: Wed, 29 Nov 2023 17:27:32 +0800 Message-ID: <20231129092732.43387-5-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129092732.43387-1-william.qiu@starfivetech.com> References: <20231129092732.43387-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 29 Nov 2023 01:28:04 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783890009299197044 X-GMAIL-MSGID: 1783890009299197044 Add OpenCores PWM controller node and add PWM pins configuration on VisionFive 2 board. Signed-off-by: William Qiu --- .../jh7110-starfive-visionfive-2.dtsi | 22 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index b89e9791efa7..e08af8a830ab 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -323,6 +323,12 @@ reserved-data@600000 { }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; @@ -513,6 +519,22 @@ GPOEN_ENABLE, }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = , + ; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + spi0_pins: spi0-0 { mosi-pins { pinmux = ; + clocks = <&syscrg JH7110_SYSCLK_PWM_APB>; + resets = <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + sfctemp: temperature-sensor@120e0000 { compatible = "starfive,jh7110-temp"; reg = <0x0 0x120e0000 0x0 0x10000>;