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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li Subject: [PATCH V11 1/7] x86: Drop CPU_SUP_INTEL from SCHED_MC_PRIO for the expansion. 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Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li Reviewed-by: Perry Yuan --- arch/x86/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index ad478a2b49e2..77b1af90f7a2 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1054,8 +1054,9 @@ config SCHED_MC config SCHED_MC_PRIO bool "CPU core priorities scheduler support" - depends on SCHED_MC && CPU_SUP_INTEL - select X86_INTEL_PSTATE + depends on SCHED_MC + select X86_INTEL_PSTATE if CPU_SUP_INTEL + select X86_AMD_PSTATE if CPU_SUP_AMD && ACPI select CPU_FREQ default y help From patchwork Wed Nov 29 06:54:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meng Li X-Patchwork-Id: 171111 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a5a7:0:b0:403:3b70:6f57 with SMTP id d7csp161376vqn; Tue, 28 Nov 2023 22:55:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IEFuDxqAIZivCPkRzJfQSmOdSneLAfbJAMAccSvjujf5zfztzvKE98zAZezXSrZ/vY3al9O X-Received: by 2002:a05:6a20:914e:b0:187:d44:59f1 with SMTP id x14-20020a056a20914e00b001870d4459f1mr16890752pzc.31.1701240937304; Tue, 28 Nov 2023 22:55:37 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1701240937; cv=pass; d=google.com; s=arc-20160816; b=nITA0Dx5QT0D26ewQPMlVvq2qaJfXW7f7VmDB8IFr92zie0jc+QUwUEul9rF9YIAwr Ilz8UEFqv0jzi6Fl2NIAGoJQxXI0FxM+MeMtJmtBXXlorvm21dfD/kHofCiPsDVL2/vL vEgo6pX/b1BQIt1puptPqSxr4I7YNwKoWHRj1BSuPK39XnMxDXk35UmJv67jVCxvlShe JhJRGxbFGCJczM/Yd1z16ZpQFYk4WC7w4gTOUsc0K+SWew7q9XKf00pCiCZ51Slwdf3P q3+Hexh1DPx/nAV0uhH5ajMSk16EB3AL3VdsLZ66937uUHSV+NvsrxQ1NN39UTgHZ+Tx tT8Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AlF2WKiSUPyODRJ7ueMUccEPh7maCKY1Dj6+XRqyp7A=; fh=px4bRiBuq3I9SXanjlkRNLIg6oMFdG8uo3HGDz2F7II=; b=BL0TZO/0FLGAltfAu65h9yFhVlOdCEAO93XUVxjcPbyvCEqLGBmnd/LcsLQWpARapv R9vL1vIdP7g6UK530PNLwFzKbbl0rYyRFGRLld1pL2jdEJb4hYs7CVHzgOAPe+9DWBzk t9FCpn8bRTtWIb5903HloUHpzDK4bSnsN+H9ehJVvwQryyNr0al1CiMv+4t2L0BbMCHY +y/+h88cuiUZrYGn9P6mN6/SnMDazE+0xIfzH+onUawaDeD2vi/CsHOyCb+OK9XKHcTQ KEgkXQFWP0RLegyHS2FjIi3wROPpnPA36cXZ7avK5N0CZHIH7PnD91y39E5ozdf2ysZE Qf9Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=m902KU9M; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from howler.vger.email (howler.vger.email. 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V11 2/7] acpi: cppc: Add get the highest performance cppc control Date: Wed, 29 Nov 2023 14:54:32 +0800 Message-ID: <20231129065437.290183-3-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129065437.290183-1-li.meng@amd.com> References: <20231129065437.290183-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA51:EE_|PH7PR12MB7018:EE_ X-MS-Office365-Filtering-Correlation-Id: 07d383dc-f687-4d65-157b-08dbf0a8229f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UZoNGauQVKFcmzJ2KW+OcM1ZavTe0Le7BdFoYnxfc7Y5Ph56J+sP2YVtCCrzCyCuQpGz/8cvNwlDsvpPoED5KQnS0n8ew3N03WZky2wAXHR2shY0IsM8jFvwVmKae2llDOCx5lwSeyUP7LrW25cv4pZn9WAji0dNS/goWOzMYefQ7ulhQiH24H1HXnG8QK5KI7I5aB7MftkMRbWlb4RHUUdxcV1DaA92smJsKVNY5Pj9C1K21nAoB+7fHsh0XXNmeRUJaiPYaAXYfcvVr/mkdsal58MhoT+K9X6rxMv1GoBQXRix0d7E7hvys1dTSy1iujPNiA+taYNe1bjbDxcIIWfEU/l8KtyfcaB+JtFf+z9ufuUIeYbxD7AdQluJ8qPG+kmh6mqst1pBKgcNZAA5Bz3UJ7Br0H3zbrnBjzm3rP5uK3aPl+T/idraKR1EId0UyufrwQphY1hL1U1qT+8iXVpSal6NDuHR9hhFAzWK7ym6946S7Z19QMe8juXd/8XamHfgtSSSIXFXVlszAktfaCaGKSCC4GONOUp1lXeNU6RthuxRij2lqXdNDEOHJLFWlgBUw+7/pLrd+5GwmG7GTAgv8F+LZXQEN8tus9gODFxIocweCntcwWnVE8faIoMqeUPj7zMDqDCL+PXBUxvZKnoyfgexiQUNlc0S5KEwU6WyfHmIwFWIGfdMWFI/FW2l8MhSOJmh8MHpVF8DNZo1DBO89qPD0GRYeQ89WjUdNlgH954DY+0pnw1+FfhO/K4q/O9V+YFS3+mPbgISM/mj7hRA7QGIAnbjyTB437YcQEw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(346002)(39860400002)(396003)(376002)(230922051799003)(64100799003)(1800799012)(82310400011)(451199024)(186009)(46966006)(36840700001)(40470700004)(36756003)(41300700001)(1076003)(81166007)(356005)(47076005)(5660300002)(2906002)(7416002)(82740400003)(336012)(426003)(16526019)(26005)(86362001)(40480700001)(2616005)(36860700001)(7696005)(8936002)(6666004)(8676002)(4326008)(40460700003)(478600001)(966005)(70206006)(110136005)(70586007)(316002)(6636002)(54906003)(15583001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2023 06:55:12.8455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07d383dc-f687-4d65-157b-08dbf0a8229f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA51.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7018 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Tue, 28 Nov 2023 22:55:33 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783880417047412166 X-GMAIL-MSGID: 1783880417047412166 Add support for getting the highest performance to the generic CPPC driver. This enables downstream drivers such as amd-pstate to discover and use these values. Please refer to the ACPI_Spec for details on continuous performance control of CPPC. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Acked-by: Huang Rui Signed-off-by: Meng Li Link: https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#highest-performance Reviewed-by: Perry Yuan --- drivers/acpi/cppc_acpi.c | 13 +++++++++++++ include/acpi/cppc_acpi.h | 5 +++++ 2 files changed, 18 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 7ff269a78c20..ad388a0e8484 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1154,6 +1154,19 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); } +/** + * cppc_get_highest_perf - Get the highest performance register value. + * @cpunum: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_get_highest_perf(int cpunum, u64 *highest_perf) +{ + return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_highest_perf); + /** * cppc_get_epp_perf - Get the epp register value. * @cpunum: CPU from which to get epp preference value. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 6126c977ece0..c0b69ffe7bdb 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -139,6 +139,7 @@ struct cppc_cpudata { #ifdef CONFIG_ACPI_CPPC_LIB extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); +extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_enable(int cpu, bool enable); @@ -165,6 +166,10 @@ static inline int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) { return -ENOTSUPP; } +static inline int cppc_get_highest_perf(int cpunum, u64 *highest_perf) +{ + return -ENOTSUPP; +} static inline int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs) { return -ENOTSUPP; From patchwork Wed Nov 29 06:54:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meng Li X-Patchwork-Id: 171109 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a5a7:0:b0:403:3b70:6f57 with SMTP id d7csp161348vqn; Tue, 28 Nov 2023 22:55:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IGDg6hNTrXssHZriY3uX70Zu0kT1Z1tyUxnDRX7y3/oAH0TtINaMLe1x9yxmc1sKZSyJR/V X-Received: by 2002:a05:6359:738b:b0:16e:411f:ed1d with SMTP id uz11-20020a056359738b00b0016e411fed1dmr7882305rwb.18.1701240931246; Tue, 28 Nov 2023 22:55:31 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1701240931; cv=pass; d=google.com; s=arc-20160816; b=aChfGjtokIH7doOhAu188bhaproNA+3byThMo7dYhmNqoZeagD4ZWBsVgfZ9N8yEwM gZvDN0RG5t/xSC3zrxjJEUOIpddgiGAVtQJLEO6lfou3VwLIYUQpWWV/81dxADalZtO2 ChQEPgWISS86elFa3XR+XXxca4GfD0yrPCvain+VY8pLEZ0fB0SRm10moUZYP4m8noV5 7wsVEt2P725QdiqUpOU6wmglodGSDY5kqAo/9WxfitYnLV/Op4gQfDKPkGkG8Cl0oyHo Bq/GUq+Ev/hud4smvr/rEHHnE9Y3t8ReLVp0Dch0E9KzsIamyXU/4uRdAmq1RShGjWkh DfNw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=agG3WjWQm9LbsC/s5I+FFl0Buz9G0pMPDTL9zOrMnOw=; fh=px4bRiBuq3I9SXanjlkRNLIg6oMFdG8uo3HGDz2F7II=; b=G5tZnhKtNfEHE55kAXrkXDvF+Xcta08kCTiWl79E/CXidhQdckH8aCBc4eJgD2c0v6 gzPD2ZdVN01d0LJTENYRIV2wz1otVIVAOU11x3K9/THa099rh1ui/+lP2EVHfz62DDfL BsJwyoxpHLCEwqZqbuF0oo2nrnRgo+f8mkmX/DqMo6kBVyuTaM6/lExwfWBAoRJhdLQn VzwwZLCj8u3hYW/vBDV35GnDzKIs5yD32jww/GTFwDRP3Uj0q6iRT4BWcHNPjnt1yu10 VAGkM6/hM+Qn4XrTF81sQt71e15dVrIjKhJ1+xHzBU4BKFXUaj1fQTWHbZqmv4qgPWSI mzlg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=eU2b1QOG; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from snail.vger.email (snail.vger.email. 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V11 3/7] cpufreq: amd-pstate: Enable amd-pstate preferred core supporting. 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We call it amd-pstate preferrred core. Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. amd-pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority. The initial core rankings are set up by amd-pstate when the system boots. Add a variable hw_prefcore in cpudata structure. It will check if the processor and power firmware support preferred core feature. Add one new early parameter `disable` to allow user to disable the preferred core. Only when hardware supports preferred core and user set `enabled` in early parameter, amd pstate driver supports preferred core featue. Tested-by: Oleksandr Natalenko Reviewed-by: Huang Rui Reviewed-by: Wyes Karny Reviewed-by: Mario Limonciello Co-developed-by: Perry Yuan Signed-off-by: Perry Yuan Signed-off-by: Meng Li --- drivers/cpufreq/amd-pstate.c | 141 +++++++++++++++++++++++++++++++---- include/linux/amd-pstate.h | 4 + 2 files changed, 129 insertions(+), 16 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..74dcf63d75f9 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,7 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 +#define AMD_PSTATE_PREFCORE_THRESHOLD 166 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -64,6 +66,7 @@ static struct cpufreq_driver amd_pstate_driver; static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; +static bool amd_pstate_prefcore = true; /* * AMD Energy Preference Performance (EPP) @@ -290,23 +293,21 @@ static inline int amd_pstate_enable(bool enable) static int pstate_init_perf(struct amd_cpudata *cpudata) { u64 cap1; - u32 highest_perf; int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; - /* - * TODO: Introduce AMD specific power feature. - * - * CPPC entry doesn't indicate the highest performance in some ASICs. + /* For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as + * the default max perf. */ - highest_perf = amd_get_highest_perf(); - if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1)) - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (cpudata->hw_prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); @@ -318,17 +319,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) static int cppc_init_perf(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; - u32 highest_perf; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; - highest_perf = amd_get_highest_perf(); - if (highest_perf > cppc_perf.highest_perf) - highest_perf = cppc_perf.highest_perf; - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (cpudata->hw_prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); WRITE_ONCE(cpudata->lowest_nonlinear_perf, @@ -676,6 +675,80 @@ static void amd_perf_ctl_reset(unsigned int cpu) wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } +/* + * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks + * due to locking, so queue the work for later. + */ +static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); + +/* + * Get the highest performance register value. + * @cpu: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf) +{ + int ret; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 cap1; + + ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); + if (ret) + return ret; + WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); + } else { + u64 cppc_highest_perf; + + ret = cppc_get_highest_perf(cpu, &cppc_highest_perf); + if (ret) + return ret; + WRITE_ONCE(*highest_perf, cppc_highest_perf); + } + + return (ret); +} + +#define CPPC_MAX_PERF U8_MAX + +static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) +{ + int ret, prio; + u32 highest_perf; + + ret = amd_pstate_get_highest_perf(cpudata->cpu, &highest_perf); + if (ret) + return; + + cpudata->hw_prefcore = true; + /* check if CPPC preferred core feature is enabled*/ + if (highest_perf < CPPC_MAX_PERF) + prio = (int)highest_perf; + else { + pr_debug("AMD CPPC preferred core is unsupported!\n"); + cpudata->hw_prefcore = false; + return; + } + + if (!amd_pstate_prefcore) + return; + + /* + * The priorities can be set regardless of whether or not + * sched_set_itmt_support(true) has been called and it is valid to + * update them at any time after it has been called. + */ + sched_set_itmt_core_prio(prio, cpudata->cpu); + + schedule_work(&sched_prefcore_work); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -697,6 +770,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; + amd_pstate_init_prefcore(cpudata); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -845,6 +920,17 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sysfs_emit(buf, "%u\n", perf); } +static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy, + char *buf) +{ + bool hw_prefcore; + struct amd_cpudata *cpudata = policy->driver_data; + + hw_prefcore = READ_ONCE(cpudata->hw_prefcore); + + return sysfs_emit(buf, "%s\n", str_enabled_disabled(hw_prefcore)); +} + static ssize_t show_energy_performance_available_preferences( struct cpufreq_policy *policy, char *buf) { @@ -1037,18 +1123,27 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, return ret < 0 ? ret : count; } +static ssize_t prefcore_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore)); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); +static DEVICE_ATTR_RO(prefcore); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_hw_prefcore, NULL, }; @@ -1056,6 +1151,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_hw_prefcore, &energy_performance_preference, &energy_performance_available_preferences, NULL, @@ -1063,6 +1159,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, + &dev_attr_prefcore.attr, NULL }; @@ -1114,6 +1211,8 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; cpudata->epp_policy = 0; + amd_pstate_init_prefcore(cpudata); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -1527,7 +1626,17 @@ static int __init amd_pstate_param(char *str) return amd_pstate_set_driver(mode_idx); } + +static int __init amd_prefcore_param(char *str) +{ + if (!strcmp(str, "disable")) + amd_pstate_prefcore = false; + + return 0; +} + early_param("amd_pstate", amd_pstate_param); +early_param("amd_prefcore", amd_prefcore_param); MODULE_AUTHOR("Huang Rui "); MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 446394f84606..87e140e9e6db 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -52,6 +52,9 @@ struct amd_aperf_mperf { * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value * @boost_supported: check whether the Processor or SBIOS supports boost mode + * @hw_prefcore: check whether HW supports preferred core featue. + * Only when hw_prefcore and early prefcore param are true, + * AMD P-State driver supports preferred core featue. * @epp_policy: Last saved policy used to set energy-performance preference * @epp_cached: Cached CPPC energy-performance preference value * @policy: Cpufreq policy value @@ -81,6 +84,7 @@ struct amd_cpudata { u64 freq; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li Subject: [PATCH V11 4/7] cpufreq: Add a notification message that the highest perf has changed Date: Wed, 29 Nov 2023 14:54:34 +0800 Message-ID: <20231129065437.290183-5-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129065437.290183-1-li.meng@amd.com> References: <20231129065437.290183-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA51:EE_|DS0PR12MB8245:EE_ X-MS-Office365-Filtering-Correlation-Id: ccbb551f-047b-467d-dd60-08dbf0a82795 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: p7S5H+ky+iKAKMgMff1dN2yIxs6bzvSnStefVqbEfB8V1j6doAK74Yr4rMQmcuRDCM4GmNqRXB/YS60zAdX21LIcXV6Yhm+eDP0I0hRIz2qk4MGujB7OSbPCjHrpUouL+Ll+FLA7qb9CoO79Wc7lVFF8agwq+GfCm3Igdkr1KUZwxJ2Wp5TdbzozVkd9C44LKVBwN5PW/GVkHvnxG9lIYYNaq9O5I8RIENKn2W/briXlNmk2pl3P3yte9Yw4/eor99G2w7urWVALBi/r+gjmoAWG94i1ppTFEmn7tdJxa8YWT+1ATeA4a1ADokvtYR13P9ubLM3N89s9gveWArX9SsdPTD+lNt2a/RwdwdZA6OGajMdFfkiZy3pkMOgYEj259EguEEx8bKHoFjiEk7+T0hNDRlZnvVSyymnB4jsm+wOpw8Rx+azrQWbGlwvihqvgrYREl5+MvaLxnY14Qk5/AOcZDdeVJiWc3oVR6yhv10joWl44kW3UE/nXmcER5jg0WoDDucKDgB/4v4gye68WcmngAIjt29+pmK4F3GyrnbHQ9QvXKSBdt2mbgpd/9ZtDEYhLVtJGnZLZVORpYTeNIGzzzvM/fKmBFL9RisrdkLuYRUblTF/X68Zey9eDzrAvavn+U9t+L56XVQh6wXZCOkxM+fAPi7H8pDbCIohv7C3zU3bxFqYtmAnOjdfkhZiTiptAnvELnjSUXrko4tRMoO+eB2c5KB60yb6GxG4mB/kigVRKarQ0AgDSAxUpap84G8jU5jw1Aa80mzZQs8Ry6+aw9e9dfyRqjzshlbdTcBw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(136003)(346002)(39860400002)(396003)(230922051799003)(451199024)(1800799012)(82310400011)(186009)(64100799003)(46966006)(40470700004)(36840700001)(26005)(83380400001)(81166007)(6636002)(47076005)(426003)(336012)(82740400003)(86362001)(4326008)(8936002)(7696005)(70206006)(36860700001)(316002)(70586007)(110136005)(966005)(54906003)(15650500001)(5660300002)(8676002)(7416002)(478600001)(356005)(2906002)(36756003)(40480700001)(41300700001)(6666004)(16526019)(1076003)(2616005)(40460700003)(226483002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2023 06:55:21.1737 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ccbb551f-047b-467d-dd60-08dbf0a82795 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA51.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8245 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 28 Nov 2023 22:55:34 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783880414829733003 X-GMAIL-MSGID: 1783880414829733003 ACPI 6.5 section 8.4.6.1.1.1 specifies that Notify event 0x85 can be emmitted to cause the the OSPM to re-evaluate the highest performance register. Add support for this event. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li Link: https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#processor-device-notification-values Reviewed-by: Perry Yuan --- drivers/acpi/processor_driver.c | 6 ++++++ drivers/cpufreq/cpufreq.c | 13 +++++++++++++ include/linux/cpufreq.h | 5 +++++ 3 files changed, 24 insertions(+) diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c index 4bd16b3f0781..29b2fb68a35d 100644 --- a/drivers/acpi/processor_driver.c +++ b/drivers/acpi/processor_driver.c @@ -27,6 +27,7 @@ #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80 #define ACPI_PROCESSOR_NOTIFY_POWER 0x81 #define ACPI_PROCESSOR_NOTIFY_THROTTLING 0x82 +#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED 0x85 MODULE_AUTHOR("Paul Diefenbaugh"); MODULE_DESCRIPTION("ACPI Processor Driver"); @@ -83,6 +84,11 @@ static void acpi_processor_notify(acpi_handle handle, u32 event, void *data) acpi_bus_generate_netlink_event(device->pnp.device_class, dev_name(&device->dev), event, 0); break; + case ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED: + cpufreq_update_highest_perf(pr->id); + acpi_bus_generate_netlink_event(device->pnp.device_class, + dev_name(&device->dev), event, 0); + break; default: acpi_handle_debug(handle, "Unsupported event [0x%x]\n", event); break; diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 934d35f570b7..14a4cbc6dd05 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2717,6 +2717,19 @@ void cpufreq_update_limits(unsigned int cpu) } EXPORT_SYMBOL_GPL(cpufreq_update_limits); +/** + * cpufreq_update_highest_perf - Update highest performance for a given CPU. + * @cpu: CPU to update the highest performance for. + * + * Invoke the driver's ->update_highest_perf callback if present + */ +void cpufreq_update_highest_perf(unsigned int cpu) +{ + if (cpufreq_driver->update_highest_perf) + cpufreq_driver->update_highest_perf(cpu); +} +EXPORT_SYMBOL_GPL(cpufreq_update_highest_perf); + /********************************************************************* * BOOST * *********************************************************************/ diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 1c5ca92a0555..f62257b2a42f 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -235,6 +235,7 @@ int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu); void refresh_frequency_limits(struct cpufreq_policy *policy); void cpufreq_update_policy(unsigned int cpu); void cpufreq_update_limits(unsigned int cpu); +void cpufreq_update_highest_perf(unsigned int cpu); bool have_governor_per_policy(void); bool cpufreq_supports_freq_invariance(void); struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy); @@ -263,6 +264,7 @@ static inline bool cpufreq_supports_freq_invariance(void) return false; } static inline void disable_cpufreq(void) { } +static inline void cpufreq_update_highest_perf(unsigned int cpu) { } #endif #ifdef CONFIG_CPU_FREQ_STAT @@ -380,6 +382,9 @@ struct cpufreq_driver { /* Called to update policy limits on firmware notifications. */ void (*update_limits)(unsigned int cpu); + /* Called to update highest performance on firmware notifications. */ + void (*update_highest_perf)(unsigned int cpu); + /* optional */ int (*bios_limit)(int cpu, unsigned int *limit); From patchwork Wed Nov 29 06:54:35 2023 Content-Type: text/plain; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V11 5/7] cpufreq: amd-pstate: Update amd-pstate preferred core ranking dynamically Date: Wed, 29 Nov 2023 14:54:35 +0800 Message-ID: <20231129065437.290183-6-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129065437.290183-1-li.meng@amd.com> References: <20231129065437.290183-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA51:EE_|BL1PR12MB5333:EE_ X-MS-Office365-Filtering-Correlation-Id: b874ced8-ae55-482f-6740-08dbf0a82b0a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3hsDF6RMvrZrPHNWoeqYKGFRTkUh/iCL1sKZi7dhLrxPFNwiBBoYdVCeeyfa1CZX3nTEvh+qs0sKxNeoo3EciHCHYknPEjfBnMfSanyIcNYjD2igaJHTOyZ9FP9svPUHrG1sDKXsyLipK73PEYzme1oMlA5u8F3nc8INWD3zIjtOC6MN3kBaF2vOv5xRlRgQZJ6n28y0ATAq/IZkkgNYCk6wHrmwRL8EHzBAZmBizrnZg0eEcLk/MSeWMHovmWLC/IbqAhUO498dI0TkWMWjyoaS0NgZurkeMXkVmFC4LB7UpjRKJk0iengKxeYVha1oQ0SenCUsVPSmn8eHzozNhZ/l0Y7shauJeJol9/1LCV20K0p6fg3MNfEEiZW80hD6GqQbbODCOBG3/x54m7jcBmqBvZqXHez2/OqgZfe36YuMD3B6bfRuu8O58Xd4XQJ6jZOPHAnJpLs3vqvzupy0fydAYLvtZlqPj1Nk1D0xLUb8TI+34rd0L9z0wfUufTrCONRGZuPUpP9EkrcXicrpJStCH4I+1CLzE2pewj6ZFX56gApc8cR44MyYfSw6o9IrJpNXYA4wNfLEcnmT2f8qh/p07eBvlGGNteSMEQvRMiWm/pgMiv7MA870zL42M75Ack7fYJIb16nN0IS/ZxDe7e08GhdxHutJY5U8A3cSpBBFTPjTCzpQ8oVRWpvs0hNONKAvxS2bRt4gOEf2ApcR9tho7PNwNybJUyGYoAQboGS5CEDvWXXQfR/rNnIXL3vVta6rF4IshjAgSKiIXQU0Pg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(396003)(136003)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(82310400011)(36840700001)(46966006)(40470700004)(82740400003)(426003)(336012)(36860700001)(40480700001)(81166007)(40460700003)(83380400001)(47076005)(356005)(66899024)(2906002)(110136005)(86362001)(5660300002)(8936002)(8676002)(4326008)(6636002)(316002)(7416002)(70586007)(54906003)(70206006)(15650500001)(478600001)(6666004)(41300700001)(7696005)(36756003)(16526019)(26005)(2616005)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2023 06:55:26.9706 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b874ced8-ae55-482f-6740-08dbf0a82b0a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA51.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5333 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 28 Nov 2023 22:56:10 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783880455632487606 X-GMAIL-MSGID: 1783880455632487606 Preferred core rankings can be changed dynamically by the platform based on the workload and platform conditions and accounting for thermals and aging. When this occurs, cpu priority need to be set. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Reviewed-by: Huang Rui Signed-off-by: Meng Li Reviewed-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 46 ++++++++++++++++++++++++++++++++++++ include/linux/amd-pstate.h | 6 +++++ 2 files changed, 52 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 74dcf63d75f9..88df6510dcc0 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -312,6 +312,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); + WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1)); return 0; } @@ -333,6 +334,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->lowest_nonlinear_perf, cppc_perf.lowest_nonlinear_perf); WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); + WRITE_ONCE(cpudata->prefcore_ranking, cppc_perf.highest_perf); if (cppc_state == AMD_PSTATE_ACTIVE) return 0; @@ -749,6 +751,34 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) schedule_work(&sched_prefcore_work); } +static void amd_pstate_update_highest_perf(unsigned int cpu) +{ + struct cpufreq_policy *policy; + struct amd_cpudata *cpudata; + u32 prev_high = 0, cur_high = 0; + int ret; + + if ((!amd_pstate_prefcore) || (!cpudata->hw_prefcore)) + return; + + ret = amd_pstate_get_highest_perf(cpu, &cur_high); + if (ret) + return; + + policy = cpufreq_cpu_get(cpu); + cpudata = policy->driver_data; + prev_high = READ_ONCE(cpudata->prefcore_ranking); + + if (prev_high != cur_high) { + WRITE_ONCE(cpudata->prefcore_ranking, cur_high); + + if (cur_high < CPPC_MAX_PERF) + sched_set_itmt_core_prio((int)cur_high, cpu); + } + + cpufreq_cpu_put(policy); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -920,6 +950,17 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sysfs_emit(buf, "%u\n", perf); } +static ssize_t show_amd_pstate_prefcore_ranking(struct cpufreq_policy *policy, + char *buf) +{ + u32 perf; + struct amd_cpudata *cpudata = policy->driver_data; + + perf = READ_ONCE(cpudata->prefcore_ranking); + + return sysfs_emit(buf, "%u\n", perf); +} + static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy, char *buf) { @@ -1133,6 +1174,7 @@ cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); @@ -1143,6 +1185,7 @@ static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_prefcore_ranking, &amd_pstate_hw_prefcore, NULL, }; @@ -1151,6 +1194,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_prefcore_ranking, &amd_pstate_hw_prefcore, &energy_performance_preference, &energy_performance_available_preferences, @@ -1491,6 +1535,7 @@ static struct cpufreq_driver amd_pstate_driver = { .suspend = amd_pstate_cpu_suspend, .resume = amd_pstate_cpu_resume, .set_boost = amd_pstate_set_boost, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate", .attr = amd_pstate_attr, }; @@ -1505,6 +1550,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .online = amd_pstate_epp_cpu_online, .suspend = amd_pstate_epp_suspend, .resume = amd_pstate_epp_resume, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate-epp", .attr = amd_pstate_epp_attr, }; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 87e140e9e6db..426822612373 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -39,11 +39,16 @@ struct amd_aperf_mperf { * @cppc_req_cached: cached performance request hints * @highest_perf: the maximum performance an individual processor may reach, * assuming ideal conditions + * For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the fixed value as the highest_perf. * @nominal_perf: the maximum sustained performance level of the processor, * assuming ideal operating conditions * @lowest_nonlinear_perf: the lowest performance level at which nonlinear power * savings are achieved * @lowest_perf: the absolute lowest performance level of the processor + * @prefcore_ranking: the preferred core ranking, the higher value indicates a higher + * priority. * @max_freq: the frequency that mapped to highest_perf * @min_freq: the frequency that mapped to lowest_perf * @nominal_freq: the frequency that mapped to nominal_perf @@ -73,6 +78,7 @@ struct amd_cpudata { u32 nominal_perf; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V11 6/7] Documentation: amd-pstate: introduce amd-pstate preferred core Date: Wed, 29 Nov 2023 14:54:36 +0800 Message-ID: <20231129065437.290183-7-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129065437.290183-1-li.meng@amd.com> References: <20231129065437.290183-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA52:EE_|MW3PR12MB4459:EE_ X-MS-Office365-Filtering-Correlation-Id: d0ab6f56-5cce-4a4a-740e-08dbf0a83048 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7tnB0OY9rNwM0Q+mBvebVVe8vxOAmCoUEdGvMUKlWEdUETBO386/4nz/wgpbjfohSIvHi/Z+NrohCOWP5QR7daS6NoFdRaAWlvgGRnqaznEMOZHhKRAhJeg6OFDEPyAmli6bCIT50t5GbEkgXulRg8aD6hL/EtpZeobl6uFIJH1QbFtIEGanMggBDIsszO6b2QMEuDKfCtJNgx4zKeIvC21M0nhcfZYTkhFmtHkoiXsmaw+sM3sYy0pD9N6vIHHy5byUcUvlCtvI9vRPQEyG2+2aWK5mOR0DuCGplvGG8cl2CIbkoJWUQTXAHe4XAWjpDOv75uPUwtt4rvLhaTIEsmLtefUsYke97HSdSYZ5toV22QGSH7PSqNm9QRsloxUy8j/eG4RX74WfD2IqTi79/LB7e3n8l/af3ZbC7YFaLuBbggSbVP1GutduXWPax8mHV/bf/ErnzT/1VaYPi2lK/r0fiSHXJJsCTsWVgoi2qk6s7I79dG2K4UNseA7/bgi9lDZLDSc9hnQfCiXdreiU/Uz494HHG+ov+epWYBG9+w5968i9Wc0/2YMjs/CgSMr4oteaxZulezavITm2tcNjjNw72OTWhXz1PYnAQ0Hi9kP0ziCp2H5r+SwboaJUKfw7cw5IECRbE8w+j8yTNcTF/+IX5kiliyKMzf8gdR5h9kwhnfB3l5X7r1VFdKJEl/4Yb3TO2seiK123rEolXmQTjmMjK8xCks2Dh7mmYPTVu9aiYYJzLK1Us5hErB+8H8tD8gj5rmahS5LDDfjLOkauxQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(376002)(136003)(396003)(39860400002)(230922051799003)(451199024)(64100799003)(186009)(82310400011)(1800799012)(36840700001)(40470700004)(46966006)(40460700003)(316002)(6636002)(70206006)(110136005)(70586007)(54906003)(336012)(36756003)(16526019)(6666004)(426003)(26005)(1076003)(2616005)(478600001)(82740400003)(83380400001)(356005)(81166007)(86362001)(36860700001)(7696005)(47076005)(40480700001)(5660300002)(7416002)(2906002)(8936002)(41300700001)(4326008)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2023 06:55:35.7658 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0ab6f56-5cce-4a4a-740e-08dbf0a83048 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA52.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4459 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 28 Nov 2023 22:56:07 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783880453181027673 X-GMAIL-MSGID: 1783880453181027673 Introduce amd-pstate preferred core. check preferred core state set by the kernel parameter: $ cat /sys/devices/system/cpu/amd-pstate/prefcore Tested-by: Oleksandr Natalenko Reviewed-by: Wyes Karny Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li Reviewed-by: Perry Yuan < perry.yuan@amd.com> --- Documentation/admin-guide/pm/amd-pstate.rst | 59 ++++++++++++++++++++- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1cf40f69278c..0b832ff529db 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -300,8 +300,8 @@ platforms. The AMD P-States mechanism is the more performance and energy efficiency frequency management method on AMD processors. -AMD Pstate Driver Operation Modes -================================= +``amd-pstate`` Driver Operation Modes +====================================== ``amd_pstate`` CPPC has 3 operation modes: autonomous (active) mode, non-autonomous (passive) mode and guided autonomous (guided) mode. @@ -353,6 +353,48 @@ is activated. In this mode, driver requests minimum and maximum performance level and the platform autonomously selects a performance level in this range and appropriate to the current workload. +``amd-pstate`` Preferred Core +================================= + +The core frequency is subjected to the process variation in semiconductors. +Not all cores are able to reach the maximum frequency respecting the +infrastructure limits. Consequently, AMD has redefined the concept of +maximum frequency of a part. This means that a fraction of cores can reach +maximum frequency. To find the best process scheduling policy for a given +scenario, OS needs to know the core ordering informed by the platform through +highest performance capability register of the CPPC interface. + +``amd-pstate`` preferred core enables the scheduler to prefer scheduling on +cores that can achieve a higher frequency with lower voltage. The preferred +core rankings can dynamically change based on the workload, platform conditions, +thermals and ageing. + +The priority metric will be initialized by the ``amd-pstate`` driver. The ``amd-pstate`` +driver will also determine whether or not ``amd-pstate`` preferred core is +supported by the platform. + +``amd-pstate`` driver will provide an initial core ordering when the system boots. +The platform uses the CPPC interfaces to communicate the core ranking to the +operating system and scheduler to make sure that OS is choosing the cores +with highest performance firstly for scheduling the process. When ``amd-pstate`` +driver receives a message with the highest performance change, it will +update the core ranking and set the cpu's priority. + +``amd-pstate`` Preferred Core Switch +================================= +Kernel Parameters +----------------- + +``amd-pstate`` peferred core`` has two states: enable and disable. +Enable/disable states can be chosen by different kernel parameters. +Default enable ``amd-pstate`` preferred core. + +``amd_prefcore=disable`` + +For systems that support ``amd-pstate`` preferred core, the core rankings will +always be advertised by the platform. But OS can choose to ignore that via the +kernel parameter ``amd_prefcore=disable``. + User Space Interface in ``sysfs`` - General =========================================== @@ -385,6 +427,19 @@ control its functionality at the system level. They are located in the to the operation mode represented by that string - or to be unregistered in the "disable" case. +``prefcore`` + Preferred core state of the driver: "enabled" or "disabled". + + "enabled" + Enable the ``amd-pstate`` preferred core. + + "disabled" + Disable the ``amd-pstate`` preferred core + + + This attribute is read-only to check the state of preferred core set + by the kernel parameter. + ``cpupower`` tool support for ``amd-pstate`` =============================================== From patchwork Wed Nov 29 06:54:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meng Li X-Patchwork-Id: 171115 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a5a7:0:b0:403:3b70:6f57 with SMTP id d7csp161585vqn; Tue, 28 Nov 2023 22:56:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IHVgqi94FcgRu810K7dhSbNLqQTdQNMJvIvEVFxCtpozNrvJ+pIx4ezyIJWSi25JApW41Lc X-Received: by 2002:a05:6808:3012:b0:3b8:450e:6aae with SMTP id ay18-20020a056808301200b003b8450e6aaemr21233547oib.4.1701240983618; Tue, 28 Nov 2023 22:56:23 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1701240983; cv=pass; d=google.com; s=arc-20160816; b=yIRy0DOG1F75VOGUoJAiTWx6dO9D5OEoO6ZlCN9jBHAvWM1D2W3Bp6YFmrzD1R4q7o eL6U72fgz8RrTVHNZsc1SX2clxo/MGD6Bbq1kz7GQSIE2kpG9ZIQWS1Pi2DtDnLJjd1e QLc5/HCaZtKQpC5zlvocKTHXNX6am4OJJ+VSSaicVd18SMJ7vuQdSci7S+DJJo9nd0Xv awyF0en7+uEpYI6nfvrRaJ+LkTZNv5BLdpZFzPr9S4+La6dL5H8AeLBO5kz2s4BPyj4g 87dEkzlOJBBeJHFBB4JnAIGtFUIYv/ZQfMiaU1TsYnYT/n8KfzIxF+9a9BSNaNOpWxGy JLEA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iKc1dIPsjE9yGYtF4kKEBsXDZo1NDaqtRaV3fani9k4=; fh=px4bRiBuq3I9SXanjlkRNLIg6oMFdG8uo3HGDz2F7II=; b=nScnknd1e0YzhV35217pqiYdxD9EupDBvZDZ7nqqfH0qduKnVpnLzOCTaB0zubpFDs Id6/du9AMd3oIq1D1oVmPk9hIwEWS3p61pGT5r13FbMzk1ADC6gkkAGKdFWwVt+GhSm3 n1XBKVHDprbh0OUj10/bp4eddn8TnsrcfU39LqjlCMs8Q0vVbJvIWDj5uZnR3uLLCa7R zdZklFQEBaZqQUKbvwHNkul4xZIK8H1GpM+jIXNrUq4SbnHKPQj/73ONsRSETF8ZyX5b Jt2pqoYo02x1EbAJ4TP6+IMnGToQNfn9rqLS7irjYFKKl/eF8QAYJHDnV0BGUr3c9DTk sndw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=h8FVn1gD; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from lipwig.vger.email (lipwig.vger.email. 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V11 7/7] Documentation: introduce amd-pstate preferrd core mode kernel command line options Date: Wed, 29 Nov 2023 14:54:37 +0800 Message-ID: <20231129065437.290183-8-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129065437.290183-1-li.meng@amd.com> References: <20231129065437.290183-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA52:EE_|PH7PR12MB7162:EE_ X-MS-Office365-Filtering-Correlation-Id: 083529a5-eb54-4c17-065c-08dbf0a832e4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Kpz4ZUufly4qa3LqPwBfJ5kZFMYUwC6MA1wONlLmUFanJzPOhSSSzZfoxs4eeuPc672yrUaD8L/Xf2Xe2Tp/ctuNapU8BnAgNEDrcUu5Kz8CekY3gyEwysJfR3qTQf6+DX8JkPnW7ucQzV97vLW95WOniLmECzvXBSUmODNYQJygQqCQNHMoKDAXr8QI3yM/mfK75vOKG3/GiU6oSh1b5/7jO46mdrRGQmlLClUvJRB5DXupo8LWWvVdrlZln+fmnA4ceMmI3mWlJxu0JECFx22Y0KRI1KhV3gDFE3Hb0639eK7ERTBCJCRsOFjbSs0ifgpkmPMpusJFd0LkzJ+0MnxDbDyEWdI7EjBvbZr5r6Dd9rNRScnBcjROV+1GSOn3L2Wyq/rI5uMZkLNWi48+YME+wr+kAlYqrnbZ9g96v+HczPutoAmQzL4m24HpIIWMTMGmmZLt8kQ8eynbE0ylkANq3PhIgFGDemTACXrUCRfZJeXhfWwVtsZv8E919oMgpDqvM2vzW+MP7mH6xTQUp/U6BxUdUGSaJJsBrErW2rk+C2YMo0lbcAHOtqkYWbTYH52t+iLePMEBnarmnFCm+xRH0y0gx2jGnHgXaNeC73NLDKM4bwOlifxn/C5b5qMT/ZeY3df6KhcFTItMx5mcvshxYv21i04SLgwvBrRfKuAyqcYLvJ36gYc3CVgE8qgIkc7EMqQgVu9fuleF6LMmM6xC6WHE0hDGhUGW3FAqQCok52zQPWb2BMIx5WY/wQ3IWNp9BM2rGeSN8s1fHaujtL4rNLJHI3pg9xn/CVP9j3imGvrk2LwVK211OkBysV7f X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(39860400002)(136003)(376002)(230922051799003)(451199024)(82310400011)(186009)(64100799003)(1800799012)(40470700004)(36840700001)(46966006)(40480700001)(41300700001)(2906002)(40460700003)(7416002)(86362001)(5660300002)(356005)(81166007)(83380400001)(70586007)(6636002)(70206006)(8936002)(4326008)(8676002)(336012)(110136005)(54906003)(16526019)(7696005)(82740400003)(2616005)(316002)(1076003)(26005)(36756003)(426003)(478600001)(47076005)(36860700001)(36900700001)(14943795004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2023 06:55:40.1408 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 083529a5-eb54-4c17-065c-08dbf0a832e4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA52.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7162 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 28 Nov 2023 22:56:21 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783880466052193555 X-GMAIL-MSGID: 1783880466052193555 amd-pstate driver support enable/disable preferred core. Default enabled on platforms supporting amd-pstate preferred core. Disable amd-pstate preferred core with "amd_prefcore=disable" added to the kernel command line. Signed-off-by: Meng Li Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Reviewed-by: Huang Rui Tested-by: Oleksandr Natalenko Reviewed-by: Perry Yuan < perry.yuan@amd.com> --- Documentation/admin-guide/kernel-parameters.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 758bb25ea3e6..008bdfd63c22 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -363,6 +363,11 @@ selects a performance level in this range and appropriate to the current workload. + amd_prefcore= + [X86] + disable + Disable amd-pstate preferred core. + amijoy.map= [HW,JOY] Amiga joystick support Map of devices attached to JOY0DAT and JOY1DAT Format: ,