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[8.43.85.97]) by mx.google.com with ESMTPS id 3-20020ac85943000000b004236d668b48si12482084qtz.720.2023.11.28.19.18.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 19:18:34 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 092EB3857B85 for ; Wed, 29 Nov 2023 03:18:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 023D03858D3C for ; Wed, 29 Nov 2023 03:18:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 023D03858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 023D03858D3C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701227891; cv=none; b=QOoWJJwCPgqdk9k5VfNUF37eSz82Jd/3vAM9fEDcKJyVPCo9l59iB1uIGDh7yQSxMZloEhI0zrf+ZynrMxwjnCF/PsB9kWW0zWjKkItVeL9CFPVWH19t2U00k7N9JYh0QmJs8ucq9Kj+mtHb6b6fIpJdsiuSgPgEZE0g7mr5oyQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701227891; c=relaxed/simple; bh=Z+hpiomDvD9lUbJkMAeqTBW5bpnvVYIqiEhmfiQ3Tp8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=UmpMzkmN5fgRG7Zhu9YNWQ++08iY+HBLv1Vk91rRT0vJmq5Iq7g+ZrLOxlwM7lTY7jd4mL57ktWfGlp3OVeEQLEIZgpzWljmiH5sEpjT5BskptEnC5gQyc1Ql2sI/0mWrqLgdQZBVjCHmUxXJfj3HKUJKYsz6Vl/DhnZ5q3z45I= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8BxbOptrWZl55E9AA--.29449S3; Wed, 29 Nov 2023 11:18:05 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bx7txqrWZlQWlPAA--.45324S4; Wed, 29 Nov 2023 11:18:02 +0800 (CST) From: Jiahao Xu To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, chenglulu@loongson.cn, xuchenghua@loongson.cn, Jiahao Xu Subject: [PATCH] LoongArch: Fix ICE and use simplify_gen_subreg instead of gen_rtx_SUBREG directly. Date: Wed, 29 Nov 2023 11:18:00 +0800 Message-Id: <20231129031800.37090-1-xujiahao@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bx7txqrWZlQWlPAA--.45324S4 X-CM-SenderInfo: 50xmxthkdrqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj93XoWfGryftr17WrykKr13tr47Awc_yoWkKrW7pr W5WF47Kw48tF9Iyas5Ga43A34IyrZrJrsI9F93t3yfGr13X34Fqa4Ykw4ayFyUta1v9rW7 Zr1kA3Wjyw17G3gCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07j83kZUUUUU= X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783866761472305613 X-GMAIL-MSGID: 1783866761472305613 loongarch_expand_vec_cond_mask_expr generates 'subreg's of 'subreg's, which are not supported in gcc, it causes an ICE: ice.c:55:1: error: unrecognizable insn: 55 | } | ^ (insn 63 62 64 8 (set (reg:V4DI 278) (subreg:V4DI (subreg:V4DF (reg:V4DI 273 [ vect__53.26 ]) 0) 0)) -1 (nil)) during RTL pass: vregs ice.c:55:1: internal compiler error: in extract_insn, at recog.cc:2804 Last time, Ruoyao has fixed a similar ICE: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636156.html This patch fixes ICE and use simplify_gen_subreg instead of gen_rtx_SUBREG as much as possible to avoid the same ice happening again. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_try_expand_lsx_vshuf_const): Use simplify_gen_subreg instead of gen_rtx_SUBREG. (loongarch_expand_vec_perm_const_2): Ditto. (loongarch_expand_vec_cond_expr): Ditto. gcc/testsuite/ChangeLog: * gcc.target/loongarch/pr112476-3.c: New test. * gcc.target/loongarch/pr112476-4.c: New test. diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index e8a2584ac97..69fcb0aa6fb 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -8799,13 +8799,13 @@ loongarch_try_expand_lsx_vshuf_const (struct expand_vec_perm_d *d) if (d->vmode == E_V2DFmode) { sel = gen_rtx_CONST_VECTOR (E_V2DImode, gen_rtvec_v (d->nelt, rperm)); - tmp = gen_rtx_SUBREG (E_V2DImode, d->target, 0); + tmp = simplify_gen_subreg (E_V2DImode, d->target, d->vmode, 0); emit_move_insn (tmp, sel); } else if (d->vmode == E_V4SFmode) { sel = gen_rtx_CONST_VECTOR (E_V4SImode, gen_rtvec_v (d->nelt, rperm)); - tmp = gen_rtx_SUBREG (E_V4SImode, d->target, 0); + tmp = simplify_gen_subreg (E_V4SImode, d->target, d->vmode, 0); emit_move_insn (tmp, sel); } else @@ -9584,8 +9584,8 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d) /* Adjust op1 for selecting correct value in high 128bit of target register. op1: E_V4DImode, { 4, 5, 6, 7 } -> { 2, 3, 4, 5 }. */ - rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0); - rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, d->op0, 0); + rtx conv_op1 = simplify_gen_subreg (E_V4DImode, op1_alt, d->vmode, 0); + rtx conv_op0 = simplify_gen_subreg (E_V4DImode, d->op0, d->vmode, 0); emit_insn (gen_lasx_xvpermi_q_v4di (conv_op1, conv_op1, conv_op0, GEN_INT (0x21))); @@ -9614,8 +9614,8 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d) emit_move_insn (op0_alt, d->op0); /* Generate subreg for fitting into insn gen function. */ - rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0); - rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0); + rtx conv_op1 = simplify_gen_subreg (E_V4DImode, op1_alt, d->vmode, 0); + rtx conv_op0 = simplify_gen_subreg (E_V4DImode, op0_alt, d->vmode, 0); /* Adjust op value in temp register. op0 = {0,1,2,3}, op1 = {4,5,0,1} */ @@ -9661,9 +9661,10 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d) emit_move_insn (op1_alt, d->op1); emit_move_insn (op0_alt, d->op0); - rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0); - rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0); - rtx conv_target = gen_rtx_SUBREG (E_V4DImode, d->target, 0); + rtx conv_op1 = simplify_gen_subreg (E_V4DImode, op1_alt, d->vmode, 0); + rtx conv_op0 = simplify_gen_subreg (E_V4DImode, op0_alt, d->vmode, 0); + rtx conv_target = simplify_gen_subreg (E_V4DImode, d->target, + d->vmode, 0); emit_insn (gen_lasx_xvpermi_q_v4di (conv_op1, conv_op1, conv_op0, GEN_INT (0x02))); @@ -9695,9 +9696,10 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d) Selector sample: E_V4DImode, { 0, 1, 4 ,5 } */ if (!d->testing_p) { - rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, d->op1, 0); - rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, d->op0, 0); - rtx conv_target = gen_rtx_SUBREG (E_V4DImode, d->target, 0); + rtx conv_op1 = simplify_gen_subreg (E_V4DImode, d->op1, d->vmode, 0); + rtx conv_op0 = simplify_gen_subreg (E_V4DImode, d->op0, d->vmode, 0); + rtx conv_target = simplify_gen_subreg (E_V4DImode, d->target, + d->vmode, 0); /* We can achieve the expectation by using sinple xvpermi.q insn. */ emit_move_insn (conv_target, conv_op1); @@ -9722,8 +9724,8 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d) emit_move_insn (op1_alt, d->op1); emit_move_insn (op0_alt, d->op0); - rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0); - rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0); + rtx conv_op1 = simplify_gen_subreg (E_V4DImode, op1_alt, d->vmode, 0); + rtx conv_op0 = simplify_gen_subreg (E_V4DImode, op0_alt, d->vmode, 0); /* Adjust op value in temp regiter. op0 = { 0, 1, 2, 3 }, op1 = { 6, 7, 2, 3 } */ emit_insn (gen_lasx_xvpermi_q_v4di (conv_op1, conv_op1, @@ -9767,9 +9769,10 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d) emit_move_insn (op1_alt, d->op1); emit_move_insn (op0_alt, d->op0); - rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0); - rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0); - rtx conv_target = gen_rtx_SUBREG (E_V4DImode, d->target, 0); + rtx conv_op1 = simplify_gen_subreg (E_V4DImode, op1_alt, d->vmode, 0); + rtx conv_op0 = simplify_gen_subreg (E_V4DImode, op0_alt, d->vmode, 0); + rtx conv_target = simplify_gen_subreg (E_V4DImode, d->target, + d->vmode, 0); emit_insn (gen_lasx_xvpermi_q_v4di (conv_op1, conv_op1, conv_op0, GEN_INT (0x13))); @@ -9801,10 +9804,11 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d) Selector sample:E_V8SImode, { 2, 2, 2, 2, 2, 2, 2, 2 } */ if (!d->testing_p) { - rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, d->op1, 0); - rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, d->op0, 0); + rtx conv_op1 = simplify_gen_subreg (E_V4DImode, d->op1, d->vmode, 0); + rtx conv_op0 = simplify_gen_subreg (E_V4DImode, d->op0, d->vmode, 0); rtx temp_reg = gen_reg_rtx (d->vmode); - rtx conv_temp = gen_rtx_SUBREG (E_V4DImode, temp_reg, 0); + rtx conv_temp = simplify_gen_subreg (E_V4DImode, temp_reg, + d->vmode, 0); emit_move_insn (temp_reg, d->op0); @@ -9913,9 +9917,11 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d) emit_move_insn (op0_alt, d->op0); emit_move_insn (op1_alt, d->op1); - rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, d->op0, 0); - rtx conv_op0a = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0); - rtx conv_op1a = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0); + rtx conv_op0 = simplify_gen_subreg (E_V4DImode, d->op0, d->vmode, 0); + rtx conv_op0a = simplify_gen_subreg (E_V4DImode, op0_alt, + d->vmode, 0); + rtx conv_op1a = simplify_gen_subreg (E_V4DImode, op1_alt, + d->vmode, 0); /* Duplicate op0's low 128bit in op0, then duplicate high 128bit in op1. After this, xvshuf.* insn's selector argument can @@ -9948,10 +9954,12 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d) emit_move_insn (op0_alt, d->op0); emit_move_insn (op1_alt, d->op1); - rtx conv_op0a = gen_rtx_SUBREG (E_V4DImode, op0_alt, 0); - rtx conv_op1a = gen_rtx_SUBREG (E_V4DImode, op1_alt, 0); - rtx conv_op0 = gen_rtx_SUBREG (E_V4DImode, d->op0, 0); - rtx conv_op1 = gen_rtx_SUBREG (E_V4DImode, d->op1, 0); + rtx conv_op0a = simplify_gen_subreg (E_V4DImode, op0_alt, + d->vmode, 0); + rtx conv_op1a = simplify_gen_subreg (E_V4DImode, op1_alt, + d->vmode, 0); + rtx conv_op0 = simplify_gen_subreg (E_V4DImode, d->op0, d->vmode, 0); + rtx conv_op1 = simplify_gen_subreg (E_V4DImode, d->op1, d->vmode, 0); /* Reorganize op0's hi/lo 128bit and op1's hi/lo 128bit, to make sure that selector's low 128bit can access all op0's elements, and @@ -10071,12 +10079,12 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d) { case E_V4DFmode: sel = gen_rtx_CONST_VECTOR (E_V4DImode, gen_rtvec_v (d->nelt, rperm)); - tmp = gen_rtx_SUBREG (E_V4DImode, d->target, 0); + tmp = simplify_gen_subreg (E_V4DImode, d->target, d->vmode, 0); emit_move_insn (tmp, sel); break; case E_V8SFmode: sel = gen_rtx_CONST_VECTOR (E_V8SImode, gen_rtvec_v (d->nelt, rperm)); - tmp = gen_rtx_SUBREG (E_V8SImode, d->target, 0); + tmp = simplify_gen_subreg (E_V8SImode, d->target, d->vmode, 0); emit_move_insn (tmp, sel); break; default: @@ -10162,7 +10170,7 @@ loongarch_expand_vec_perm_const_2 (struct expand_vec_perm_d *d) 64bit in target vector register. */ else if (extract_ev_od) { - rtx converted = gen_rtx_SUBREG (E_V4DImode, d->target, 0); + rtx converted = simplify_gen_subreg (E_V4DImode, d->target, d->vmode, 0); emit_insn (gen_lasx_xvpermi_d_v4di (converted, converted, GEN_INT (0xD8))); } @@ -11252,7 +11260,9 @@ loongarch_expand_vec_cond_expr (machine_mode mode, machine_mode vimode, if (mode != vimode) { xop1 = gen_reg_rtx (vimode); - emit_move_insn (xop1, gen_rtx_SUBREG (vimode, operands[1], 0)); + emit_move_insn (xop1, + simplify_gen_subreg (vimode, operands[1], + mode, 0)); } emit_move_insn (src1, xop1); } @@ -11269,7 +11279,9 @@ loongarch_expand_vec_cond_expr (machine_mode mode, machine_mode vimode, if (mode != vimode) { xop2 = gen_reg_rtx (vimode); - emit_move_insn (xop2, gen_rtx_SUBREG (vimode, operands[2], 0)); + emit_move_insn (xop2, + simplify_gen_subreg (vimode, operands[2], + mode, 0)); } emit_move_insn (src2, xop2); } @@ -11288,7 +11300,8 @@ loongarch_expand_vec_cond_expr (machine_mode mode, machine_mode vimode, gen_rtx_AND (vimode, mask, src1)); /* The result is placed back to a register with the mask. */ emit_insn (gen_rtx_SET (mask, bsel)); - emit_move_insn (operands[0], gen_rtx_SUBREG (mode, mask, 0)); + emit_move_insn (operands[0], + simplify_gen_subreg (mode, mask, vimode, 0)); } } diff --git a/gcc/testsuite/gcc.target/loongarch/pr112476-3.c b/gcc/testsuite/gcc.target/loongarch/pr112476-3.c new file mode 100644 index 00000000000..d696d4182bb --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr112476-3.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mlsx" } */ + +#include + +typedef int8_t orc_int8; +typedef int16_t orc_int16; +typedef int32_t orc_int32; +typedef int64_t orc_int64; + +typedef union +{ + orc_int32 i; + float f; + orc_int16 x2[2]; + orc_int8 x4[4]; +} orc_union32; +typedef union +{ + orc_int64 i; + double f; + orc_int32 x2[2]; + float x2f[2]; + orc_int16 x4[4]; +} orc_union64; + +void +audio_orc_s32_to_double (double * restrict d1, + const signed int * restrict s1, int n) +{ + int i; + orc_union64 *restrict ptr0; + const orc_union32 *restrict ptr4; + orc_union32 var33; + orc_union64 var34; + orc_union64 var35; + orc_union64 var36; + + ptr0 = (orc_union64 *) d1; + ptr4 = (orc_union32 *) s1; + + var34.i = 0x41e0000000000000UL; + + for (i = 0; i < n; i++) { + var33 = ptr4[i]; + var36.f = var33.i; + { + orc_union64 _src1; + orc_union64 _src2; + orc_union64 _dest1; + _src1.i = ((var36.i) & ((((var36.i)&0x7ff0000000000000UL) == 0) ? 0xfff0000000000000UL : 0xffffffffffffffffUL)); + _src2.i = ((var34.i) & ((((var34.i)&0x7ff0000000000000UL) == 0) ? 0xfff0000000000000UL : 0xffffffffffffffffUL)); + _dest1.f = _src1.f / _src2.f; + var35.i = ((_dest1.i) & ((((_dest1.i)&0x7ff0000000000000UL) == 0) ? 0xfff0000000000000UL : 0xffffffffffffffffUL)); + } + ptr0[i] = var35; + } +} diff --git a/gcc/testsuite/gcc.target/loongarch/pr112476-4.c b/gcc/testsuite/gcc.target/loongarch/pr112476-4.c new file mode 100644 index 00000000000..955d98552eb --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr112476-4.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mlasx" } */ + +#include "pr112476-3.c"