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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id m12-20020a1709062acc00b009c3828fec06sm5734760eje.81.2023.11.27.08.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 08:20:12 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 17:20:03 +0100 Subject: [PATCH 1/6] dt-bindings: arm-smmu: Document SM8[45]50 GPU SMMU MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v1-1-a228b8122ebf@linaro.org> References: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701102008; l=2687; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=74tAYPhFS0JRCe3sr6MjDifnedbnYgVr+albesY88R0=; b=No3Vb43Hd8bD4NOsHXSg5ppXhq7oWxb1HCy48OeWtBGzmM/Vf85XVb4qfsN85FKcmgSofqivP np1tT3yPxGoBCcURjbxS75Vp3ViOIvu5TsM+75m9B+XJYAMDFfL629i X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 27 Nov 2023 08:20:27 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783734821870054478 X-GMAIL-MSGID: 1783734821870054478 SM8450 and SM8550 both use a Qualcomm-modified MMU500 for their GPU. In both cases, it requires a set of clocks to be enabled. Describe that. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/iommu/arm,smmu.yaml | 48 +++++++++++++++++++++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index aa9e1c0895a5..19dba93a7654 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -89,6 +89,8 @@ properties: - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 + - qcom,sm8450-smmu-500 + - qcom,sm8550-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -453,6 +455,50 @@ allOf: - description: Voter clock required for HLOS SMMU access - description: Interface clock required for register access + - if: + properties: + compatible: + const: qcom,sm8450-smmu-500 + then: + properties: + clock-names: + items: + - const: gmu + - const: hub + - const: hlos + - const: bus + - const: iface + - const: ahb + + clocks: + items: + - description: GMU clock + - description: GPU HUB clock + - description: HLOS vote clock + - description: GPU memory bus clock + - description: GPU SNoC bus clock + - description: GPU AHB clock + + - if: + properties: + compatible: + const: qcom,sm8550-smmu-500 + then: + properties: + clock-names: + items: + - const: hlos + - const: bus + - const: iface + - const: ahb + + clocks: + items: + - description: HLOS vote clock + - description: GPU memory bus clock + - description: GPU SNoC bus clock + - description: GPU AHB clock + # Disallow clocks for all other platforms with specific compatibles - if: properties: @@ -473,8 +519,6 @@ allOf: - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8350-smmu-500 - - qcom,sm8450-smmu-500 - - qcom,sm8550-smmu-500 then: properties: clock-names: false From patchwork Mon Nov 27 16:20:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 170277 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp3260760vqx; Mon, 27 Nov 2023 08:21:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IF5vcwbxvySwhqR0IpxZ+bWQPwHac8u0hxBikkUQLs4K0hvwgx2u1aYCxvMOVsCiZsZZDCC X-Received: by 2002:a05:6a21:3391:b0:182:119d:2d0e with SMTP id yy17-20020a056a21339100b00182119d2d0emr12955244pzb.20.1701102094174; Mon, 27 Nov 2023 08:21:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701102094; cv=none; d=google.com; s=arc-20160816; b=XurNfIbRal1fncwIwe3Jm6H2Zk2a+KkgeGWc1mRsTaQGUYmgjyCBrjs/W7ZWd/iDFR Q6CUNVl0Q1wRyOsjX41dCK8jRBgJ4yBF7V5b+rJOIfSLt6bJ24F48PCxi3wmJ3A+u7um XK1dvqhg7kOygLNSLnge3ZkekRHymPIItLg+eT27lXPt1vSSASjk8Qcb067cbBHS2rZU ldqnGZ4SVfICDqJ8DD4mK/v6REmuZt18wUHYTdgubFqJTSJ5hGkR0mfmrkkwBCduSb1g YwNvh4eVqYG7vAXAhhwNNvXkAuHJlnDpmL9EJkfKnyPnEFHUZfSERR19y8ew0Z3CD0ze /w7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=wScVN9GJ+E8NH1QgW/pZgzNPoRc7lXT0Ko7dLMF2kn0=; fh=zzYSWXNBsU2oipz3/KLm28IOiO9aOMgcMqtn4vFvWpY=; b=vwPpkQsrTHTH6UXUlufHje5uElHMMov6xlvwNe/wdxhX1UNDCb4R3S3WypSXjyF4qn 0A/mL6DOj6AxuJsrHbUsuy86xuAYwKhTyAEtLzFAs7k1Xk3VgVs1e1v3192L1xP0WELR Z0a6bOgncopLGeC6utfuZ3CNf+5UQLRrxxbGKw7iixqoq4lbzn7UwQczAZNIf/jzjUbn MfUmXhrnX+yTLvMnemoVoD/JQqbWchzvUsq73V6DjBQAQmtDurbKREgxUGy/IgUbafnV kliHEkMdNWwxgQ4wpYuOX8Zg84sXUiyKcD+UFnvyR4JmYlxT6zC9Ax4uzlonggwuNLuw EaqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tBb5eVlo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from howler.vger.email (howler.vger.email. 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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id m12-20020a1709062acc00b009c3828fec06sm5734760eje.81.2023.11.27.08.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 08:20:14 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 17:20:04 +0100 Subject: [PATCH 2/6] arm64: dts: qcom: sm8450: Add GPU nodes MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v1-2-a228b8122ebf@linaro.org> References: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701102008; l=7123; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=I5oAq4yvU3S7sBbp5DBP75jCv9QJAYvsZHzH8XavMSU=; b=HoaVPcrRvjXrREUWeLaJt3R2+uJce6mBb18Ppr+odKdWMibsFYokteuvpay3z5ROgGRGAbOrn dlbTW4nz8kMCq0TN9SpOcjf9dm0DocD7Sairm1/44Z/7BgYh9MDJGHm X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 27 Nov 2023 08:21:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783734829330595373 X-GMAIL-MSGID: 1783734829330595373 Add the required nodes to support the A730 GPU. Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 202 +++++++++++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index bde9c1093384..e9664672c160 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -2019,6 +2021,206 @@ tcsr: syscon@1fc0000 { reg = <0x0 0x1fc0000 0x0 0x30000>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-730.1", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x400>, + <&adreno_smmu 1 0x400>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-818000000 { + opp-hz = /bits/ 64 <818000000>; + opp-level = ; + }; + + opp-791000000 { + opp-hz = /bits/ 64 <791000000>; + opp-level = ; + }; + + opp-734000000 { + opp-hz = /bits/ 64 <734000000>; + opp-level = ; + }; + + opp-640000000 { + opp-hz = /bits/ 64 <640000000>; + opp-level = ; + }; + + opp-599000000 { + opp-hz = /bits/ 64 <599000000>; + opp-level = ; + }; + + opp-545000000 { + opp-hz = /bits/ 64 <545000000>; + opp-level = ; + }; + + opp-492000000 { + opp-hz = /bits/ 64 <492000000>; + opp-level = ; + }; + + opp-421000000 { + opp-hz = /bits/ 64 <421000000>; + opp-level = ; + }; + + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-level = ; + }; + + opp-317000000 { + opp-hz = /bits/ 64 <317000000>; + opp-level = ; + }; + + opp-285000000 { + opp-hz = /bits/ 64 <285000000>; + opp-level = ; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x400>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8450-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "gmu", + "hub", + "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8450-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; 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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id m12-20020a1709062acc00b009c3828fec06sm5734760eje.81.2023.11.27.08.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 08:20:16 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 17:20:05 +0100 Subject: [PATCH 3/6] arm64: dts: qcom: sm8550: Add GPU nodes MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v1-3-a228b8122ebf@linaro.org> References: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701102008; l=5572; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=zs3rMUmNrxdSrAAcrhg7P26RbaOTU6dGtl32v7guU6Q=; b=e1rrRcDcznSKhXJckpVjzmPlMWYvIviY5+mO0EUkcv8jDrnaXlpypvc+ixkkL04SwZfjQmZtz eEfK7YPm2HcC0QYXrU7OP5at2TW9b5jHZCqpqhIv8NFtg1UyRX1LbuP X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Mon, 27 Nov 2023 08:20:50 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783734786011396592 X-GMAIL-MSGID: 1783734786011396592 Add the required nodes to support the A740 GPU. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 166 +++++++++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7bafb3d88d69..8f6641c58b3b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2841,6 +2841,172 @@ dispcc: clock-controller@af00000 { #power-domain-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-740.1", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-615000000 { + opp-hz = /bits/ 64 <615000000>; + opp-level = ; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = ; + }; + + opp-475000000 { + opp-hz = /bits/ 64 <475000000>; + opp-level = ; + }; + + opp-401000000 { + opp-hz = /bits/ 64 <401000000>; + opp-level = ; + }; + + opp-348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-level = ; + }; + + opp-295000000 { + opp-hz = /bits/ 64 <295000000>; + opp-level = ; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8550-snps-eusb2-phy"; reg = <0x0 0x088e3000 0x0 0x154>; From patchwork Mon Nov 27 16:20:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 170273 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp3260271vqx; Mon, 27 Nov 2023 08:21:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IEsm6T3N2IR82YnYa7Mc26hSXMfpBH9gwnI8o59PfRczbF5NovCxNpBNaGDSgmaxUqUiBq9 X-Received: by 2002:a05:6a20:3d0b:b0:18c:90f9:5084 with SMTP id y11-20020a056a203d0b00b0018c90f95084mr4636922pzi.27.1701102060447; Mon, 27 Nov 2023 08:21:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701102060; cv=none; d=google.com; s=arc-20160816; b=ksCGHPjXyPrO9F/ly1GqGCVaGHFuoWMqhacGybOCU3ukYOGtENCi5x3gptMJsbs5jW MljdPxxpleVWii9GiWThhUgMfGa7YrR+0uJCl1THnUhH1o+4hy0tHTFUj+sCSp3Rda7r U77AU2TAi2Gznv8UOhhtXczYBLrcwwsfnZCqWtPDdAY/MZjOhmaJbrfFonALBMbmGgOB Atww/dJY7Br7rgfjrQmzZhdqr+uxXzAHitnIFpzGjO2g6UeT9/P71M0j+R7e36g4Vixb 0Rmyg2951eMHAbUZsTZ/dVzyu1mRM2mLgwAx+A4C9hwaixvGxc2f5uz+rBamq7GbpTCo UpvA== ARC-Message-Signature: i=1; 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Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index eef811def39b..9fe51d308675 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -596,6 +596,14 @@ &gcc { <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio17"; From patchwork Mon Nov 27 16:20:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 170276 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp3260711vqx; Mon, 27 Nov 2023 08:21:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IF9PU8bdSc90s9o7e13G8O0LLvfMczdzzpBNq643VOkMgWI7a6qWDkCvzE6ccfaQyqOgXcx X-Received: by 2002:a05:6a00:1252:b0:6cb:8abd:39b5 with SMTP id u18-20020a056a00125200b006cb8abd39b5mr17758814pfi.1.1701102091179; Mon, 27 Nov 2023 08:21:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701102091; cv=none; d=google.com; s=arc-20160816; b=jOgIPlCvBFddpPZ8Y66wdPLpOS8Nd25pYlmVjNG2tG+ipHiajE3yFx2eAJwkvBLQt9 CcM8AS4Stqln8MOoGl9oc2HSgmHCgxppKLdkd9tm5FnujKGSnQNu7IOkZoAyE4DWaeXe cZoB5r6Hn7Svsypxd8Bp4WKT5NHEX/bX9sG0VIBvKaCGkJI4sjy06qeJcZlfoDRGt9ET 4ADiyvGRQiQvnCQfpXpLYn2tMytpplkytRvKi1OJHUj2vGxe1iS3k9P4oaZL4tKWP3Le KAdbxSdpgjjurVPHWR/oXX7XqDPjdwHBe8ftDN7lZPFxr5E1bCvndHbttbdJur88FBTa uMOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=R+c7o+g11wQaVIfs6Upk57wmZsR4iWH52vbiNHzvWM8=; fh=zzYSWXNBsU2oipz3/KLm28IOiO9aOMgcMqtn4vFvWpY=; b=fXQysQzeIheFPC7XQUlW0CMUtZtkky1NAvF0etiAnpoXOHpKlDY6bwzavAH038DtVb 5O2DS8MrTI5nyUgksLzoRt/fjbFVlJ3qPgLFbTA3lgUFwWvWbOApELiXVtP3QOf9l1ze vUb2V80djrVc6wnUbkmmNtU/jdxAefu21owkJLdcZ1eh8+4zxG7MWY4hpOuDILcc03eK zd+Ubkk+eRnuZ5bSokoOqCuMkYf7BLegdb/GCYM9xjGNafUxqVqpOxwI90iuT26Q2nyW dNSva+b7bSwfoVO1jG8axyIUIRzNgygXBoYChH1FGFCANf5+NLWaKYB5HhSDhLFeOLaD MHpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=To2sSPpS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from snail.vger.email (snail.vger.email. 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Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 9a70875028b7..52244e9bfdee 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -512,6 +512,14 @@ vreg_l3g_1p2: ldo3 { }; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; + }; +}; + &i2c_master_hub_0 { status = "okay"; }; From patchwork Mon Nov 27 16:20:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 170274 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp3260414vqx; Mon, 27 Nov 2023 08:21:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IEKSGFczZJlQFVXJ2K9KppcHVoI6nj8xevdeSF9V98MVMPh3gl3bNS74mAzgrg1RxSzVo7S X-Received: by 2002:a05:6a00:93a7:b0:6be:4228:6970 with SMTP id ka39-20020a056a0093a700b006be42286970mr13353497pfb.21.1701102069444; Mon, 27 Nov 2023 08:21:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701102069; cv=none; d=google.com; s=arc-20160816; b=SB+O7qVvYvdVga0br1N1IRSWRzFdYntYkEOA99IcuakoPHrAWdgq2jx/F4csHtTYl+ j0vyMi/03oCHHMxo+yMl7kguqrojROKYisU4cCm39KGUHNJYJ01at/YFOKkHZ/xJKwSE o0QRSBpscr3mtSetrhAevAgHg3Hk52ntQ1lBulnYz5O/fNpaLiaCPmds2XGR09Q+OXZk A3sAvoZ1B9jZNnqKljgLdBgUNFSZV55P3OxiKBNMGiGICnaaApUsVBwFAiXIFvwu3ePN 4QhT2XWcyvyanwepAhaNK4pNvipRGJ1hp/DwkWe42Pfd5mGUbccr0lJbRkIo7woYFjpK enjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=8gQ6YImSRCbx+1xRUL4mfy0bfTlxIzI8pSH1DPk4t6M=; fh=zzYSWXNBsU2oipz3/KLm28IOiO9aOMgcMqtn4vFvWpY=; b=hFifMgmfZogBJ5R2mUl0JtidwRBGQD2FyGIQ/4DeB7Buo4ONe5kusRGXN1+7JWn1jB 2PHerldSsaBNQ+QqQR+QgJN539w05y05Di+TPJd3HDNXSCsLFvgGW7TDRSfkWyKK+Lrr t74P8M4SqrXWEHWCrtgMDKjMJUGf7mRiVb5vItrLRogNkzBgm4GQPJQcOF0zu+qfbfw9 QepCIeFguWGKvhTEwzMKic4H+S7sdKEG5SJtyEyy4lQsrt5MzLS/wIadleT2WkBJBaT8 UESEUaXz/rLCbnKtgk6GkMt/xMkPQgGjzJw41UBJhFFmNWXc9vr0tP1NTgVQzBITWYOT lQwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xXjPfRLM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from morse.vger.email (morse.vger.email. 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Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 20153d08edde..a20d5d76af35 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -580,6 +580,14 @@ &dispcc { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8450/a730_zap.mbn"; + }; +}; + &i2c9 { clock-frequency = <400000>; status = "okay";