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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id f1-20020a05620a280100b007759afd289bsi9623506qkp.133.2023.11.27.05.24.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 05:24:47 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5A15B3858439 for ; Mon, 27 Nov 2023 13:24:47 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by sourceware.org (Postfix) with ESMTPS id 0B1A33858CD1 for ; Mon, 27 Nov 2023 13:24:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0B1A33858CD1 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0B1A33858CD1 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.206.34.216 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701091464; cv=none; b=T7a+rIK1NWkkvjkwkT5nJxFQe5RT/bJdGTIWyiZDnHh6otC+kw6xlC/xTPmweiVLuxdAF64/+d+3iDL9yrP5nIfyYdkz62zFFq48NA7AF/fw+JLGm5kv4+0R4pNbF3DF4dTSNb5cFdhJof0fSrZTS/iSUI8IIv6DB2Q9gRFE/lU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701091464; c=relaxed/simple; bh=R2lNwtRcffkxCj1mv07r+PE5VRkVthB03X6PjGu6aCc=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Hc74IAz+sX9flfEDarW6G+CMQK5Q/bl0Lu/bfijKMm2rFLVf3o94zLB+RnVUiVdtYS1P1bZ8HoyCnzok5SRQY0pQmV9zxeOBBe6172J6qQ3YhJZkOhReJvxjTAC4rxtoNsjnVzevbcZK5cgyzzb8KEny3MynFpv7KgisXm/HaxM= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp85t1701091454tuzm8kq7 Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 27 Nov 2023 21:24:13 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: tym1VHZoWxkC9LEoBZ08IYPKaSBKZYi287rl/JUABjtMJi0ze7oD3V9veEU+y xlDeitfP9FITFET38P8+ZNUTaco9RICkCiYkGckgHFUvcpHekOPvopN8uWCVRbuUH/XcIlS cnuiVi5Aj22C/YztowGsaJV+8+9NX6t1IGy+k0b3yxMYH1w1BZSn0Suz50+YDMmVLOiyCpZ vkguGCI5JOqdnaOX+tsp9NlHytacFSgU1fneL5JVGgWwfsjD7TeMk4wpSLpgP/fHJkFAyDX DZ41dqTaouwQdUI8lDWtuqKL27mIPQ57aKaSWkhBuWG2AEsQO14IiZ3HLYqZGy88XPKvtXN rDoeOoLuyFT0J875HRc9Lx0w9nLJl1UjIWQzIKUE175JyOG8+ZVYMd7FgrCBmMwvdaI44jj qP0KYOSUi8k= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 1751474319033449838 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix VSETVL PASS regression Date: Mon, 27 Nov 2023 21:24:12 +0800 Message-Id: <20231127132412.2440640-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783723707736622823 X-GMAIL-MSGID: 1783723707736622823 This patch is regression fix patch, not an optimization patch. Since trunk GCC generates redundant vsetvl than GCC-13. This is the case: bb 2: def a2 (vsetvl a2, zero) bb 3: use a2 bb 4: use a2 (vle) before this patch: bb 2: vsetvl a2 zero bb 3: vsetvl zero, zero ----> should be eliminated. bb 4: vle.v The root cause is we didn't set bb 3 as transparent since the incorrect codes. bb 3 didn't modify "a2" just use it, the VSETVL status from bb 2 can be available to bb 3 and bb 4: bb 2 -> bb 3 -> bb4. Another regression fix is anticipation calculation: bb 4: use a5 (sub) use a5 (vle) The vle VSETVL status should be considered as anticipated as long as both sub and vle a5 def are coming from same def. Tested on zvl128b no regression. I am going to test on zvl256/zvl512/zvl1024 PR target/112713 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix regression. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr112713-1.c: New test. * gcc.target/riscv/rvv/vsetvl/pr112713-2.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 29 ++++++++---- .../gcc.target/riscv/rvv/vsetvl/pr112713-1.c | 24 ++++++++++ .../gcc.target/riscv/rvv/vsetvl/pr112713-2.c | 47 +++++++++++++++++++ 3 files changed, 91 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 74367ec8d8e..b3e07d4c3aa 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1433,9 +1433,23 @@ private: inline bool modify_or_use_vl_p (insn_info *i, const vsetvl_info &info) { - return info.has_vl () - && (find_access (i->uses (), REGNO (info.get_vl ())) - || find_access (i->defs (), REGNO (info.get_vl ()))); + if (info.has_vl ()) + { + if (find_access (i->defs (), REGNO (info.get_vl ()))) + return true; + if (find_access (i->uses (), REGNO (info.get_vl ()))) + { + resource_info resource = full_register (REGNO (info.get_vl ())); + def_lookup dl1 = crtl->ssa->find_def (resource, i); + def_lookup dl2 = crtl->ssa->find_def (resource, info.get_insn ()); + if (dl1.matching_set () || dl2.matching_set ()) + return true; + /* If their VLs are coming from same def, we still want to fuse + their VSETVL demand info to gain better performance. */ + return dl1.prev_def (i) != dl2.prev_def (i); + } + } + return false; } inline bool modify_avl_p (insn_info *i, const vsetvl_info &info) { @@ -1702,7 +1716,7 @@ public: for (insn_info *i = next_insn->prev_nondebug_insn (); i != prev_insn; i = i->prev_nondebug_insn ()) { - // no def amd use of vl + // no def and use of vl if (!ignore_vl && modify_or_use_vl_p (i, info)) return false; @@ -2635,11 +2649,8 @@ pre_vsetvl::compute_lcm_local_properties () for (const insn_info *insn : bb->real_nondebug_insns ()) { - if ((info.has_nonvlmax_reg_avl () - && find_access (insn->defs (), REGNO (info.get_avl ()))) - || (info.has_vl () - && find_access (insn->uses (), - REGNO (info.get_vl ())))) + if (info.has_nonvlmax_reg_avl () + && find_access (insn->defs (), REGNO (info.get_avl ()))) { bitmap_clear_bit (m_transp[bb_index], i); break; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c new file mode 100644 index 00000000000..76402ab6167 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +size_t +foo (char const *buf, size_t len) +{ + size_t sum = 0; + size_t vl = __riscv_vsetvlmax_e8m8(); + size_t step = vl * 4; + const char *it = buf, *end = buf + len; + for(; it + step <= end; ) { + it += vl; + vint8m8_t v3 = __riscv_vle8_v_i8m8((void*)it, vl); it += vl; + vbool1_t m3 = __riscv_vmsgt_vx_i8m8_b1(v3, -65, vl); + sum += __riscv_vcpop_m_b1(m3, vl); + } + return sum; +} + +/* { dg-final { scan-assembler-times {vsetvli} 1 } } */ +/* { dg-final { scan-assembler-not {vsetivli} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c new file mode 100644 index 00000000000..04539d998cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +static size_t +utf8_count_rvv(char const *buf, size_t len) +{ + size_t sum = 0; + for (size_t vl; len > 0; len -= vl, buf += vl) { + vl = __riscv_vsetvl_e8m8(len); + vint8m8_t v = __riscv_vle8_v_i8m8((void*)buf, vl); + vbool1_t mask = __riscv_vmsgt_vx_i8m8_b1(v, -65, vl); + sum += __riscv_vcpop_m_b1(mask, vl); + } + return sum; +} + +size_t +utf8_count_rvv_4x_tail(char const *buf, size_t len) +{ + size_t sum = 0; + size_t vl = __riscv_vsetvlmax_e8m8(); + size_t step = vl * 4; + const char *it = buf, *end = buf + len; + for(; it + step <= end; ) { + vint8m8_t v0 = __riscv_vle8_v_i8m8((void*)it, vl); it += vl; + vint8m8_t v1 = __riscv_vle8_v_i8m8((void*)it, vl); it += vl; + vint8m8_t v2 = __riscv_vle8_v_i8m8((void*)it, vl); it += vl; + vint8m8_t v3 = __riscv_vle8_v_i8m8((void*)it, vl); it += vl; + vbool1_t m0 = __riscv_vmsgt_vx_i8m8_b1(v0, -65, vl); + vbool1_t m1 = __riscv_vmsgt_vx_i8m8_b1(v1, -65, vl); + vbool1_t m2 = __riscv_vmsgt_vx_i8m8_b1(v2, -65, vl); + vbool1_t m3 = __riscv_vmsgt_vx_i8m8_b1(v3, -65, vl); + sum += __riscv_vcpop_m_b1(m0, vl); + sum += __riscv_vcpop_m_b1(m1, vl); + sum += __riscv_vcpop_m_b1(m2, vl); + sum += __riscv_vcpop_m_b1(m3, vl); + } + return sum + utf8_count_rvv(it, end - it); +} + +/* { dg-final { scan-assembler-times {vsetvli} 2 } } */ +/* { dg-final { scan-assembler-not {vsetivli} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 } } */