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[8.43.85.97]) by mx.google.com with ESMTPS id y10-20020a05620a25ca00b0077d71f57e7dsi9353305qko.174.2023.11.27.04.31.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 04:31:18 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Zht2iAP0; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 54AFB3857C48 for ; Mon, 27 Nov 2023 12:31:18 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 533223858C2D for ; Mon, 27 Nov 2023 12:31:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 533223858C2D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 533223858C2D Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.93 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701088272; cv=none; b=ldrgn8vmssAN2JmJBx6Fc2h5i2DO5sfyce9haUWpGjczlPHJsSrwm8E9B1vGHNq5wGsE/WiwtvylY6sBc9NsBRO5kwEsxm2ysZZlkhSexNMOQ0vhzXtouXTINaoAYVuOaJD5iHwVHe8NGoTbpb2iqPTIXtOkoIdOTMkg3gpqffk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701088272; c=relaxed/simple; bh=4WlzjJ6HndMnTh7IVIypjY7AI+8QM+xzkePmoY52PT0=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=WhVW2NZ5lPvMUmaLY6rHKo9pzxGmvHJbpto+Yd/5TxOFdlNoo7P3dZk2cMBFnraQ/yHfr9WKpMu3kZrsj9qeXW6u2Ad499quwXoKR02i0B7wt+xPBo55sjHvNyBbuctfvttQdFiIImdL2BUDIJ7iRZnAH5sV/QKgIzZq+9LHIWw= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701088270; x=1732624270; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=4WlzjJ6HndMnTh7IVIypjY7AI+8QM+xzkePmoY52PT0=; b=Zht2iAP0wRSd+/ZCLlsaSEXojDIuG2zjjq7bOd/Y7huNjSToJk6RJlhs lt421aQYpHnpeRnn0mKMTa4pMBREHNvzdzk1iVcFCDbqXEhHKH4/4f9pe v6YbRO+rTJQTtvnQHD273jqsMVacpgrGPcyFucfpKMm9TbalYKllXLTXP 383GgBp8REpD5U9OBExpS+GsnVesrINZWQBKX26PjlKmQX9KJGMZWYWN8 GLzFTtf0okgjNSugXIFsb4LnVSUHXRZqr/LvuXuUK2nPai7nnbtzrBAl1 J+PBTJ7I6jbdtpLvoIxfhwD8Z7946REvRyW0aqQj7o/y79VQoIJ8a5cDM w==; X-IronPort-AV: E=McAfee;i="6600,9927,10906"; a="389840242" X-IronPort-AV: E=Sophos;i="6.04,230,1695711600"; d="scan'208";a="389840242" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Nov 2023 04:31:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10906"; a="771915528" X-IronPort-AV: E=Sophos;i="6.04,230,1695711600"; d="scan'208";a="771915528" Received: from scymds04.sc.intel.com ([10.82.73.238]) by fmsmga007.fm.intel.com with ESMTP; 27 Nov 2023 04:31:09 -0800 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds04.sc.intel.com (Postfix) with ESMTP id BF52620054E4; Mon, 27 Nov 2023 04:31:07 -0800 (PST) From: "Cui, Lili" To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com, ccoutant@gmail.com Subject: [PATCH] Support APX PUSHP/POPP Date: Mon, 27 Nov 2023 12:31:06 +0000 Message-Id: <20231127123106.3600817-1-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783720342807335173 X-GMAIL-MSGID: 1783720342807335173 Hi Jan, this patch is to add APX pushp/popp. I created a new bitfile rex2 for pushp/popp in i386_opcode_modifier. I wonder if you think this is too expensive and want to replace it with a special handle. Also in decoder, no regular fixup is added. Looking forward to your comments. Thanks, Lili. gas/ChangeLog: * config/tc-i386.c (is_apx_rex2_encoding): Added rex2. * testsuite/gas/i386/x86-64.exp: Add new test for pushp and popp. * testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: New test. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.d: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.s: Ditto. opcodes/ChangeLog: * i386-dis.c (putop): print pushp and popp. * i386-gen.c: Added new BITFIELD for Rex2. * i386-opc.h: Ditto. * i386-opc.tbl: Added new insns. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-tbl.h: Regenerated. --- gas/config/tc-i386.c | 2 +- .../gas/i386/x86-64-apx-pushp-popp-intel.d | 14 ++++++ .../gas/i386/x86-64-apx-pushp-popp-inval.l | 5 +++ .../gas/i386/x86-64-apx-pushp-popp-inval.s | 7 +++ .../gas/i386/x86-64-apx-pushp-popp.d | 14 ++++++ .../gas/i386/x86-64-apx-pushp-popp.s | 8 ++++ gas/testsuite/gas/i386/x86-64.exp | 3 ++ opcodes/i386-dis.c | 45 ++++++++++++------- opcodes/i386-gen.c | 1 + opcodes/i386-opc.h | 3 ++ opcodes/i386-opc.tbl | 2 + 11 files changed, 87 insertions(+), 17 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-pushp-popp.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-pushp-popp.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 0dde2a9ad44..0321f366f48 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3892,7 +3892,7 @@ is_apx_evex_encoding (void) static INLINE bool is_apx_rex2_encoding (void) { - return i.rex2 || i.rex2_encoding; + return i.rex2 || i.rex2_encoding || i.tm.opcode_modifier.rex2; } static unsigned int diff --git a/gas/testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d b/gas/testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d new file mode 100644 index 00000000000..44e3e96a5df --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d @@ -0,0 +1,14 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 APX_F pushp popp insns (Intel disassembly) +#source: x86-64-apx-pushp-popp.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*d5 08 50[ ]+pushp rax +\s*[a-f0-9]+:\s*d5 19 57[ ]+pushp r31 +\s*[a-f0-9]+:\s*d5 08 58[ ]+popp rax +\s*[a-f0-9]+:\s*d5 19 5f[ ]+popp r31 diff --git a/gas/testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l b/gas/testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l new file mode 100644 index 00000000000..c4d774b9673 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l @@ -0,0 +1,5 @@ +.* Assembler messages: +.*:4: Error: operand size mismatch for `pushp' +.*:5: Error: operand size mismatch for `popp' +.*:6: Error: operand size mismatch for `pushp' +.*:7: Error: operand size mismatch for `popp' diff --git a/gas/testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s b/gas/testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s new file mode 100644 index 00000000000..28ed5d8145a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s @@ -0,0 +1,7 @@ +# Check bytecode of APX_F pushp popp instructions with illegal instructions. + + .text + pushp %eax + popp %eax + pushp (%rax) + popp (%rax) diff --git a/gas/testsuite/gas/i386/x86-64-apx-pushp-popp.d b/gas/testsuite/gas/i386/x86-64-apx-pushp-popp.d new file mode 100644 index 00000000000..b20e5ba9a35 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-pushp-popp.d @@ -0,0 +1,14 @@ +#as: +#objdump: -dw +#name: x86_64 APX_F pushp popp insns +#source: x86-64-apx-pushp-popp.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*d5 08 50[ ]+pushp %rax +\s*[a-f0-9]+:\s*d5 19 57[ ]+pushp %r31 +\s*[a-f0-9]+:\s*d5 08 58[ ]+popp %rax +\s*[a-f0-9]+:\s*d5 19 5f[ ]+popp %r31 diff --git a/gas/testsuite/gas/i386/x86-64-apx-pushp-popp.s b/gas/testsuite/gas/i386/x86-64-apx-pushp-popp.s new file mode 100644 index 00000000000..0ea66d0e70c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-pushp-popp.s @@ -0,0 +1,8 @@ +# Check 64bit APX_F pushp popp instructions + + .text + _start: + pushp %rax + pushp %r31 + popp %rax + popp %r31 diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 8b41f9891a5..74433a20e24 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -348,6 +348,9 @@ run_dump_test "x86-64-avx512dq-rcigrne" run_dump_test "x86-64-apx-push2pop2" run_dump_test "x86-64-apx-push2pop2-intel" run_list_test "x86-64-apx-push2pop2-inval" +run_dump_test "x86-64-apx-pushp-popp" +run_dump_test "x86-64-apx-pushp-popp-intel" +run_list_test "x86-64-apx-pushp-popp-inval" run_dump_test "x86-64-avx512dq-rcigru-intel" run_dump_test "x86-64-avx512dq-rcigru" run_dump_test "x86-64-avx512dq-rcigrz-intel" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index b33b44d7c27..6542e9b81dc 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1931,23 +1931,23 @@ static const struct dis386 dis386[] = { { "dec{S|}", { RMeSI }, 0 }, { "dec{S|}", { RMeDI }, 0 }, /* 50 */ - { "push{!P|}", { RMrAX }, 0 }, - { "push{!P|}", { RMrCX }, 0 }, - { "push{!P|}", { RMrDX }, 0 }, - { "push{!P|}", { RMrBX }, 0 }, - { "push{!P|}", { RMrSP }, 0 }, - { "push{!P|}", { RMrBP }, 0 }, - { "push{!P|}", { RMrSI }, 0 }, - { "push{!P|}", { RMrDI }, 0 }, + { "push!P", { RMrAX }, 0 }, + { "push!P", { RMrCX }, 0 }, + { "push!P", { RMrDX }, 0 }, + { "push!P", { RMrBX }, 0 }, + { "push!P", { RMrSP }, 0 }, + { "push!P", { RMrBP }, 0 }, + { "push!P", { RMrSI }, 0 }, + { "push!P", { RMrDI }, 0 }, /* 58 */ - { "pop{!P|}", { RMrAX }, 0 }, - { "pop{!P|}", { RMrCX }, 0 }, - { "pop{!P|}", { RMrDX }, 0 }, - { "pop{!P|}", { RMrBX }, 0 }, - { "pop{!P|}", { RMrSP }, 0 }, - { "pop{!P|}", { RMrBP }, 0 }, - { "pop{!P|}", { RMrSI }, 0 }, - { "pop{!P|}", { RMrDI }, 0 }, + { "pop!P", { RMrAX }, 0 }, + { "pop!P", { RMrCX }, 0 }, + { "pop!P", { RMrDX }, 0 }, + { "pop!P", { RMrBX }, 0 }, + { "pop!P", { RMrSP }, 0 }, + { "pop!P", { RMrBP }, 0 }, + { "pop!P", { RMrSI }, 0 }, + { "pop!P", { RMrDI }, 0 }, /* 60 */ { X86_64_TABLE (X86_64_60) }, { X86_64_TABLE (X86_64_61) }, @@ -10621,6 +10621,19 @@ putop (instr_info *ins, const char *in_template, int sizeflag) case 'P': if (l == 0) { + /* For pushp and popp, do not print {rex2} for them. */ + if (ins->address_mode == mode_64bit && !cond + && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W)) + { + *ins->obufp++ = 'p'; + ins->rex2 |= 16; + break; + } + + /* If "!p" printis nothing in intel_syntax. */ + if (!cond && ins->intel_syntax) + break; + if ((ins->modrm.mod == 3 || !cond) && !(sizeflag & SUFFIX_ALWAYS)) break; diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 7dab744134f..7efb064b9ca 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -471,6 +471,7 @@ static bitfield opcode_modifiers[] = BITFIELD (IsPrefix), BITFIELD (ImmExt), BITFIELD (NoRex64), + BITFIELD (Rex2), BITFIELD (Vex), BITFIELD (VexVVVV), BITFIELD (VexW), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index edd59dd67ea..575ef123ee6 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -627,6 +627,8 @@ enum ImmExt, /* instruction don't need Rex64 prefix. */ NoRex64, + /* instruction need Rex2 prefix. */ + Rex2, /* insn has VEX prefix: 1: 128bit VEX prefix (or operand dependent). 2: 256bit VEX prefix. @@ -787,6 +789,7 @@ typedef struct i386_opcode_modifier unsigned int isprefix:1; unsigned int immext:1; unsigned int norex64:1; + unsigned int rex2:1; unsigned int vex:2; unsigned int vexvvvv:2; unsigned int vexw:2; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 642e519fe3a..539837e17ab 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -225,6 +225,7 @@ push, 0x68, i186&No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 } push, 0x6, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } // In 64bit mode, the operand size is implicitly 64bit. push, 0x50, x64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } +pushp, 0x50, APX_F, No_bSuf|No_lSuf|No_sSuf|Rex2, {Reg64 } push, 0xff/6, x64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } push, 0x6a, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S } push, 0x68, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S } @@ -238,6 +239,7 @@ pop, 0x8f/0, No64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word pop, 0x7, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg } // In 64bit mode, the operand size is implicitly 64bit. pop, 0x58, x64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 } +popp, 0x58, APX_F, No_bSuf|No_lSuf|No_sSuf|Rex2, { Reg64 } pop, 0x8f/0, x64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } pop, 0xfa1, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }