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Mon, 27 Nov 2023 12:14:28 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ARCERp6014923 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 27 Nov 2023 12:14:27 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 27 Nov 2023 04:14:22 -0800 From: Krishna chaitanya chundru Date: Mon, 27 Nov 2023 17:43:49 +0530 Subject: [PATCH v3 1/3] dt-bindings: phy: qcom,qmp: Add PCIe qcom,refclk-always-on property MIME-Version: 1.0 Message-ID: <20231127-refclk_always_on-v3-1-26d969fa8f1d@quicinc.com> References: <20231127-refclk_always_on-v3-0-26d969fa8f1d@quicinc.com> In-Reply-To: <20231127-refclk_always_on-v3-0-26d969fa8f1d@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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Mon, 27 Nov 2023 04:15:03 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783719324783316408 X-GMAIL-MSGID: 1783719324783316408 Document qcom,refclk-always-on property which is needed in some platforms to supply refclk even in PCIe low power states. Signed-off-by: Krishna chaitanya chundru --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 2c3d6553a7ba..c747c9f35795 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -93,6 +93,13 @@ properties: "#phy-cells": const: 0 + qcom,refclk-always-on: + type: boolean + description: In some platform where PCIe switch is connected, pcie switch due to some design + limitation fails to propage clkreq signal to the host and due to that host will not send + refclk, which results in linkdown in L1.2 or L1.1 exit initiated by EP. + This property if set keeps refclk always on even in Low power states. + required: - compatible - reg From patchwork Mon Nov 27 12:13:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 170106 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp3053974vqx; Mon, 27 Nov 2023 04:15:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IHtcUF7dbiIyCsxlvGkYAoMEsSCB2U+uUUEVMsSlRznS5d+PgUrNWvhFafJB4Qc8V5wGRnn X-Received: by 2002:a05:6a20:3ca5:b0:18b:3158:4231 with SMTP id b37-20020a056a203ca500b0018b31584231mr16946619pzj.16.1701087351031; Mon, 27 Nov 2023 04:15:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701087351; cv=none; d=google.com; s=arc-20160816; b=QOgoizBlYkx/9EL7rFqcLarNHPxrNLM4f8hp8hzPZcR105CeXoj77645ICHGCXckV8 Mh5nQQZeDnyN8/LwE48DZ9pCxvNcwiet8cMgB9w3a3TUvuqtqbjsM6KN20h5oF2qVaPC eY9J5R6jMqqhNNoqybFmVJFz8Dkit+rsWcpQi8bla+zsKBi+Y0V8ypvr0OTg+jpr02Pg iTBz+EdUkuGF/66ftVFChqOHcgO4cTFxmt2POeZgqgDFNHcs/iNbCFVF1UiEqYMlytS8 j0WwLISOcj/m+T7i9yhuKddA0QEN6wk8bM5tIACQoFcugcbjvEjmT+FJQ8LhMat72bs5 R7Eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=Hrl2aH6q5tbRJjwS/p1ZIAlXo3Tyl2J9JqtUC+NcOlg=; fh=qHq3rRh8rkp/HF0tX5GVbz676UBDtNYVqikJv7UmaZ8=; b=lsKrAkACqvGk+XsqyiB31qkl8nsyOcz6LD8NOfm/0TkUkBLFMrcCK+dbNxbAsyRk7R 7tC3KOrLcTv00/Ff9aLJTuxTctq6EFVWWVuCVjB5ovH7we7G5eFtI/jbaI0vTAZ6GMmK ylJS7rwTDfboeqCuYrQ6RhnNsyPuzb9FgQnvhXwPypGualnjG8HkiGJNOOhU88LvtO8Z BcVV3golxN5XM6bUD5/klzAp8vjGvgwSUCdqSa9GA6jxY04W4HLr3iOQH7WatLFn6Wno Xb9rHy3eU8nqQqa0F1Vhn4Cz030ri+xDzaI+UL0suYpyNO/XA/Hcv2ccI2FwrMBr4gyj 0Jig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="YD6B/fVB"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. 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Mon, 27 Nov 2023 12:14:34 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ARCEXGx014992 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 27 Nov 2023 12:14:33 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 27 Nov 2023 04:14:27 -0800 From: Krishna chaitanya chundru Date: Mon, 27 Nov 2023 17:43:50 +0530 Subject: [PATCH v3 2/3] phy: qcom-qmp-pcie: Add endpoint refclk control register offset MIME-Version: 1.0 Message-ID: <20231127-refclk_always_on-v3-2-26d969fa8f1d@quicinc.com> References: <20231127-refclk_always_on-v3-0-26d969fa8f1d@quicinc.com> In-Reply-To: <20231127-refclk_always_on-v3-0-26d969fa8f1d@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , , , , "Krishna chaitanya chundru" , Dmitry Baryshkov X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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Mon, 27 Nov 2023 04:15:16 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783719370130782052 X-GMAIL-MSGID: 1783719370130782052 Some platforms needs to keep endpoint refclk always on, for this purpose add this offset for all the applicable phy versions. And also add reg layout for few controllers as we are adding endpoint refclk control register which changes based upon phy version. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 26 +++++++++++++++++++--- drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h | 4 ++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 4 ++++ 6 files changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index a63ca7424974..7fdf9b2596b6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -77,6 +77,7 @@ enum qphy_reg_layout { QPHY_START_CTRL, QPHY_PCS_STATUS, QPHY_PCS_POWER_DOWN_CONTROL, + QPHY_PCS_ENDPOINT_REFCLK_CNTRL, /* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE }; @@ -93,6 +94,7 @@ static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V3_PCS_ENDPOINT_REFCLK_CNTRL, }; static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { @@ -107,6 +109,7 @@ static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL, }; static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { @@ -114,6 +117,23 @@ static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_CNTRL, +}; + +static const unsigned int pciephy_v5_20_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V5_20_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V5_20_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V5_20_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_20_PCS_POWER_DOWN_CONTROL, + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_CNTRL, +}; + +static const unsigned int pciephy_v6_20_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V6_20_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V6_20_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V6_20_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_20_PCS_POWER_DOWN_CONTROL, + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_CNTRL, }; static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { @@ -2956,7 +2976,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v5_20_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, @@ -3012,7 +3032,7 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = sm8550_qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v6_20_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, @@ -3047,7 +3067,7 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v5_20_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h index a469ae2a10a1..9b166286afda 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h @@ -11,6 +11,7 @@ #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x24 #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h index cdf8c04ea078..8b114e538a07 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h @@ -9,6 +9,7 @@ /* Only for QMP V5_20 PHY - PCIe PCS registers */ #define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x020 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h index e3eb08776339..f7abe95c49ad 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h @@ -10,6 +10,7 @@ #define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c #define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018 #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_CNTRL 0x020 #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h index f0754b6f9e3a..96f9232214d7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h @@ -6,6 +6,10 @@ #ifndef QCOM_PHY_QMP_PCS_V5_20_H_ #define QCOM_PHY_QMP_PCS_V5_20_H_ +#define QPHY_V5_20_PCS_SW_RESET 0x000 +#define QPHY_V5_20_PCS_PCS_STATUS1 0x014 +#define QPHY_V5_20_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V5_20_PCS_START_CONTROL 0x044 #define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170 #define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188 #define QPHY_V5_20_PCS_EQ_CONFIG2 0x1d8 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h index 9c3f1e4950e6..cc3d40badb5d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h @@ -7,6 +7,10 @@ #define QCOM_PHY_QMP_PCS_V6_20_H_ /* Only for QMP V6_20 PHY - USB/PCIe PCS registers */ +#define QPHY_V6_20_PCS_SW_RESET 0x000 +#define QPHY_V6_20_PCS_PCS_STATUS1 0x014 +#define QPHY_V6_20_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V6_20_PCS_START_CONTROL 0x044 #define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178 #define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190 #define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8 From patchwork Mon Nov 27 12:13:51 2023 Content-Type: text/plain; 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Mon, 27 Nov 2023 04:15:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783719369669573913 X-GMAIL-MSGID: 1783719369669573913 In PCIe low power states like L1.1 or L1.2 the phy will stop supplying refclk to endpoint. If endpoint asserts clkreq to bring back link L0, then RC needs to provide refclk to endpoint. Some platforms with pcie switch fail to drive the clkreq signal to the host from the endpoints because of the switch board design. Due to that refclk needs to supplied to the endpoint always. Add a flag to keep refclk always supplied to endpoint. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 7fdf9b2596b6..e95f677817f7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -43,6 +43,8 @@ /* QPHY_PCS_STATUS bit */ #define PHYSTATUS BIT(6) #define PHYSTATUS_4_20 BIT(7) +/* PCS_PCIE_ENDPOINT_REFCLK_CNTRL */ +#define EPCLK_ALWAYS_ON_EN BIT(6) #define PHY_INIT_COMPLETE_TIMEOUT 10000 @@ -2264,6 +2266,8 @@ struct qmp_pcie { struct phy *phy; int mode; + bool refclk_always_on; + struct clk_fixed_rate pipe_clk_fixed; }; @@ -3179,6 +3183,10 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); + if (qmp->refclk_always_on && cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL]) + qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL], + EPCLK_ALWAYS_ON_EN); + if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); qmp_pcie_init_port_b(qmp, tbls); @@ -3701,6 +3709,12 @@ static int qmp_pcie_probe(struct platform_device *pdev) if (ret) goto err_node_put; + qmp->refclk_always_on = of_property_read_bool(dev->of_node, "qcom,refclk-always-on"); + if (qmp->refclk_always_on && !qmp->cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL]) { + dev_err(dev, "refclk is always on is present but refclk cntrl offset is not present\n"); + goto err_node_put; + } + ret = phy_pipe_clk_register(qmp, np); if (ret) goto err_node_put;