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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id c10-20020a05622a024a00b00423a4bd9b4csi2924273qtx.240.2023.11.26.01.14.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 01:14:33 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F169738582B4 for ; Sun, 26 Nov 2023 09:14:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id 56E843858D20 for ; Sun, 26 Nov 2023 09:14:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 56E843858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 56E843858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.92.39.34 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700990046; cv=none; b=a7WyczRWrNE5PX5C/vM7vEqlUZtCJfjoW+x0mCU40D3eF6euVvHQdAGe4RFKzcjaIKPJ4iIbiRukdsTJEoUVXfz2SUQza9fqvEp/+njEcb5vlVluONrMn45V5x/r7Lr2BO6qrpw/16DLqiYTxGd5jI2z83XrbBykhHUgtpuoask= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700990046; c=relaxed/simple; bh=IzVVb0dMeRsu8roiR5o5ih+IL7U/PuagCzlESZTHlts=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=nnhjvjmi9P03Hdm2uA22ba1FO47ISvcUAjbr/RTf8Z7L6iEMsmcsyXwW6GZdRtF1qQan4lRB8WN3ELX31XObJriTLFXyZkzTB+A8WPxMaq+AsO5D2YTZk/0YqJNpwzGFlK9XzpU3zaIyrWoEo50iY9Cxd08dZQSgs0YQVUSTsYc= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp86t1700990038td6bggoi Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 26 Nov 2023 17:13:57 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: CR3LFp2JE4k+H6FE3sose+VIyjMISDMFlD338z4miVXBr6VVNvSfIjSjyvBgl BlyRti7369o4ANZ0rZXp4vJIEJxK9pgmAonsWqP+XLO724ES6d7hRtpWbXHBVI5a2Oh+teW tvO6rFneMGGqhotxAsUlyNTGyvxb0/IyrOcf84klOl42+KjRxS2X4CDUdjCH3Ru8xaoSjAZ R1Ghp/W82mxdWKkPHE1yrsZfg30SnF1ovTroGxp+OxKw2edASv/EWU46iPrSwFYuxLwDpmm IMC9WfBq1cgwUKUfZSG+21Xc/XXEkLiTZg16HJrQy9OLZgWMk0ZmLojXt2gmpqJ4x+LAz6U wtwLuUKV3tF/bqd2/q68FDsmbsQA/l8jKBN24P+uJPw5GXEHY/01fLqte/H89DFiQpWs21o X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5188715533879290868 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Disable AVL propagation of slidedown instructions Date: Sun, 26 Nov 2023 17:13:55 +0800 Message-Id: <20231126091355.2309349-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783617367660886371 X-GMAIL-MSGID: 1783617367660886371 Re-check again RVV ISA, I find that we can't allow AVL propagation not only for vrgather, but also slidedown instructions. Committed. PR target/112599 gcc/ChangeLog: * config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p): Add slidedown. (vlmax_ta_p): Ditto. (pass_avlprop::get_vlmax_ta_preferred_avl): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vf_avl-1.c: Adapt test. * gcc.target/riscv/rvv/autovec/pr112599-3.c: New test. --- gcc/config/riscv/riscv-avlprop.cc | 26 ++++++++++++++----- .../gcc.target/riscv/rvv/autovec/pr112599-3.c | 14 ++++++++++ .../gcc.target/riscv/rvv/base/vf_avl-1.c | 2 +- 3 files changed, 35 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc index 7a741c25d2b..d298f0ea456 100644 --- a/gcc/config/riscv/riscv-avlprop.cc +++ b/gcc/config/riscv/riscv-avlprop.cc @@ -108,17 +108,29 @@ avlprop_type_to_str (enum avlprop_type type) static bool avl_can_be_propagated_p (rtx_insn *rinsn) { - /* The index of "vrgather dest, source, index" may pick up the - element which has index >= AVL, so we can't strip the elements - that has index >= AVL of source register. */ - return get_attr_type (rinsn) != TYPE_VGATHER; + /* We can't do AVL propagation when the instruction is potentially + touching the element with i > AVL. So, we don't do AVL propagation + on these following situations: + + - The index of "vrgather dest, source, index" may pick up the + element which has index >= AVL, so we can't strip the elements + that has index >= AVL of source register. + - The last element of vslide1down is AVL + 1 according to RVV ISA: + vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled + - The last multiple elements of vslidedown can be the element + has index >= AVL according to RVV ISA: + 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET] + vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled. */ + return get_attr_type (rinsn) != TYPE_VGATHER + && get_attr_type (rinsn) != TYPE_VSLIDEDOWN + && get_attr_type (rinsn) != TYPE_VISLIDE1DOWN + && get_attr_type (rinsn) != TYPE_VFSLIDE1DOWN; } static bool vlmax_ta_p (rtx_insn *rinsn) { - return vlmax_avl_type_p (rinsn) && tail_agnostic_p (rinsn) - && avl_can_be_propagated_p (rinsn); + return vlmax_avl_type_p (rinsn) && tail_agnostic_p (rinsn); } static machine_mode @@ -271,6 +283,8 @@ pass_avlprop::get_preferred_avl ( rtx pass_avlprop::get_vlmax_ta_preferred_avl (insn_info *insn) const { + if (!avl_can_be_propagated_p (insn->rtl ())) + return NULL_RTX; int sew = get_sew (insn->rtl ()); enum vlmul_type vlmul = get_vlmul (insn->rtl ()); int ratio = calculate_ratio (sew, vlmul); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c new file mode 100644 index 00000000000..0954fe2b2c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */ + +#include "riscv_vector.h" + +typedef int64_t v1024b __attribute__ ((vector_size (128))); + +void foo (void *out, void *in, int64_t a, int64_t b, int64_t c, int64_t d, int64_t e) +{ + v1024b v = {a,a,a,a,a,a,a,a,a,a,a,a,b,c,d,e}; + __riscv_vse64_v_i64m1 (out, (vint64m1_t)v, 12); +} + +/* { dg-final { scan-assembler {vsetivli\s+zero,\s*16} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c index 11adf6bc611..8f352db6533 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c @@ -12,4 +12,4 @@ f_vnx2qi (int8_t a, int8_t b, int8_t *out) *(vnx2qi *) out = v; } -/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler {vsetivli\s+zero,\s*2,\s*e8,\s*mf8,\s*t[au],\s*m[au]} } } */