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Sun, 26 Nov 2023 06:08:12 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AQ68Bjr024717 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 26 Nov 2023 06:08:11 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sat, 25 Nov 2023 22:08:08 -0800 From: Luo Jie To: , , , , , , , , , , CC: , , , Subject: [PATCH v6 1/6] net: phy: introduce core support for phy-mode = "10g-qxgmii" Date: Sun, 26 Nov 2023 14:07:27 +0800 Message-ID: <20231126060732.31764-2-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231126060732.31764-1-quic_luoj@quicinc.com> References: <20231126060732.31764-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: JzRJMIuZJo6YtC49rq-3y7mMx2pOmLBA X-Proofpoint-GUID: JzRJMIuZJo6YtC49rq-3y7mMx2pOmLBA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-26_04,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311260042 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Sat, 25 Nov 2023 22:08:54 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783605690660174997 X-GMAIL-MSGID: 1783605690660174997 From: Vladimir Oltean 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport specification. It uses the same signaling as USXGMII, but it multiplexes 4 ports over the link, resulting in a maximum speed of 2.5G per port. Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean either the single-port USXGMII or the quad-port 10G-QXGMII variant, and they could get away just fine with that thus far. But there is a need to distinguish between the 2 as far as SerDes drivers are concerned. Signed-off-by: Vladimir Oltean Signed-off-by: Luo Jie --- Documentation/networking/phy.rst | 6 ++++++ drivers/net/phy/phy-core.c | 1 + drivers/net/phy/phylink.c | 11 +++++++++-- include/linux/phy.h | 4 ++++ include/linux/phylink.h | 2 ++ 5 files changed, 22 insertions(+), 2 deletions(-) diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst index 1283240d7620..f64641417c54 100644 --- a/Documentation/networking/phy.rst +++ b/Documentation/networking/phy.rst @@ -327,6 +327,12 @@ Some of the interface modes are described below: This is the Penta SGMII mode, it is similar to QSGMII but it combines 5 SGMII lines into a single link compared to 4 on QSGMII. +``PHY_INTERFACE_MODE_10G_QXGMII`` + Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII + Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz + SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved + through symbol replication. The PCS expects the standard USXGMII code word. + Pause frames / flow control =========================== diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 966c93cbe616..1cd58723d6d0 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interface_t interface) return 1; case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 4; case PHY_INTERFACE_MODE_PSGMII: return 5; diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index c276f9482f78..803251299342 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -218,6 +218,7 @@ static int phylink_interface_max_speed(phy_interface_t interface) return SPEED_1000; case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_10G_QXGMII: return SPEED_2500; case PHY_INTERFACE_MODE_5GBASER: @@ -487,7 +488,11 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface, switch (interface) { case PHY_INTERFACE_MODE_USXGMII: - caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD; + caps |= MAC_10000FD | MAC_5000FD; + fallthrough; + + case PHY_INTERFACE_MODE_10G_QXGMII: + caps |= MAC_2500FD; fallthrough; case PHY_INTERFACE_MODE_RGMII_TXID: @@ -905,6 +910,7 @@ static int phylink_parse_mode(struct phylink *pl, phylink_set(pl->supported, 25000baseSR_Full); fallthrough; case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER: phylink_set(pl->supported, 10baseT_Half); @@ -1777,7 +1783,8 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy, if (phy->is_c45 && config.rate_matching == RATE_MATCH_NONE && interface != PHY_INTERFACE_MODE_RXAUI && interface != PHY_INTERFACE_MODE_XAUI && - interface != PHY_INTERFACE_MODE_USXGMII) + interface != PHY_INTERFACE_MODE_USXGMII && + interface != PHY_INTERFACE_MODE_10G_QXGMII) config.interface = PHY_INTERFACE_MODE_NA; else config.interface = interface; diff --git a/include/linux/phy.h b/include/linux/phy.h index e5f1f41e399c..b4ea3fa172a2 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -125,6 +125,7 @@ extern const int phy_10gbit_features_array[1]; * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN + * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII * @PHY_INTERFACE_MODE_MAX: Book keeping * * Describes the interface between the MAC and PHY. @@ -165,6 +166,7 @@ typedef enum { PHY_INTERFACE_MODE_10GKR, PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_1000BASEKX, + PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -286,6 +288,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "100base-x"; case PHY_INTERFACE_MODE_QUSGMII: return "qusgmii"; + case PHY_INTERFACE_MODE_10G_QXGMII: + return "10g-qxgmii"; default: return "unknown"; } diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 875439ab45de..92bd2726cc8a 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -128,6 +128,7 @@ static inline unsigned int phylink_pcs_neg_mode(unsigned int mode, case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: /* These protocols are designed for use with a PHY which * communicates its negotiation result back to the MAC via * inband communication. Note: there exist PHYs that run @@ -680,6 +681,7 @@ static inline int phylink_get_link_timer_ns(phy_interface_t interface) case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 1600000; case PHY_INTERFACE_MODE_1000BASEX: From patchwork Sun Nov 26 06:07:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 169836 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp2317966vqx; Sat, 25 Nov 2023 22:09:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IH8YboMdHCITZ4gK7fAboPwBaYziYcRWdMQ0JUicPy34ldXLN6jt0OnCJboXtHdsMtcEcna X-Received: by 2002:a05:6e02:388a:b0:35c:5131:cc9f with SMTP id cn10-20020a056e02388a00b0035c5131cc9fmr8542752ilb.23.1700978955686; Sat, 25 Nov 2023 22:09:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700978955; cv=none; d=google.com; s=arc-20160816; b=dHtA9uP0sPpQqqWV67KhpiM8tZeg+K77a1TFYeGdqMRwjgeO3pnoS1iq2jgffOe9+v o/IsTEqZL6mmoVEDlctmsV0B+NFYlDAtpkrHQHye4VBrEIWsB8u0r2VGoM8bta5deOkQ qszIXyBJHO6FjneT8Oxr56ILS0g7IKaWB4q5l+wyEHfN7ytn9JslwAYdrnlvI6i3Dhth nAZsU1qz7hh1Mxccfhgfu+goTxOjEPuaRRWD1Iydb50jr22df/YFrvM3VIyKzQpGKsdM uuylGC7jgVvnO7hAdqQdTNYh/ozdvG1oFR+i8bEf0iDstaz89ibk7Ft5zfh35fSjlLOp V7Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fJ0kPUacM0+GFovGU/9ppRTUtY56F7LcUFW0ZWXHPxY=; fh=YX1qdW4MCOBz7ZI1DJMJ5bNVJMf0IEEa1K+kdZVRewc=; b=tP7aWVci1wgFXo/zYNmm8tSVlDtuE6bfGSWgAeNthDx5wSF9zr+ICUKBV2p9OL9FRn P/2oz519FG3kHcPppriqzwzZpnE787zrQqvDIpxdbUxNfvb5f1hPPSCagQtf8FqygAtG hq6AxDWK2TsYmNRYrqjH2MNezBgeM20qi8og9DxdNnSm541NrcF4ZsHOWe9jS9IAoTfx L/NZ4CpM7x/DOygfL4Svqyp+ppiPMdC9HsRRZ4Tl7vMi9m/at7//f03zawc7V8pz8SvZ gbdJi3My/MR86A+XY0ucJqflbRbD5a09PeX7+EOaYdDsSSNRGEzLmy/hAzbfhHNypd9K y/Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=FO4087Ov; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. 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Sat, 25 Nov 2023 22:09:14 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783605709482101315 X-GMAIL-MSGID: 1783605709482101315 From: Vladimir Oltean Add the new interface mode 10g-qxgmii, which is similar to usxgmii but extend to 4 channels to support maximum of 4 ports with the link speed 10M/100M/1G/2.5G. Signed-off-by: Vladimir Oltean Signed-off-by: Luo Jie Acked-by: Conor Dooley Reviewed-by: Andrew Lunn --- Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index d14d123ad7a0..0ef6103c5fd8 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -104,6 +104,7 @@ properties: - usxgmii - 10gbase-r - 25gbase-r + - 10g-qxgmii phy-mode: $ref: "#/properties/phy-connection-type" From patchwork Sun Nov 26 06:07:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 169834 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp2317937vqx; Sat, 25 Nov 2023 22:09:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IGQQXIzb7IxIo2iFvETbQCVyONWJoGM+yaJzTvKh5pV0ZGudj4pmVKCpYXXh4ZbT+/60bqn X-Received: by 2002:a17:902:ac86:b0:1cf:c3fb:a75f with SMTP id h6-20020a170902ac8600b001cfc3fba75fmr1290328plr.17.1700978950821; Sat, 25 Nov 2023 22:09:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700978950; cv=none; d=google.com; s=arc-20160816; b=hyePTJ/ok0BrVhfSPJh+HlG7Ec9P56OVry5iLZ9JxQtv8VV22VNrKtllC50dVY/Zl+ HcpJda1DxQXLIy6hw8lrKnpAZGlQgxXwM8VON/GRurfMADbnta8JTB7ItA+fHwmRf+TX 1VMrdqEC1hsDLlcAOy+sZnlAmL3nvh8Pj3E0Mv9OJjYoeljIjXmOjVILDoSFC3Ffhw9V ae56CLi1gdOz43a1vKi3wGyHtaCy/51i8SRKCSOQP4Ug2sRH8LaIccV/431uqOLeF+PV ucIW2JHbRpP4a4V6rOHMRGbjzCmjImW+o8JL/aO4WlDO+o91f9lb1xa02raPkHC2fKTV Ln9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mGAPiwQH9ZnwXhYA9V18stSSqTp0PD6Oex4u6WDgTkU=; fh=CzJZH1Mq0+1gFor3WuKjwLRRL9rPD0zvQs0go/fRLgA=; b=z5wyfRWIU44YeIFDUkxEXvTP0C+YcZs0vh9YfJ9gT4EV6JhLf7NmYPHHwQ9aN3Ns4s 1/cmv0p8VDsD/icUF8ViR3pW/XiyAxzDiwkgFaQkrG3RYGjmx3pWMlyBVNBdrLi1a33k CVIayniCzI/n+UN+iyDPciyQVfpGpHUUl9rYT39AV/i+qUhZz8C3qU2Bba3NMoq5WLzi M09urxb2CBxwFV4oL3fA9fJoP0F9L68+ztj6z0naeUl5Tu6fo5JGLazh5rM2y3BUPyTP EbUm1+Jc5UvKQ5IrzbM1OxP9qswJTHoiFnbWu14Hlk+5gQnGRdeKOVQguErWR6osh+C6 RKWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=FMvBQqNQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from agentk.vger.email (agentk.vger.email. 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Sat, 25 Nov 2023 22:09:06 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783605704357188411 X-GMAIL-MSGID: 1783605704357188411 Add qca8084 PHY support, which is four-port PHY with maximum link capability 2.5G, the features of each port is almost same as QCA8081 and slave seed config is not needed. Three kind of interface modes supported by qca8084. PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_2500BASEX and PHY_INTERFACE_MODE_SGMII. The PCS(serdes) and clock are also needed to be configured to bringup qca8084 PHY, which will be added in the pcs driver. The additional CDT configurations used for qca8084. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 50 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 37fb033e1c29..f376d794d170 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -176,6 +176,7 @@ #define AT8030_PHY_ID_MASK 0xffffffef #define QCA8081_PHY_ID 0x004dd101 +#define QCA8084_PHY_ID 0x004dd180 #define QCA8327_A_PHY_ID 0x004dd033 #define QCA8327_B_PHY_ID 0x004dd034 @@ -1760,6 +1761,9 @@ static bool qca808x_is_prefer_master(struct phy_device *phydev) static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) { + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) + return false; + return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); } @@ -1824,6 +1828,23 @@ static int qca808x_read_status(struct phy_device *phydev) return ret; if (phydev->link) { + /* There are two PCSs available for QCA8084, which support the + * following interface modes. + * + * 1. PHY_INTERFACE_MODE_10G_QXGMII utilizes PCS1 for all + * available 4 ports, which is for all link speeds. + * + * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the + * fourth port, which is only for the link speed 2500M same + * as QCA8081. + * + * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth + * port, which is for the link speed 10M, 100M and 1000M same + * as QCA8081. + */ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + return 0; + if (phydev->speed == SPEED_2500) phydev->interface = PHY_INTERFACE_MODE_2500BASEX; else @@ -1958,6 +1979,14 @@ static int qca808x_cable_test_start(struct phy_device *phydev) phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) { + /* Adjust the positive and negative pulse thereshold of CDT */ + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8075, 0xa060); + + /* Disable the near echo bypass */ + phy_modify_mmd(phydev, MDIO_MMD_PCS, 0x807f, BIT(15), 0); + } + return 0; } @@ -2227,6 +2256,26 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .link_change_notify = qca808x_link_change_notify, +}, { + /* Qualcomm QCA8084 */ + PHY_ID_MATCH_MODEL(QCA8084_PHY_ID), + .name = "Qualcomm QCA8084", + .flags = PHY_POLL_CABLE_TEST, + .probe = at803x_probe, + .config_intr = at803x_config_intr, + .handle_interrupt = at803x_handle_interrupt, + .get_tunable = at803x_get_tunable, + .set_tunable = at803x_set_tunable, + .set_wol = at803x_set_wol, + .get_wol = at803x_get_wol, + .get_features = qca808x_get_features, + .config_aneg = at803x_config_aneg, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_status = qca808x_read_status, + .soft_reset = qca808x_soft_reset, + .cable_test_start = qca808x_cable_test_start, + .cable_test_get_status = qca808x_cable_test_get_status, }, }; module_phy_driver(at803x_driver); @@ -2242,6 +2291,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = { { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, + { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID) }, { } }; From patchwork Sun Nov 26 06:07:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 169832 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp2317873vqx; Sat, 25 Nov 2023 22:08:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IFvqqEb6xAbnp8pl6xFkLKUDdHIzJABcM1Rf4udhXFFyq5pgJMwKWVub/nRIdNr44N7//KS X-Received: by 2002:a05:6808:3c99:b0:3b5:8586:b17e with SMTP id gs25-20020a0568083c9900b003b58586b17emr5128559oib.52.1700978939645; Sat, 25 Nov 2023 22:08:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700978939; cv=none; d=google.com; s=arc-20160816; b=cLbqWeldp/JQRUSlAbUpB+LRadWgr8nY2PXxXIkIR6YfcTTP60MO1faw0KBKCmOIp9 Xw7ERo+NkhXYqnAePkXJ21+Abi4h6EZbsebDs9fG5vumqJ9fpn9yi0z+5D1+XLw3k9vV NQs5itKJabD9BAmojT97IoDNnr8lpwE5gRYTxDi9udsGPTRGeonkWnDcNJKUVyJ8WA+o ruVsQjSj/GGlFacqmcvLcg9KOg/BFYbvt6FCCvw3wOIsTfnc4uEixcNtEhjT7F6bXMsh V4Z4EtcZqHMnDuKXpc9AH/mKebwoYbESq9WTcO/23apq49BWE+2wQY9Y9PKXxWtCaaTA gLBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=SGKuNtLiEI9lSbymQ62ComQ7nNr0WmS8+Wf4Jy0hCRg=; fh=CzJZH1Mq0+1gFor3WuKjwLRRL9rPD0zvQs0go/fRLgA=; b=L6tNx2u9IcOcuYFOYxWlh5c5Rtn8nf9qY34SH0LL2RrQhMRWdlRgJ4uueEcjqSPKjg f0zXRWm4AQsxeHE7z/vQc0pk4aT065JtNA3VqrHNbgFewQjK+5CQhPC73BqIl6qR5+dl qUTdypNkT9myBiwOVSfT7sdVp7g8NwawOhCjcGOgcmz59AJEuGx8klecXBWb9pWJSmzx OL0qUURFJ4M4vn1gUKubNxhyQEh692BnWHp95xnuXYf3OMrZEFvGi9cpHDHzgvDdh1yy s+DrNzV42Q1EwYTZJ1g3qbWnpGLakHYWkYEZIwbH0+z3iGBkzp6fUO6SHGdrPWEkdWbl bHIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=eh1spQAw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from howler.vger.email (howler.vger.email. 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Sat, 25 Nov 2023 22:08:54 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783605692884434621 X-GMAIL-MSGID: 1783605692884434621 The function phydev_id_is_qca808x is applicable to the PHY qca8081 and qca8084. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index f376d794d170..430547f304f7 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -1165,6 +1165,12 @@ static void at803x_link_change_notify(struct phy_device *phydev) } } +static bool phydev_id_is_qca808x(struct phy_device *phydev) +{ + return phydev_id_compare(phydev, QCA8081_PHY_ID) || + phydev_id_compare(phydev, QCA8084_PHY_ID); +} + static int at803x_read_specific_status(struct phy_device *phydev) { int ss; @@ -1184,8 +1190,8 @@ static int at803x_read_specific_status(struct phy_device *phydev) if (sfc < 0) return sfc; - /* qca8081 takes the different bits for speed value from at803x */ - if (phydev->drv->phy_id == QCA8081_PHY_ID) + /* qca808x takes the different bits for speed value from at803x */ + if (phydev_id_is_qca808x(phydev)) speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); else speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); @@ -1316,7 +1322,7 @@ static int at803x_config_aneg(struct phy_device *phydev) */ ret = 0; - if (phydev->drv->phy_id == QCA8081_PHY_ID) { + if (phydev_id_is_qca808x(phydev)) { int phy_ctrl = 0; /* The reg MII_BMCR also needs to be configured for force mode, the @@ -1470,8 +1476,8 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair) { u16 cdt; - /* qca8081 takes the different bit 15 to enable CDT test */ - if (phydev->drv->phy_id == QCA8081_PHY_ID) + /* qca808x takes the different bit 15 to enable CDT test */ + if (phydev_id_is_qca808x(phydev)) cdt = QCA808X_CDT_ENABLE_TEST | QCA808X_CDT_LENGTH_UNIT | QCA808X_CDT_INTER_CHECK_DIS; @@ -1487,7 +1493,7 @@ static int at803x_cdt_wait_for_completion(struct phy_device *phydev) int val, ret; u16 cdt_en; - if (phydev->drv->phy_id == QCA8081_PHY_ID) + if (phydev_id_is_qca808x(phydev)) cdt_en = QCA808X_CDT_ENABLE_TEST; else cdt_en = AT803X_CDT_ENABLE_TEST; From patchwork Sun Nov 26 06:07:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 169835 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp2317948vqx; Sat, 25 Nov 2023 22:09:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IGG0bawO2ODQwa1/4TaUFVg81d0TX4Ohhmq6/F9oJ/ez2wU++Ib8IM6iGWL8MlrrtVUzgr4 X-Received: by 2002:a05:6870:46a7:b0:1fa:1355:da45 with SMTP id a39-20020a05687046a700b001fa1355da45mr7834299oap.11.1700978953491; Sat, 25 Nov 2023 22:09:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700978953; cv=none; d=google.com; s=arc-20160816; b=FKlFujBntkec4BFD9KHlSy1b7XNtkVIe3hHNxf6Yrunws/2fgdyzAQKV6ooJrw6Nqy GYveHzGYPeEVvFszQv6wXzotFlPqnzQ/J5kkzxJmYlcZA75418aD865EuXhLhyai4tQD 7bBoGdq7/A7V6/ximvq0Z6kRlg4DU+8O4R8O9CIYQK1mW/FQVsNPB+tMsaPvQhTCr8QR TQHlKmkE6UzDdHZybWTW5kl7+muCvj+Us09qZHM86J9XQ70SeWVeJy8xviJpi8r+G9Va PTzlQWAkZa/8+BttCme+9P89tQsUoTXk02TLQYkKtTOgVLt3wP6svgtv061v5ZoHd0c4 qIRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lS/O/ANo9EsSWeo3/3mKUSbDHP/ElCBmzowwBa2lrmI=; fh=CzJZH1Mq0+1gFor3WuKjwLRRL9rPD0zvQs0go/fRLgA=; b=sGxCDbtYGybdofecq7i8NtX7wCZTva6IKVfu0rAz7IqX2IhhMhAS9ko1V5Xam+NB8l Ifgo67yxnrYa2kOa2tZFy66h+jKR7TgkFIH2DpdjOgQR9koi79ZBWs1l2X1liN7pVL31 XstHyt8ib81teEK01cIQOGIlhx4IjCDAGXERYp44bCfmGos10LejXjjiTYvBY0aN5oqG g3/5RPNbWL8VUeqTQY/OWpm3bSSQE928OO5twWIy0LI2nAkUAYpj5d2895M39xwhg9pj 2keCMQcTfNmurHR9VmkLy/X0RmERUGHtWNVbtIXVZ4vDCI7uyzpqOUb9uSWcXMBwBuRH LuWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Cf3GnrnN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. 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Sat, 25 Nov 2023 22:09:11 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783605707176803441 X-GMAIL-MSGID: 1783605707176803441 Configure MSE detect threshold and ADC clock edge invert. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 430547f304f7..c0d5d4410e89 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -280,6 +280,15 @@ #define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 #define QCA8081_PHY_FIFO_RSTN BIT(11) +/* QCA8084 ADC clock edge */ +#define QCA8084_ADC_CLK_SEL 0x8b80 +#define QCA8084_ADC_CLK_SEL_ACLK GENMASK(7, 4) +#define QCA8084_ADC_CLK_SEL_ACLK_FALL 0xf +#define QCA8084_ADC_CLK_SEL_ACLK_RISE 0x0 + +#define QCA8084_MSE_THRESHOLD 0x800a +#define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -2085,6 +2094,26 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static int qca8084_config_init(struct phy_device *phydev) +{ + int ret; + + /* Invert ADC clock edge */ + ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL, + QCA8084_ADC_CLK_SEL_ACLK, + FIELD_PREP(QCA8084_ADC_CLK_SEL_ACLK, + QCA8084_ADC_CLK_SEL_ACLK_FALL)); + if (ret < 0) + return ret; + + /* Adjust MSE threshold value to avoid link issue with + * some link partner. + */ + return phy_write_mmd(phydev, MDIO_MMD_PMAPMD, + QCA8084_MSE_THRESHOLD, + QCA8084_MSE_THRESHOLD_2P5G_VAL); +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2282,6 +2311,7 @@ static struct phy_driver at803x_driver[] = { .soft_reset = qca808x_soft_reset, .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, + .config_init = qca8084_config_init, }, }; module_phy_driver(at803x_driver); From patchwork Sun Nov 26 06:07:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 169833 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp2317899vqx; Sat, 25 Nov 2023 22:09:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IEwPNjPdQeQWZHN1+DSBYD0TLPh/LlWjEG4ZlSQ76oxUVc0hmQaD3mbIEKg1oKnEoT4UYvQ X-Received: by 2002:a17:90b:1b44:b0:285:b0fa:f7c6 with SMTP id nv4-20020a17090b1b4400b00285b0faf7c6mr2920930pjb.10.1700978944966; Sat, 25 Nov 2023 22:09:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700978944; cv=none; d=google.com; s=arc-20160816; b=JQVssvLL0yHK07xniCf4Ci0zxdN/TxuyzUgi+brhz6el5CB9J/HqbSt6vPijx0SPgn cAKfvX3huYu+QcSxSBqTYH4za0zPz9LCSbni9/cfVk1et1bBqbS+7dIYz0Br5KX3YA1K 3hdpv3NzCa3ckarLC5iT5OCe8Ej32hFtoJ8tZgjtJHYzvoswiWeSxEXgQNGmSQcqMwEz SeyE9vzkMwqCuSLz8V/osfkBhweC40OWSNSO+AQvSNKU401YyYWXV5+Ms77GSEOQJb+J nWLDt8tSADvlbjWP2k9F90PRzGN6XNeJIrvrvKunHS4ZLIerZvkykK6RMe1wihfl9HyO LEbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YAEbePQjuOtIFFbxRz6vCXEReg9DSyCnUSz57STbWpI=; fh=CzJZH1Mq0+1gFor3WuKjwLRRL9rPD0zvQs0go/fRLgA=; b=dAjcgxVwmXKEnE/Tzprf7oTsxInLTaPnHA+FYBGVI4m0ZI7YfTym/fmWzPSjLI4hRg 87V+0C7kwEUyfh5m7UtE6Aa+dbvhotOydDZ0Byqzp5iWqBLn9fPszlBL5IgaQUFZwsDi 8pIpxJymctc8IKDT3kbb2msR5wm9YfRgLntMAxb9kZVaGC+xPT0ivob7qYGachFMAEFu Nj5j4UCqcRrZuUc/QqgQpi0JKn+XfG2vtLi+09+1WiiLngimj740VvjwsCJZyM/M0zEV qqFTPX//Dwpmvq9xbK9tM6Aj8j6DSTyg+e9Te/KqSMGNh7fP2s58S3GKQE+deIojvrAG gcDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=h+E6KtW6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. 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Sun, 26 Nov 2023 06:08:30 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AQ68TrZ003642 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 26 Nov 2023 06:08:29 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sat, 25 Nov 2023 22:08:25 -0800 From: Luo Jie To: , , , , , , , , , , CC: , , , Subject: [PATCH v6 6/6] net: phy: qca8084: add qca8084_link_change_notify Date: Sun, 26 Nov 2023 14:07:32 +0800 Message-ID: <20231126060732.31764-7-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231126060732.31764-1-quic_luoj@quicinc.com> References: <20231126060732.31764-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 44VO1U_gIfGcxZmiOIaLIQBDBnZ02dpa X-Proofpoint-GUID: 44VO1U_gIfGcxZmiOIaLIQBDBnZ02dpa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-26_04,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 phishscore=0 malwarescore=0 mlxscore=0 adultscore=0 clxscore=1015 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311260042 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Sat, 25 Nov 2023 22:09:04 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783605698249992909 X-GMAIL-MSGID: 1783605698249992909 When the link is changed, qca8084 needs to do the fifo reset and adjust the IPG level for the qusgmii link speed 1000M. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index c0d5d4410e89..16ea022744ce 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -289,6 +289,13 @@ #define QCA8084_MSE_THRESHOLD 0x800a #define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 +#define QCA8084_FIFO_CONTROL 0x19 +#define QCA8084_FIFO_MAC_2_PHY BIT(1) +#define QCA8084_FIFO_PHY_2_MAC BIT(0) + +#define QCA8084_MMD7_IPG_OP 0x901d +#define QCA8084_IPG_10_TO_11_EN BIT(0) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -2114,6 +2121,39 @@ static int qca8084_config_init(struct phy_device *phydev) QCA8084_MSE_THRESHOLD_2P5G_VAL); } +static void qca8084_link_change_notify(struct phy_device *phydev) +{ + int ret; + + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, + QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC, + 0); + if (ret) + return; + + /* If the PHY works on PHY_INTERFACE_MODE_10G_QXGMII mode, the fifo + * needs to be kept as reset state in link down status. + */ + if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII || + phydev->link) { + msleep(50); + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, + QCA8084_FIFO_MAC_2_PHY | + QCA8084_FIFO_PHY_2_MAC, + QCA8084_FIFO_MAC_2_PHY | + QCA8084_FIFO_PHY_2_MAC); + if (ret) + return; + } + + /* Enable IPG 10 to 11 tuning on link speed 1000M of QUSGMII mode. */ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + phy_modify_mmd(phydev, MDIO_MMD_AN, QCA8084_MMD7_IPG_OP, + QCA8084_IPG_10_TO_11_EN, + phydev->speed == SPEED_1000 ? + QCA8084_IPG_10_TO_11_EN : 0); +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2312,6 +2352,7 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .config_init = qca8084_config_init, + .link_change_notify = qca8084_link_change_notify, }, }; module_phy_driver(at803x_driver);