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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id cb8-20020a170906a44800b009fd4583851esm3569253ejb.178.2023.11.25.06.27.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:27:14 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 15:27:03 +0100 Subject: [PATCH v6 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v6-1-682e4855b7e2@linaro.org> References: <20230328-topic-msgram_mpm-v6-0-682e4855b7e2@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v6-0-682e4855b7e2@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700922431; l=3285; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=UnAJ2EWA9JR18tWPDeobMem6WcpQTcTZkHcMBc8DA5o=; b=2NrJMi4Wx+FGVOzYyLITnbX5suwHJ1qk4x1+EdNB/0gWA9Tu7x8Maq1745tzQFYNIqkSBMs8m vcFVDVq+keCDu6x+TGKskBrfJ3kSUJoxOxM+B7HB/BZ3m3sBIZRhsJC X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Sat, 25 Nov 2023 06:27:26 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783546458014434540 X-GMAIL-MSGID: 1783546458014434540 Due to the wild nature of the Qualcomm RPM Message RAM, we can't really use 'reg' to point to the MPM's slice of Message RAM without cutting into an already-defined RPM MSG RAM node used for GLINK and SMEM. Document passing the register space as a slice of SRAM through the qcom,rpm-msg-ram property. This also makes 'reg' deprecated. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../bindings/interrupt-controller/qcom,mpm.yaml | 52 +++++++++++++++------- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml index 509d20c091af..4ce7912d8047 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -29,6 +29,12 @@ properties: maxItems: 1 description: Specifies the base address and size of vMPM registers in RPM MSG RAM. + deprecated: true + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the APSS MPM slice of the RPM Message RAM interrupts: maxItems: 1 @@ -64,33 +70,45 @@ properties: required: - compatible - - reg - interrupts - mboxes - interrupt-controller - '#interrupt-cells' - qcom,mpm-pin-count - qcom,mpm-pin-map + - qcom,rpm-msg-ram additionalProperties: false examples: - | #include - mpm: interrupt-controller@45f01b8 { - compatible = "qcom,mpm"; - interrupts = ; - reg = <0x45f01b8 0x1000>; - mboxes = <&apcs_glb 1>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - qcom,mpm-pin-count = <96>; - qcom,mpm-pin-map = <2 275>, - <5 296>, - <12 422>, - <24 79>, - <86 183>, - <90 260>, - <91 260>; + + remoteproc-rpm { + compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + }; + + mpm: interrupt-controller { + compatible = "qcom,mpm"; + qcom,rpm-msg-ram = <&apss_mpm>; + interrupts = ; + mboxes = <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + qcom,mpm-pin-count = <96>; + qcom,mpm-pin-map = <2 275>, + <5 296>, + <12 422>, + <24 79>, + <86 183>, + <91 260>; + }; }; From patchwork Sat Nov 25 14:27:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 169746 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp1968273vqx; Sat, 25 Nov 2023 06:28:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IFQDuZbS3GgTJ07LQYFYUTJVYzEW6r7Yu1MWhrji1yJ/gmJmWrT8OQIfBqgaoMbLP6hJi6r X-Received: by 2002:a17:90b:17cd:b0:285:a0ae:6a4c with SMTP id me13-20020a17090b17cd00b00285a0ae6a4cmr2497882pjb.29.1700922539380; Sat, 25 Nov 2023 06:28:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700922539; cv=none; d=google.com; s=arc-20160816; b=AGfjXzwGl3roZ4XaNDtMAefA76MPn8YsRQzqZTErp1MdN5hXXGp6VbEKJO/L4FhaHN y3MRtsQvE8iGJr12AfY0+kGAvoJzsEkh7V1uBI5CIApc2Hb8fYx5IykidvOAtxwEgWQM 2OXAfFDw+er8n5bFU00E/lhVv+5Zy7YQAlQTSB/QpopOIkJCc4f5XuLWWBHaFqGQOJbU vrfRLj1fs/3qfVQsgYgyVz9+spRInBxAj+DBcaRiIobiiOEViGH3CkzEQIGpBtNLqAx3 /1IcaRjG5+9yiO0v0n6QZPhzhXVjXhH3uUYSzSa6m+SfH4q5eFrvWXlaxUVoTF6kVLOG +HzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=IjrMx0Y9XqGbeFGv2v7KF3vpFk6Af7SmrHYjsceKUcc=; fh=U1JT+TKNacymScwygDAagMa2UR8OqmqOmCHB7vFmHHM=; b=qbCQiDoxVvsGWhFo24IsF++FDyiNsTgX0S1jnj7xl3BJcbor2UNyIJDN+/EEVuKtH2 N5L4H/MmucrTnxgLVfXCHnKdIpqWgybRIBkNSbUBrvye8KGi2SycS2i/be0qHXP7Dstl NCfrAek+1NMPS5QZ922S9+kcGXMtX3Yx6fb9JEnEBOWp0t80xF8cgHTGK9IkWnps+k8y LDZ/brhkrzc7FP/dJ+hDTeiNZlYzRbQUmHyRDZ/23k8Sf1CpUWWQDYyslm2dCFtQ990b Txcjz5SaQTvu/22WStwVOHShYCCWO/5swC2xi8qJOhvhQY3/LgMTV5EZuR+l/1PntKaq 18vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nMSIOCap; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from snail.vger.email (snail.vger.email. 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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id cb8-20020a170906a44800b009fd4583851esm3569253ejb.178.2023.11.25.06.27.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:27:16 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 15:27:04 +0100 Subject: [PATCH v6 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v6-2-682e4855b7e2@linaro.org> References: <20230328-topic-msgram_mpm-v6-0-682e4855b7e2@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v6-0-682e4855b7e2@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700922431; l=2753; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=C9jl/qWAOl6wjNdLIwtjlGydPzEtEemM1AEix/NRi+g=; b=QtoC2BFtU8WEQA3FaUGzzwenP8GqsgZoAjavep58j+7Xe7xYs8nBar2m2me6Rpy4DsIoa0wF3 Rm4t4mZXOxaC1SKmjd726QWQTfffqWQ1f0bR+GNiVeYGNpXTX11V9zK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Sat, 25 Nov 2023 06:27:30 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783546552684689147 X-GMAIL-MSGID: 1783546552684689147 The MPM hardware is accessible to us from the ARM CPUs through a shared memory region (RPM MSG RAM) that's also concurrently accessed by other kinds of cores on the system (like modem, ADSP etc.). Modeling this relation in a (somewhat) sane manner in the device tree basically requires us to either present the MPM as a child of said memory region (which makes little sense, as a mapped memory carveout is not a bus), define nodes which bleed their register spaces into one another, or passing their slice of the MSG RAM through some kind of a property. Go with the third option and add a way to map a region passed through the "qcom,rpm-msg-ram" property as our register space. The current way of using 'reg' is preserved for ABI reasons. Acked-by: Shawn Guo Signed-off-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue --- drivers/irqchip/irq-qcom-mpm.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index 7124565234a5..7115e3056aa5 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) struct device *dev = &pdev->dev; struct irq_domain *parent_domain; struct generic_pm_domain *genpd; + struct device_node *msgram_np; struct qcom_mpm_priv *priv; unsigned int pin_cnt; + struct resource res; int i, irq; int ret; @@ -374,9 +377,21 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) raw_spin_lock_init(&priv->lock); - priv->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + /* If we have a handle to an RPM message ram partition, use it. */ + msgram_np = of_parse_phandle(np, "qcom,rpm-msg-ram", 0); + if (msgram_np) { + ret = of_address_to_resource(msgram_np, 0, &res); + /* Don't use devm_ioremap_resource, as we're accessing a shared region. */ + priv->base = devm_ioremap(dev, res.start, resource_size(&res)); + of_node_put(msgram_np); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } else { + /* Otherwise, fall back to simple MMIO. */ + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } for (i = 0; i < priv->reg_stride; i++) { qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0);