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[2620:137:e000::3:3]) by mx.google.com with ESMTPS id a187-20020a624dc4000000b006c3212b57aasi4452850pfb.325.2023.11.24.17.23.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 17:23:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=osZExdbV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id C30E08250247; Fri, 24 Nov 2023 17:23:31 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231588AbjKYBXP (ORCPT + 99 others); Fri, 24 Nov 2023 20:23:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231477AbjKYBXM (ORCPT ); Fri, 24 Nov 2023 20:23:12 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3862619A8; Fri, 24 Nov 2023 17:23:15 -0800 (PST) X-UUID: 2fc6a1668b3111ee8051498923ad61e6-20231125 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=RGHzH3Rbe7Wts9R3v3pUtZHHN9HXypnbOtqmAifMrA0=; b=osZExdbVx2l34qQtg7wgSNWidjESzprDexnhI3zLCCgWWhxMorCZoiB/QWqVZfV8a7CwUo/0/JuQEs0sqqICaUS7VAGPjjEGzGc13F/cUyszalzpAOTsZmwV1z3plkQP7Bh1mV63CN55EXcIxqa7kNK9/MZqlp6/ltKiNhu01Bs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.33,REQID:452ca7dc-453e-46b8-a953-eb6d9092de69,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:364b77b,CLOUDID:2eb57460-c89d-4129-91cb-8ebfae4653fc,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: 2fc6a1668b3111ee8051498923ad61e6-20231125 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1674614134; Sat, 25 Nov 2023 09:23:06 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Sat, 25 Nov 2023 09:23:05 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Sat, 25 Nov 2023 09:23:04 +0800 From: Chunfeng Yun To: Vinod Koul , Rob Herring CC: Chunfeng Yun , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , , , , , , Macpaul Lin Subject: [PATCH 1/2] dt-bindings: phy: mediatek: tphy: add a property for force-mode switch Date: Sat, 25 Nov 2023 09:23:02 +0800 Message-ID: <20231125012303.760-1-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Fri, 24 Nov 2023 17:23:31 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783497138176737420 X-GMAIL-MSGID: 1783497138176737420 Due to some old SoCs with shared t-phy only support force-mode switch, and can't use compatible to distinguish between shared and non-shared t-phy, add a property to supported it. But now prefer to use "mediatek,syscon-type" on new SoC as far as possible. Signed-off-by: Chunfeng Yun --- Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 2bb91542e984..eedba5b7025e 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -235,6 +235,12 @@ patternProperties: Specify the flag to enable BC1.2 if support it type: boolean + mediatek,force-mode: + description: + Use force mode to switch shared phy mode, perfer to use the bellow + property "mediatek,syscon-type" if the hardware support it. + type: boolean + mediatek,syscon-type: $ref: /schemas/types.yaml#/definitions/phandle-array maxItems: 1 From patchwork Sat Nov 25 01:23:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 169619 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp1665413vqx; Fri, 24 Nov 2023 17:23:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IGarekmp2A6i5qdnOiyrWbGpfSmflBjMj584sW2M148oWyZUKkfTyed7XlBTG/coqw+k34R X-Received: by 2002:a0d:dbc8:0:b0:5ca:b35d:965 with SMTP id d191-20020a0ddbc8000000b005cab35d0965mr5033099ywe.20.1700875408083; Fri, 24 Nov 2023 17:23:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700875408; cv=none; d=google.com; s=arc-20160816; b=nA4ZiaJn53p6Ch4qL+ZnLRdePyArUyghSvMBpXJ6gLoudIKJ48XMWW+i1PzYE2MMmw FPReV3vf17pizit1Fy3qgzZA4vxuVsBvVxkUFR1O4LNGWCte/MVid5GKT6pDvsENk2tc pOGpYmE8QfQcl4KXkjEmlfpEBK55eOpwtITpdirkSRO/co8otq3PRItCzVV0b2Ai12H4 sZQPERek+ua4Ki6aqJbOaEcGwVg/Nvxt77gpANUt3jEGFIKySTXyxJv9DtTAo7IUb4zu dPiN01VXRRtib4a7BuNf8PqS13YuSX+Zd0X0kOlQ09P3v/3Jpp8Vb2cLeuiolCzHCtME 3/0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xrv0t8BsePColscuViX0CPUL+ADw51sZfmpfju2FfJQ=; fh=hkLW7ss8Z3uJ4ls+NjsGCKHoIP3JZOBuKPImyyFsb1k=; b=epDWs3gK1k5aundW/vxhehVdS6e6+x1kJE8RuaFUfn24gpYbYUHxaMzdd04rwZxf9R 3BVIWlccQztzNl5SoWI/UgDM9dyrYL2iY8S08GRQ9ghB5S9pVj9wSv1n+WT41pMonwmw De1A06rL01aHGdvgjyhq+vWw2DUOEzPbIiglhLFql8pfQLWGID07lFiQxcxmEf1sCTLU hHd58yva9EElbw8xwoTVkLFCJuqck2y8kr4OekOeqeke1Z8kcyJp3TilLFqSSxCMYZ0N gp9UMjnUJuve/YD6FWqETM3tW0L8bNzkDIx12HYBlK1Ya0mbNg+G9iK5y+zx/EXHynSM BzXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=QnCxNViZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from agentk.vger.email (agentk.vger.email. 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Signed-off-by: Chunfeng Yun --- drivers/phy/mediatek/phy-mtk-tphy.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index 05eab9014132..a4746f6cb8a1 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -185,6 +185,10 @@ #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) +#define U3P_U3_PHYD_TOP1 0x100 +#define P3D_RG_PHY_MODE GENMASK(2, 1) +#define P3D_RG_FORCE_PHY_MODE BIT(0) + #define U3P_U3_PHYD_RXDET1 0x128 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) @@ -327,6 +331,7 @@ struct mtk_phy_instance { int discth; int pre_emphasis; bool bc12_en; + bool type_force_mode; }; struct mtk_tphy { @@ -768,6 +773,23 @@ static void u3_phy_instance_init(struct mtk_tphy *tphy, void __iomem *phya = u3_banks->phya; void __iomem *phyd = u3_banks->phyd; + if (instance->type_force_mode) { + /* force phy as usb mode, default is pcie rc mode */ + mtk_phy_update_field(phyd + U3P_U3_PHYD_TOP1, P3D_RG_PHY_MODE, 1); + mtk_phy_set_bits(phyd + U3P_U3_PHYD_TOP1, P3D_RG_FORCE_PHY_MODE); + /* power down phy by ip and pipe reset */ + mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD, + P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN); + mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE, + P3C_RG_SWRST_U3_PHYD | P3C_RG_SWRST_U3_PHYD_FORCE_EN); + udelay(10); + /* power on phy again */ + mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD, + P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN); + mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE, + P3C_RG_SWRST_U3_PHYD | P3C_RG_SWRST_U3_PHYD_FORCE_EN); + } + /* gating PCIe Analog XTAL clock */ mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3, XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD); @@ -1120,6 +1142,9 @@ static void phy_parse_property(struct mtk_tphy *tphy, { struct device *dev = &instance->phy->dev; + if (instance->type == PHY_TYPE_USB3) + instance->type_force_mode = device_property_read_bool(dev, "mediatek,force-mode"); + if (instance->type != PHY_TYPE_USB2) return;