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[8.43.85.97]) by mx.google.com with ESMTPS id c3-20020a05622a024300b00421a4d68160si2860011qtx.618.2023.11.24.00.35.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 00:35:28 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E1CC43858423 for ; Fri, 24 Nov 2023 08:35:27 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id CBD583858C62 for ; Fri, 24 Nov 2023 08:34:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CBD583858C62 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CBD583858C62 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=52.59.177.22 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700814888; cv=none; b=C8FMBBS7L1IWABKjozT9S0W/PP5nvkl88e/rBLafTBiWUVyrduZfoTuBl4JxH/F54Ptbf2qr4Pmgahy0g7AiKUT7vKA554Jbn9bbXBmlXKjrJlG/OF5Zg+nYbUoyMwwbDv64W9/Y2r49K3v+QvXDM+hKev18Gfd/xNTkbGCB/nw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700814888; c=relaxed/simple; bh=8X92AcO07bs3cgT4hRp8YfGZuQ8lqFBs+bc5R/n5doA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=RXsriRt6sdi6bZodsTkh1k5Cu3B6VwdFydgVLGAy+IxUBKi3sCeKJK756wnSchzsgyDx5zrbFAdTsZeUzGkJatNSz2uy560VXOza1L23aPHlMivUpf8VgYf+RIc8Pz9tEgpXDzI6JJfdzr7RJmI60TR8tTJ5b3FM0fqmcfCkLkQ= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp75t1700814872tusi7kgx Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 24 Nov 2023 16:34:31 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: vrqOr+ppv0t6AILmCo9/nmuu2D0sPQHV5PLUjkBumXbdxim/MteY62NrzqPWy BonrnB6qZY7o/4RMS0xZhm3g5GR6hKAkuzouBvsA4XB7tkb3ixyzLAkmi/yruJ7C20CAPoa aBGGNTipG/+1RgVlboIJU3yHrgtelqaNoH0XQsPloT2OmfTg1ImUBghATHFmNITxGBHBwk8 rqwqbOlEwL+GuzgiLUhaFfcJ88fSHTR8hkUbaX9vbG1+qAKBvHqmW1WHO2odlNYWnIj+q+R SVMs7kVRTR4C9ndfgVRTtdlKnGPsBS6OFvx7HUBqlOidupsW9ydYzagfTKxFicHlQOf+Rk8 IwTPN6TQSqFCs1/ufiw8lsCYU1HufCM8n+bjNzODZ+aJmtznLSPFqHTZpCyn8u0YpuAgqi5 978lu0dgv8WQhX45Fvzz5g== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 673712639086576973 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix inconsistency among all vectorization hooks Date: Fri, 24 Nov 2023 16:34:28 +0800 Message-Id: <20231124083428.3153486-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, RCVD_IN_SBL_CSS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783433714256922342 X-GMAIL-MSGID: 1783433714256922342 This patches 200+ ICEs exposed by testing with rv64gc_zve64d. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112694 The rootcause is we disallow poly (1,1) size vectorization in preferred_simd_mode. with this following code: - if (TARGET_MIN_VLEN < 128 && TARGET_MAX_LMUL < RVV_M2) - return word_mode; However, we allow poly (1,1) size in hook: TARGET_VECTORIZE_RELATED_MODE TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES And also enables it in all vectorization patterns. I was adding this into preferred_simd_mode because poly (1,1) size mode will cause ICE in can_duplicate_and_interleave_p. So, the alternative approach we need to block poly (1,1) size in both TARGET_VECTORIZE_RELATED_MODE and TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES hooks and all vectorization patterns. which is ugly approach and too much codes change. Now, after investivation, I find it's nice that loop vectorizer can automatically block poly (1,1) size vector in interleave vectorization with this commit: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=730909fa858bd691095bc23655077aa13b7941a9 So, we don't need to worry about ICE in interleave vectorization and allow poly (1,1) size vector in vectorization which fixes 200+ ICEs in zve64d march. PR target/112694 gcc/ChangeLog: * config/riscv/riscv-v.cc (preferred_simd_mode): Allow poly_int (1,1) vectors. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112694-1.c: New test. --- gcc/config/riscv/riscv-v.cc | 19 +++------ .../gcc.target/riscv/rvv/autovec/pr112694-1.c | 41 +++++++++++++++++++ 2 files changed, 46 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 4bd1131ba87..52826d0e769 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2088,32 +2088,23 @@ expand_tuple_move (rtx *ops) machine_mode preferred_simd_mode (scalar_mode mode) { - /* We will disable auto-vectorization when TARGET_MIN_VLEN < 128 && - riscv_autovec_lmul < RVV_M2. Since GCC loop vectorizer report ICE when we - enable -march=rv64gc_zve32* and -march=rv32gc_zve64*. in the - 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since both - RVVM1SImode in -march=*zve32*_zvl32b and RVVM1DImode in - -march=*zve64*_zvl64b are NUNITS = poly (1, 1), they will cause ICE in loop - vectorizer when we enable them in this target hook. Currently, we can - support auto-vectorization in -march=rv32_zve32x_zvl128b. Wheras, - -march=rv32_zve32x_zvl32b or -march=rv32_zve32x_zvl64b are disabled. */ if (autovec_use_vlmax_p ()) { - if (TARGET_MIN_VLEN < 128 && TARGET_MAX_LMUL < RVV_M2) - return word_mode; /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and riscv_autovec_lmul as multiply factor to calculate the the NUNITS to get the auto-vectorization mode. */ poly_uint64 nunits; poly_uint64 vector_size = BYTES_PER_RISCV_VECTOR * TARGET_MAX_LMUL; poly_uint64 scalar_size = GET_MODE_SIZE (mode); - gcc_assert (multiple_p (vector_size, scalar_size, &nunits)); + /* Disable vectorization when we can't find a RVV mode for it. + E.g. -march=rv64gc_zve32x doesn't have a vector mode to vectorize + a double (DFmode) type. */ + if (!multiple_p (vector_size, scalar_size, &nunits)) + return word_mode; machine_mode rvv_mode; if (get_vector_mode (mode, nunits).exists (&rvv_mode)) return rvv_mode; } - /* TODO: We will support minimum length VLS auto-vectorization in - the future. */ return word_mode; } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c new file mode 100644 index 00000000000..8c7f7a980e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include + +#define TEST_TYPE(TYPE) \ + __attribute__((noipa)) \ + void vmul_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] * b[i]; \ + } + +#define TEST_ALL() \ + TEST_TYPE(_Float16) \ + +TEST_ALL() + +#include + +#define SZ 512 + +#define RUN(TYPE, VAL) \ + TYPE a##TYPE[SZ]; \ + TYPE b##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = 2; \ + b##TYPE[i] = VAL; \ + } \ + vmul_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (a##TYPE[i] == 2 * VAL); + +#define RUN_ALL() \ + RUN(_Float16, 4) \ + +int main () +{ + RUN_ALL() +}