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Fri, 24 Nov 2023 08:30:54 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.194.53]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 41E81492BFA; Fri, 24 Nov 2023 08:30:54 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 3AO8UpKx3449264 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Fri, 24 Nov 2023 09:30:51 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 3AO8UoVN3449263; Fri, 24 Nov 2023 09:30:50 +0100 Date: Fri, 24 Nov 2023 09:30:50 +0100 From: Jakub Jelinek To: Uros Bizjak , Hongtao Liu Cc: gcc-patches@gcc.gnu.org Subject: [PATCH] i386: Fix ICE during cbranchv16qi4 expansion [PR112681] Message-ID: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Jakub Jelinek Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783433521595838348 X-GMAIL-MSGID: 1783433521595838348 Hi! The following testcase ICEs, because cbranchv16qi4 expansion calls ix86_expand_branch with op1 being a pre-AVX unaligned memory and ix86_expand_branch emits a xorv16qi3 instruction without making sure the operand predicates are satisfied. While I could manually check if the argument (or both?) doesn't match vector_operand predicate (apparently this one or bcst_vector_operand is used in all integral 16+ bytes *xorv*3 instructions) force it into a register, but as all gen_xorv*3 expanders call ix86_expand_vector_logical_operator, it seems easier to just call that function which ensures the right thing happens. Calling the individual gen_xorv*3 functions would mean ugly switch on the modes and using high level expand_simple_binop here seems too high level to me. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2023-11-23 Jakub Jelinek PR target/112681 * config/i386/i386-expand.cc (ix86_expand_branch): Use ix86_expand_vector_logical_operator to expand vector XOR rather than gen_rtx_SET on gen_rtx_XOR. * gcc.target/i386/sse4-pr112681.c: New test. Jakub --- gcc/config/i386/i386-expand.cc.jj 2023-11-21 09:31:35.792395304 +0100 +++ gcc/config/i386/i386-expand.cc 2023-11-23 20:57:57.128721762 +0100 @@ -2453,7 +2453,8 @@ ix86_expand_branch (enum rtx_code code, /* Generate XOR since we can't check that one operand is zero vector. */ tmp = gen_reg_rtx (mode); - emit_insn (gen_rtx_SET (tmp, gen_rtx_XOR (mode, op0, op1))); + rtx ops[3] = { tmp, op0, op1 }; + ix86_expand_vector_logical_operator (XOR, mode, ops); tmp = gen_lowpart (p_mode, tmp); emit_insn (gen_rtx_SET (gen_rtx_REG (CCZmode, FLAGS_REG), gen_rtx_UNSPEC (CCZmode, --- gcc/testsuite/gcc.target/i386/sse4-pr112681.c.jj 2023-11-23 21:01:57.983361917 +0100 +++ gcc/testsuite/gcc.target/i386/sse4-pr112681.c 2023-11-23 21:01:42.054584121 +0100 @@ -0,0 +1,11 @@ +/* PR target/112681 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse4 -mno-avx" } */ + +struct S { void *c; char d[16]; } a, b; + +int +foo (void) +{ + return __builtin_memcmp (a.d, b.d, sizeof (a.d)) != 0; +}