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Thu, 23 Nov 2023 06:48:26 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AN6mPtg011831 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Nov 2023 06:48:25 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 22 Nov 2023 22:48:20 -0800 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , Imran Shaik , , , , , , Ajit Pandey , Jagadeesh Kona , "Krzysztof Kozlowski" Subject: [PATCH V5 1/4] dt-bindings: clock: qcom: Add ECPRICC clocks for QDU1000 and QRU1000 Date: Thu, 23 Nov 2023 12:17:32 +0530 Message-ID: <20231123064735.2979802-2-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231123064735.2979802-1-quic_imrashai@quicinc.com> References: <20231123064735.2979802-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: YMtDamMOeReGbLfnyQL1KqY6TUJ_ak3W X-Proofpoint-ORIG-GUID: YMtDamMOeReGbLfnyQL1KqY6TUJ_ak3W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-23_03,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 mlxscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311230046 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UPPERCASE_50_75, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 22 Nov 2023 22:48:47 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783336406253186736 X-GMAIL-MSGID: 1783336406253186736 Add device tree bindings for qcom ecpri clock controller on QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,qdu1000-ecpricc.yaml | 68 ++++++++ .../dt-bindings/clock/qcom,qdu1000-ecpricc.h | 147 ++++++++++++++++++ 2 files changed, 215 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml create mode 100644 include/dt-bindings/clock/qcom,qdu1000-ecpricc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml new file mode 100644 index 000000000000..fd21df0e7697 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000 + +maintainers: + - Taniya Das + - Imran Shaik + +description: | + Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control + module which supports the clocks, resets on QDU1000 and QRU1000 + + See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h + +properties: + compatible: + enum: + - qcom,qdu1000-ecpricc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: GPLL1 source from GCC + - description: GPLL2 source from GCC + - description: GPLL3 source from GCC + - description: GPLL4 source from GCC + - description: GPLL5 source from GCC + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + #include + clock-controller@280000 { + compatible = "qcom,qdu1000-ecpricc"; + reg = <0x00280000 0x31c00>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,qdu1000-ecpricc.h b/include/dt-bindings/clock/qcom,qdu1000-ecpricc.h new file mode 100644 index 000000000000..731e404a2ce6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qdu1000-ecpricc.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H +#define _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H + +/* ECPRI_CC clocks */ +#define ECPRI_CC_PLL0 0 +#define ECPRI_CC_PLL1 1 +#define ECPRI_CC_ECPRI_CG_CLK 2 +#define ECPRI_CC_ECPRI_CLK_SRC 3 +#define ECPRI_CC_ECPRI_DMA_CLK 4 +#define ECPRI_CC_ECPRI_DMA_CLK_SRC 5 +#define ECPRI_CC_ECPRI_DMA_NOC_CLK 6 +#define ECPRI_CC_ECPRI_FAST_CLK 7 +#define ECPRI_CC_ECPRI_FAST_CLK_SRC 8 +#define ECPRI_CC_ECPRI_FAST_DIV2_CLK 9 +#define ECPRI_CC_ECPRI_FAST_DIV2_CLK_SRC 10 +#define ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK 11 +#define ECPRI_CC_ECPRI_FR_CLK 12 +#define ECPRI_CC_ECPRI_ORAN_CLK_SRC 13 +#define ECPRI_CC_ECPRI_ORAN_DIV2_CLK 14 +#define ECPRI_CC_ETH_100G_C2C0_HM_FF_CLK_SRC 15 +#define ECPRI_CC_ETH_100G_C2C0_UDP_FIFO_CLK 16 +#define ECPRI_CC_ETH_100G_C2C1_UDP_FIFO_CLK 17 +#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_0_CLK 18 +#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_1_CLK 19 +#define ECPRI_CC_ETH_100G_C2C_HM_FF_0_DIV_CLK_SRC 20 +#define ECPRI_CC_ETH_100G_C2C_HM_FF_1_DIV_CLK_SRC 21 +#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK 22 +#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK_SRC 23 +#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_CLK 24 +#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_DIV_CLK_SRC 25 +#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_CLK 26 +#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_DIV_CLK_SRC 27 +#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_CLK_SRC 28 +#define ECPRI_CC_ETH_100G_DBG_C2C_UDP_FIFO_CLK 29 +#define ECPRI_CC_ETH_100G_FH0_HM_FF_CLK_SRC 30 +#define ECPRI_CC_ETH_100G_FH0_MACSEC_CLK_SRC 31 +#define ECPRI_CC_ETH_100G_FH1_HM_FF_CLK_SRC 32 +#define ECPRI_CC_ETH_100G_FH1_MACSEC_CLK_SRC 33 +#define ECPRI_CC_ETH_100G_FH2_HM_FF_CLK_SRC 34 +#define ECPRI_CC_ETH_100G_FH2_MACSEC_CLK_SRC 35 +#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_CLK 36 +#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_DIV_CLK_SRC 37 +#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_CLK 38 +#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_DIV_CLK_SRC 39 +#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_CLK 40 +#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_DIV_CLK_SRC 41 +#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_CLK 42 +#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_DIV_CLK_SRC 43 +#define ECPRI_CC_ETH_100G_FH_0_UDP_FIFO_CLK 44 +#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_CLK 45 +#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_DIV_CLK_SRC 46 +#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_CLK 47 +#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_DIV_CLK_SRC 48 +#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_CLK 49 +#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_DIV_CLK_SRC 50 +#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_CLK 51 +#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_DIV_CLK_SRC 52 +#define ECPRI_CC_ETH_100G_FH_1_UDP_FIFO_CLK 53 +#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_CLK 54 +#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_DIV_CLK_SRC 55 +#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_CLK 56 +#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_DIV_CLK_SRC 57 +#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_CLK 58 +#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_DIV_CLK_SRC 59 +#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_CLK 60 +#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_DIV_CLK_SRC 61 +#define ECPRI_CC_ETH_100G_FH_2_UDP_FIFO_CLK 62 +#define ECPRI_CC_ETH_100G_FH_MACSEC_0_CLK 63 +#define ECPRI_CC_ETH_100G_FH_MACSEC_1_CLK 64 +#define ECPRI_CC_ETH_100G_FH_MACSEC_2_CLK 65 +#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK 66 +#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK_SRC 67 +#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK 68 +#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK_SRC 69 +#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK 70 +#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK_SRC 71 +#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK 72 +#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK_SRC 73 +#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK 74 +#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK_SRC 75 +#define ECPRI_CC_ETH_DBG_NFAPI_AXI_CLK 76 +#define ECPRI_CC_ETH_DBG_NOC_AXI_CLK 77 +#define ECPRI_CC_ETH_PHY_0_OCK_SRAM_CLK 78 +#define ECPRI_CC_ETH_PHY_1_OCK_SRAM_CLK 79 +#define ECPRI_CC_ETH_PHY_2_OCK_SRAM_CLK 80 +#define ECPRI_CC_ETH_PHY_3_OCK_SRAM_CLK 81 +#define ECPRI_CC_ETH_PHY_4_OCK_SRAM_CLK 82 +#define ECPRI_CC_MSS_EMAC_CLK 83 +#define ECPRI_CC_MSS_EMAC_CLK_SRC 84 +#define ECPRI_CC_MSS_ORAN_CLK 85 +#define ECPRI_CC_PHY0_LANE0_RX_CLK 86 +#define ECPRI_CC_PHY0_LANE0_TX_CLK 87 +#define ECPRI_CC_PHY0_LANE1_RX_CLK 88 +#define ECPRI_CC_PHY0_LANE1_TX_CLK 89 +#define ECPRI_CC_PHY0_LANE2_RX_CLK 90 +#define ECPRI_CC_PHY0_LANE2_TX_CLK 91 +#define ECPRI_CC_PHY0_LANE3_RX_CLK 92 +#define ECPRI_CC_PHY0_LANE3_TX_CLK 93 +#define ECPRI_CC_PHY1_LANE0_RX_CLK 94 +#define ECPRI_CC_PHY1_LANE0_TX_CLK 95 +#define ECPRI_CC_PHY1_LANE1_RX_CLK 96 +#define ECPRI_CC_PHY1_LANE1_TX_CLK 97 +#define ECPRI_CC_PHY1_LANE2_RX_CLK 98 +#define ECPRI_CC_PHY1_LANE2_TX_CLK 99 +#define ECPRI_CC_PHY1_LANE3_RX_CLK 100 +#define ECPRI_CC_PHY1_LANE3_TX_CLK 101 +#define ECPRI_CC_PHY2_LANE0_RX_CLK 102 +#define ECPRI_CC_PHY2_LANE0_TX_CLK 103 +#define ECPRI_CC_PHY2_LANE1_RX_CLK 104 +#define ECPRI_CC_PHY2_LANE1_TX_CLK 105 +#define ECPRI_CC_PHY2_LANE2_RX_CLK 106 +#define ECPRI_CC_PHY2_LANE2_TX_CLK 107 +#define ECPRI_CC_PHY2_LANE3_RX_CLK 108 +#define ECPRI_CC_PHY2_LANE3_TX_CLK 109 +#define ECPRI_CC_PHY3_LANE0_RX_CLK 110 +#define ECPRI_CC_PHY3_LANE0_TX_CLK 111 +#define ECPRI_CC_PHY3_LANE1_RX_CLK 112 +#define ECPRI_CC_PHY3_LANE1_TX_CLK 113 +#define ECPRI_CC_PHY3_LANE2_RX_CLK 114 +#define ECPRI_CC_PHY3_LANE2_TX_CLK 115 +#define ECPRI_CC_PHY3_LANE3_RX_CLK 116 +#define ECPRI_CC_PHY3_LANE3_TX_CLK 117 +#define ECPRI_CC_PHY4_LANE0_RX_CLK 118 +#define ECPRI_CC_PHY4_LANE0_TX_CLK 119 +#define ECPRI_CC_PHY4_LANE1_RX_CLK 120 +#define ECPRI_CC_PHY4_LANE1_TX_CLK 121 +#define ECPRI_CC_PHY4_LANE2_RX_CLK 122 +#define ECPRI_CC_PHY4_LANE2_TX_CLK 123 +#define ECPRI_CC_PHY4_LANE3_RX_CLK 124 +#define ECPRI_CC_PHY4_LANE3_TX_CLK 125 + +/* ECPRI_CC resets */ +#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR 0 +#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR 1 +#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR 2 +#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR 3 +#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR 4 +#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR 5 +#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR 6 +#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR 7 + +#endif From patchwork Thu Nov 23 06:47:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 168731 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp259009vqx; Wed, 22 Nov 2023 22:48:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IFha2FOYRWHbi+zuvYxAremu7bsqKU6SgIUb3DDqxrgQfGl4UFdVkGKC+BP9GQ8Rrmto6lm X-Received: by 2002:a05:6a20:3d0d:b0:187:962d:746b with SMTP id y13-20020a056a203d0d00b00187962d746bmr2595731pzi.9.1700722133366; Wed, 22 Nov 2023 22:48:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700722133; 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Thu, 23 Nov 2023 06:48:31 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AN6mU1m011867 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Nov 2023 06:48:30 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 22 Nov 2023 22:48:25 -0800 From: Imran Shaik To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , Imran Shaik , , , , , , Ajit Pandey , Jagadeesh Kona Subject: [PATCH V5 2/4] clk: qcom: branch: Add mem ops support for branch2 clocks Date: Thu, 23 Nov 2023 12:17:33 +0530 Message-ID: <20231123064735.2979802-3-quic_imrashai@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231123064735.2979802-1-quic_imrashai@quicinc.com> References: <20231123064735.2979802-1-quic_imrashai@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: PLb76y0kAOXpdAIQUv2jy3diYun7Sdxa X-Proofpoint-ORIG-GUID: PLb76y0kAOXpdAIQUv2jy3diYun7Sdxa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-23_03,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 mlxscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311230046 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 22 Nov 2023 22:48:45 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783336411396292757 X-GMAIL-MSGID: 1783336411396292757 From: Taniya Das Add the support for mem ops implementation to handle the sequence of enable/disable of the memories in ethernet PHY, prior to enable/disable of the respective clocks, which helps retain the respecive block's register contents. Signed-off-by: Taniya Das Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-branch.c | 38 +++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-branch.h | 21 +++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index fc4735f74f0f..c1dba33ac31a 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -134,6 +135,43 @@ static void clk_branch2_disable(struct clk_hw *hw) clk_branch_toggle(hw, false, clk_branch2_check_halt); } +static int clk_branch2_mem_enable(struct clk_hw *hw) +{ + struct clk_mem_branch *mem_br = to_clk_mem_branch(hw); + struct clk_branch branch = mem_br->branch; + u32 val; + int ret; + + regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg, + mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask); + + ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg, + val, val & mem_br->mem_enable_ack_mask, 0, 200); + if (ret) { + WARN(1, "%s mem enable failed\n", clk_hw_get_name(&branch.clkr.hw)); + return ret; + } + + return clk_branch2_enable(hw); +} + +static void clk_branch2_mem_disable(struct clk_hw *hw) +{ + struct clk_mem_branch *mem_br = to_clk_mem_branch(hw); + + regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg, + mem_br->mem_enable_ack_mask, 0); + + return clk_branch2_disable(hw); +} + +const struct clk_ops clk_branch2_mem_ops = { + .enable = clk_branch2_mem_enable, + .disable = clk_branch2_mem_disable, + .is_enabled = clk_is_enabled_regmap, +}; +EXPORT_SYMBOL_GPL(clk_branch2_mem_ops); + const struct clk_ops clk_branch2_ops = { .enable = clk_branch2_enable, .disable = clk_branch2_disable, diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 0cf800b9d08d..8ffed603c050 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -38,6 +38,23 @@ struct clk_branch { struct clk_regmap clkr; }; +/** + * struct clk_mem_branch - gating clock which are associated with memories + * + * @mem_enable_reg: branch clock memory gating register + * @mem_ack_reg: branch clock memory ack register + * @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_ack_reg + * @branch: branch clock gating handle + * + * Clock which can gate its memories. + */ +struct clk_mem_branch { + u32 mem_enable_reg; + u32 mem_ack_reg; + u32 mem_enable_ack_mask; + struct clk_branch branch; +}; + /* Branch clock common bits for HLOS-owned clocks */ #define CBCR_CLK_OFF BIT(31) #define CBCR_NOC_FSM_STATUS GENMASK(30, 28) @@ -85,8 +102,12 @@ extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; extern const struct clk_ops clk_branch2_aon_ops; +extern const struct clk_ops clk_branch2_mem_ops; #define to_clk_branch(_hw) \ container_of(to_clk_regmap(_hw), struct clk_branch, clkr) +#define to_clk_mem_branch(_hw) \ + container_of(to_clk_branch(_hw), struct clk_mem_branch, branch) + #endif From patchwork Thu Nov 23 06:47:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imran Shaik X-Patchwork-Id: 168733 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce62:0:b0:403:3b70:6f57 with SMTP id o2csp259206vqx; Wed, 22 Nov 2023 22:49:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IHANtC4mAZDmNZd4KxhzKgIWfuWLFsW4zmXjcsJINAjE5QBxLa3W2Mqxg+uq53WIHtJInIV X-Received: by 2002:a05:6808:210:b0:3b2:e34f:349b with SMTP id l16-20020a056808021000b003b2e34f349bmr4490170oie.42.1700722168988; Wed, 22 Nov 2023 22:49:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700722168; cv=none; d=google.com; s=arc-20160816; b=tW4Ym5v0U7lCihplKPCkku2Pj4LpqEMpACWG0MWC4LomrltOJXCQgacig3DKBh5yaJ uBMj7Hs+Uue/iDYO7Hubp1JQdPDyhRgExWVsfH9/GSz1qNYnxNuoea3nkyb96cD1RjFD sHoJjsHIqxFQkXNOW3D5a/faOWGrDEwBT2GSsBtBzESfIvXt17NBJ9nIU45P1HDEHN8z U2jhH5V3AUCzWMgBM5FCK8q58H9uj96c4ARibZE3XpomQuEhWUG5W8f7xyGsrK5rqkfV ntIaPi8MnLSHYSKaadgiRjWMx0NVVqkfUQ4iNP184CTZHdaP2W6Db5e+oiG2O3g6DgFe rxIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UEDQP3Prvx8S0b0yfONQc3Kx5v24UiGVtZLEOHHme0g=; fh=36PEPqHjFV81G283Jo0Hb4dR3KtwJVkRhrkja0TVlBg=; b=AJQu0jGoafFs4h437b2g2O2U9uVMtQfN72YUeX19Iifi80hEweJRlZ/71aGomun8Bf u2W8p8eJgTToR3Qnxj9/nJXAQr/K3EBQRUYhNp47oTNnPLu57nzMXK6ZaFrnrG6a6Guj biDe6SZy3rDYR/1DvTy38x28N+NYcXLXnzy8IGtw6MQxhSp4EOOCGdCQLX1W0uYX5Tcr RhQCyMiMAGUrP3ffxMs7vfsp5GfSjMZjFR4JuBPWo4FgHkZ/APOVMWxtsaf5e8QKVFEC Gdeko6faD5wvSfXB5kzWGdZrr5W/VeN//tun3tGy5oltgxP5zeSdIdeIieyk84tZ0vqS jGEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="niyL6N/M"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from morse.vger.email (morse.vger.email. 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Wed, 22 Nov 2023 22:49:15 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783336448985760789 X-GMAIL-MSGID: 1783336448985760789 Add ECPRI Clock Controller (ECPRICC) support for QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik Acked-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/ecpricc-qdu1000.c | 2456 ++++++++++++++++++++++++++++ 3 files changed, 2466 insertions(+) create mode 100644 drivers/clk/qcom/ecpricc-qdu1000.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ad1acd9b7426..9e54afc67519 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -668,6 +668,15 @@ config QDU_GCC_1000 QRU1000 devices. Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD, PCIe, etc. +config QDU_ECPRICC_1000 + tristate "QDU1000/QRU1000 ECPRI Clock Controller" + depends on ARM64 || COMPILE_TEST + select QDU_GCC_1000 + help + Support for the ECPRI clock controller on QDU1000 and + QRU1000 devices. Say Y if you want to support the ECPRI + clock controller functionality such as Ethernet. + config SDM_GCC_845 tristate "SDM845/SDM670 Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 17edd73f9839..607ed0fabf36 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o +obj-$(CONFIG_QDU_ECPRICC_1000) += ecpricc-qdu1000.o obj-$(CONFIG_QDU_GCC_1000) += gcc-qdu1000.o obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o obj-$(CONFIG_SC_CAMCC_7280) += camcc-sc7280.o diff --git a/drivers/clk/qcom/ecpricc-qdu1000.c b/drivers/clk/qcom/ecpricc-qdu1000.c new file mode 100644 index 000000000000..c628054a7025 --- /dev/null +++ b/drivers/clk/qcom/ecpricc-qdu1000.c @@ -0,0 +1,2456 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN, + DT_GCC_ECPRI_CC_GPLL1_OUT_EVEN, + DT_GCC_ECPRI_CC_GPLL2_OUT_MAIN, + DT_GCC_ECPRI_CC_GPLL3_OUT_MAIN, + DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN, + DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN, +}; + +enum { + P_BI_TCXO, + P_ECPRI_CC_PLL0_OUT_MAIN, + P_ECPRI_CC_PLL1_OUT_MAIN, + P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, + P_GCC_ECPRI_CC_GPLL1_OUT_EVEN, + P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, + P_GCC_ECPRI_CC_GPLL3_OUT_MAIN, + P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, + P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, +}; + +static const struct pll_vco lucid_evo_vco[] = { + { 249600000, 2020000000, 0 }, +}; + +/* 700 MHz configuration */ +static const struct alpha_pll_config ecpri_cc_pll0_config = { + .l = 0x24, + .alpha = 0x7555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll ecpri_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +/* 806 MHz configuration */ +static const struct alpha_pll_config ecpri_cc_pll1_config = { + .l = 0x29, + .alpha = 0xfaaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, +}; + +static struct clk_alpha_pll ecpri_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(1), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map ecpri_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 2 }, + { P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 3 }, + { P_ECPRI_CC_PLL1_OUT_MAIN, 4 }, + { P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 }, + { P_ECPRI_CC_PLL0_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data ecpri_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN }, + { .index = DT_GCC_ECPRI_CC_GPLL2_OUT_MAIN }, + { .index = DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN }, + { .hw = &ecpri_cc_pll1.clkr.hw }, + { .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN }, + { .hw = &ecpri_cc_pll0.clkr.hw }, +}; + +static const struct parent_map ecpri_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_ECPRI_CC_GPLL1_OUT_EVEN, 2 }, + { P_GCC_ECPRI_CC_GPLL3_OUT_MAIN, 3 }, + { P_ECPRI_CC_PLL1_OUT_MAIN, 4 }, + { P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 }, + { P_ECPRI_CC_PLL0_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data ecpri_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN }, + { .index = DT_GCC_ECPRI_CC_GPLL1_OUT_EVEN }, + { .index = DT_GCC_ECPRI_CC_GPLL3_OUT_MAIN }, + { .hw = &ecpri_cc_pll1.clkr.hw }, + { .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN }, + { .hw = &ecpri_cc_pll0.clkr.hw }, +}; + +static const struct parent_map ecpri_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 }, + { P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 3 }, + { P_ECPRI_CC_PLL1_OUT_MAIN, 4 }, + { P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 }, + { P_ECPRI_CC_PLL0_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data ecpri_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN }, + { .index = DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN }, + { .hw = &ecpri_cc_pll1.clkr.hw }, + { .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN }, + { .hw = &ecpri_cc_pll0.clkr.hw }, +}; + +static const struct freq_tbl ftbl_ecpri_cc_ecpri_clk_src[] = { + F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 ecpri_cc_ecpri_clk_src = { + .cmd_rcgr = 0x9034, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_2, + .freq_tbl = ftbl_ecpri_cc_ecpri_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_clk_src", + .parent_data = ecpri_cc_parent_data_2, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ecpri_cc_ecpri_dma_clk_src[] = { + F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0), + F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 ecpri_cc_ecpri_dma_clk_src = { + .cmd_rcgr = 0x9080, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_ecpri_dma_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_dma_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ecpri_cc_ecpri_fast_clk_src[] = { + F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0), + F(600000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 ecpri_cc_ecpri_fast_clk_src = { + .cmd_rcgr = 0x904c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_ecpri_fast_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_fast_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ecpri_cc_ecpri_oran_clk_src[] = { + F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 ecpri_cc_ecpri_oran_clk_src = { + .cmd_rcgr = 0x9064, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_ecpri_oran_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_oran_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src[] = { + F(201500000, P_ECPRI_CC_PLL1_OUT_MAIN, 4, 0, 0), + F(403000000, P_ECPRI_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_c2c0_hm_ff_clk_src = { + .cmd_rcgr = 0x81b0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_c2c0_hm_ff_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src[] = { + F(100000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_c2c_hm_macsec_clk_src = { + .cmd_rcgr = 0x8150, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_c2c_hm_macsec_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src = { + .cmd_rcgr = 0x81c8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_fh0_hm_ff_clk_src = { + .cmd_rcgr = 0x8168, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh0_hm_ff_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_fh0_macsec_clk_src = { + .cmd_rcgr = 0x8108, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh0_macsec_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_fh1_hm_ff_clk_src = { + .cmd_rcgr = 0x8180, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_ecpri_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh1_hm_ff_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src[] = { + F(200000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_fh1_macsec_clk_src = { + .cmd_rcgr = 0x8120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh1_macsec_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_fh2_hm_ff_clk_src = { + .cmd_rcgr = 0x8198, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh2_hm_ff_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_fh2_macsec_clk_src = { + .cmd_rcgr = 0x8138, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_0, + .freq_tbl = ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh2_macsec_clk_src", + .parent_data = ecpri_cc_parent_data_0, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src[] = { + F(533000000, P_GCC_ECPRI_CC_GPLL1_OUT_EVEN, 1, 0, 0), + F(700000000, P_GCC_ECPRI_CC_GPLL3_OUT_MAIN, 1, 0, 0), + F(806000000, P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src = { + .cmd_rcgr = 0x8228, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_1, + .freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src", + .parent_data = ecpri_cc_parent_data_1, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src = { + .cmd_rcgr = 0x8240, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_1, + .freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src", + .parent_data = ecpri_cc_parent_data_1, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src = { + .cmd_rcgr = 0x81e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_1, + .freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src", + .parent_data = ecpri_cc_parent_data_1, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src = { + .cmd_rcgr = 0x81f8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_1, + .freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src", + .parent_data = ecpri_cc_parent_data_1, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src = { + .cmd_rcgr = 0x8210, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_1, + .freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src", + .parent_data = ecpri_cc_parent_data_1, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_ecpri_cc_mss_emac_clk_src[] = { + F(403000000, P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 ecpri_cc_mss_emac_clk_src = { + .cmd_rcgr = 0xe00c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = ecpri_cc_parent_map_2, + .freq_tbl = ftbl_ecpri_cc_mss_emac_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_mss_emac_clk_src", + .parent_data = ecpri_cc_parent_data_2, + .num_parents = ARRAY_SIZE(ecpri_cc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_ecpri_fast_div2_clk_src = { + .reg = 0x907c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_fast_div2_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_fast_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src = { + .reg = 0x8290, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src = { + .reg = 0x8294, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src = { + .reg = 0x8298, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src = { + .reg = 0x829c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src = { + .reg = 0x8260, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src = { + .reg = 0x8264, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src = { + .reg = 0x8268, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src = { + .reg = 0x826c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src = { + .reg = 0x8270, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src = { + .reg = 0x8274, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src = { + .reg = 0x8278, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src = { + .reg = 0x827c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src = { + .reg = 0x8280, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src = { + .reg = 0x8284, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src = { + .reg = 0x8288, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src = { + .reg = 0x828c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch ecpri_cc_ecpri_cg_clk = { + .halt_reg = 0x900c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x900c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_cg_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_ecpri_dma_clk = { + .halt_reg = 0x902c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x902c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_dma_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_dma_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_ecpri_dma_noc_clk = { + .halt_reg = 0xf004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_dma_noc_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_dma_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_ecpri_fast_clk = { + .halt_reg = 0x9014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_fast_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_fast_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_ecpri_fast_div2_clk = { + .halt_reg = 0x901c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x901c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_fast_div2_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_fast_div2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_ecpri_fast_div2_noc_clk = { + .halt_reg = 0xf008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_fast_div2_noc_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_fast_div2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_ecpri_fr_clk = { + .halt_reg = 0x9004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_fr_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_ecpri_oran_div2_clk = { + .halt_reg = 0x9024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_ecpri_oran_div2_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_oran_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_eth_100g_c2c0_udp_fifo_clk = { + .halt_reg = 0x80cc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80cc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_c2c0_udp_fifo_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_eth_100g_c2c1_udp_fifo_clk = { + .halt_reg = 0x80d0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80d0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_c2c1_udp_fifo_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk = { + .mem_enable_reg = 0x8410, + .mem_ack_reg = 0x8424, + .mem_enable_ack_mask = BIT(0), + .branch = { + .halt_reg = 0x80b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk = { + .mem_enable_reg = 0x8410, + .mem_ack_reg = 0x8424, + .mem_enable_ack_mask = BIT(1), + .branch = { + .halt_reg = 0x80bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk = { + .mem_enable_reg = 0x8410, + .mem_ack_reg = 0x8424, + .mem_enable_ack_mask = BIT(4), + .branch = { + .halt_reg = 0x80ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_c2c_hm_macsec_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_c2c_hm_macsec_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk = { + .mem_enable_reg = 0x8414, + .mem_ack_reg = 0x8428, + .mem_enable_ack_mask = BIT(0), + .branch = { + .halt_reg = 0x80d8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80d8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk = { + .mem_enable_reg = 0x8414, + .mem_ack_reg = 0x8428, + .mem_enable_ack_mask = BIT(1), + .branch = { + .halt_reg = 0x80e0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80e0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_branch ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk = { + .halt_reg = 0x80f0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80f0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk = { + .mem_enable_reg = 0x8404, + .mem_ack_reg = 0x8418, + .mem_enable_ack_mask = BIT(0), + .branch = { + .halt_reg = 0x800c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x800c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_0_hm_ff_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk = { + .mem_enable_reg = 0x8404, + .mem_ack_reg = 0x8418, + .mem_enable_ack_mask = BIT(1), + .branch = { + .halt_reg = 0x8014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_0_hm_ff_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk = { + .mem_enable_reg = 0x8404, + .mem_ack_reg = 0x8418, + .mem_enable_ack_mask = BIT(2), + .branch = { + .halt_reg = 0x801c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x801c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_0_hm_ff_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_3_clk = { + .mem_enable_reg = 0x8404, + .mem_ack_reg = 0x8418, + .mem_enable_ack_mask = BIT(3), + .branch = { + .halt_reg = 0x8024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_0_hm_ff_3_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_branch ecpri_cc_eth_100g_fh_0_udp_fifo_clk = { + .halt_reg = 0x8034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_0_udp_fifo_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk = { + .mem_enable_reg = 0x8408, + .mem_ack_reg = 0x841c, + .mem_enable_ack_mask = BIT(0), + .branch = { + .halt_reg = 0x8044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_1_hm_ff_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk = { + .mem_enable_reg = 0x8408, + .mem_ack_reg = 0x841c, + .mem_enable_ack_mask = BIT(1), + .branch = { + .halt_reg = 0x804c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x804c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_1_hm_ff_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk = { + .mem_enable_reg = 0x8408, + .mem_ack_reg = 0x841c, + .mem_enable_ack_mask = BIT(2), + .branch = { + .halt_reg = 0x8054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_1_hm_ff_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_3_clk = { + .mem_enable_reg = 0x8408, + .mem_ack_reg = 0x841c, + .mem_enable_ack_mask = BIT(3), + .branch = { + .halt_reg = 0x805c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x805c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_1_hm_ff_3_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_branch ecpri_cc_eth_100g_fh_1_udp_fifo_clk = { + .halt_reg = 0x806c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x806c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_1_udp_fifo_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk = { + .mem_enable_reg = 0x840c, + .mem_ack_reg = 0x8420, + .mem_enable_ack_mask = BIT(0), + .branch = { + .halt_reg = 0x807c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x807c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_2_hm_ff_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk = { + .mem_enable_reg = 0x840c, + .mem_ack_reg = 0x8420, + .mem_enable_ack_mask = BIT(1), + .branch = { + .halt_reg = 0x8084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8084, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_2_hm_ff_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk = { + .mem_enable_reg = 0x840c, + .mem_ack_reg = 0x8420, + .mem_enable_ack_mask = BIT(2), + .branch = { + .halt_reg = 0x808c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x808c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_2_hm_ff_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_3_clk = { + .mem_enable_reg = 0x840c, + .mem_ack_reg = 0x8420, + .mem_enable_ack_mask = BIT(3), + .branch = { + .halt_reg = 0x8094, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8094, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_2_hm_ff_3_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_branch ecpri_cc_eth_100g_fh_2_udp_fifo_clk = { + .halt_reg = 0x80a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_2_udp_fifo_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk = { + .mem_enable_reg = 0x8404, + .mem_ack_reg = 0x8418, + .mem_enable_ack_mask = BIT(4), + .branch = { + .halt_reg = 0x8004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_macsec_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh0_macsec_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk = { + .mem_enable_reg = 0x8408, + .mem_ack_reg = 0x841c, + .mem_enable_ack_mask = BIT(4), + .branch = { + .halt_reg = 0x803c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x803c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_macsec_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh1_macsec_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk = { + .mem_enable_reg = 0x840c, + .mem_ack_reg = 0x8420, + .mem_enable_ack_mask = BIT(4), + .branch = { + .halt_reg = 0x8074, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8074, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_fh_macsec_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_fh2_macsec_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk = { + .mem_enable_reg = 0x8410, + .mem_ack_reg = 0x8424, + .mem_enable_ack_mask = BIT(5), + .branch = { + .halt_reg = 0x80c4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80c4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_mac_c2c_hm_ref_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk = { + .mem_enable_reg = 0x8414, + .mem_ack_reg = 0x8428, + .mem_enable_ack_mask = BIT(5), + .branch = { + .halt_reg = 0x80e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk = { + .mem_enable_reg = 0x8404, + .mem_ack_reg = 0x8418, + .mem_enable_ack_mask = BIT(5), + .branch = { + .halt_reg = 0x802c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x802c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_mac_fh0_hm_ref_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk = { + .mem_enable_reg = 0x8408, + .mem_ack_reg = 0x841c, + .mem_enable_ack_mask = BIT(5), + .branch = { + .halt_reg = 0x8064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_mac_fh1_hm_ref_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh2_hm_ref_clk = { + .mem_enable_reg = 0x840c, + .mem_ack_reg = 0x8420, + .mem_enable_ack_mask = BIT(5), + .branch = { + .halt_reg = 0x809c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x809c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_100g_mac_fh2_hm_ref_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_branch ecpri_cc_eth_dbg_nfapi_axi_clk = { + .halt_reg = 0x80f4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80f4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_dbg_nfapi_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_dma_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_eth_dbg_noc_axi_clk = { + .halt_reg = 0x80fc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x80fc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_dbg_noc_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_mss_emac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk = { + .mem_enable_reg = 0x8404, + .mem_ack_reg = 0x8418, + .mem_enable_ack_mask = BIT(6), + .branch = { + .halt_reg = 0xd140, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd140, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_phy_0_ock_sram_clk", + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk = { + .mem_enable_reg = 0x8408, + .mem_ack_reg = 0x841C, + .mem_enable_ack_mask = BIT(6), + .branch = { + .halt_reg = 0xd148, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd148, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_phy_1_ock_sram_clk", + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk = { + .mem_enable_reg = 0x840c, + .mem_ack_reg = 0x8420, + .mem_enable_ack_mask = BIT(6), + .branch = { + .halt_reg = 0xd150, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd150, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_phy_2_ock_sram_clk", + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk = { + .mem_enable_reg = 0x8410, + .mem_ack_reg = 0x8424, + .mem_enable_ack_mask = BIT(6), + .branch = { + .halt_reg = 0xd158, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd158, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_phy_3_ock_sram_clk", + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_mem_branch ecpri_cc_eth_phy_4_ock_sram_clk = { + .mem_enable_reg = 0x8414, + .mem_ack_reg = 0x8428, + .mem_enable_ack_mask = BIT(6), + .branch = { + .halt_reg = 0xd160, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_eth_phy_4_ock_sram_clk", + .ops = &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_branch ecpri_cc_mss_emac_clk = { + .halt_reg = 0xe008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xe008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_mss_emac_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_mss_emac_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_mss_oran_clk = { + .halt_reg = 0xe004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xe004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_mss_oran_clk", + .parent_hws = (const struct clk_hw*[]) { + &ecpri_cc_ecpri_oran_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy0_lane0_rx_clk = { + .halt_reg = 0xd000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy0_lane0_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy0_lane0_tx_clk = { + .halt_reg = 0xd050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy0_lane0_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy0_lane1_rx_clk = { + .halt_reg = 0xd004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy0_lane1_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy0_lane1_tx_clk = { + .halt_reg = 0xd054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy0_lane1_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy0_lane2_rx_clk = { + .halt_reg = 0xd008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy0_lane2_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy0_lane2_tx_clk = { + .halt_reg = 0xd058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd058, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy0_lane2_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy0_lane3_rx_clk = { + .halt_reg = 0xd00c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd00c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy0_lane3_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy0_lane3_tx_clk = { + .halt_reg = 0xd05c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd05c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy0_lane3_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy1_lane0_rx_clk = { + .halt_reg = 0xd010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy1_lane0_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy1_lane0_tx_clk = { + .halt_reg = 0xd060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd060, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy1_lane0_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy1_lane1_rx_clk = { + .halt_reg = 0xd014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy1_lane1_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy1_lane1_tx_clk = { + .halt_reg = 0xd064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy1_lane1_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy1_lane2_rx_clk = { + .halt_reg = 0xd018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy1_lane2_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy1_lane2_tx_clk = { + .halt_reg = 0xd068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd068, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy1_lane2_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy1_lane3_rx_clk = { + .halt_reg = 0xd01c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd01c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy1_lane3_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy1_lane3_tx_clk = { + .halt_reg = 0xd06c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd06c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy1_lane3_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy2_lane0_rx_clk = { + .halt_reg = 0xd020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy2_lane0_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy2_lane0_tx_clk = { + .halt_reg = 0xd070, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd070, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy2_lane0_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy2_lane1_rx_clk = { + .halt_reg = 0xd024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy2_lane1_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy2_lane1_tx_clk = { + .halt_reg = 0xd074, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd074, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy2_lane1_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy2_lane2_rx_clk = { + .halt_reg = 0xd028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy2_lane2_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy2_lane2_tx_clk = { + .halt_reg = 0xd078, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd078, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy2_lane2_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy2_lane3_rx_clk = { + .halt_reg = 0xd02c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd02c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy2_lane3_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy2_lane3_tx_clk = { + .halt_reg = 0xd07c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd07c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy2_lane3_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy3_lane0_rx_clk = { + .halt_reg = 0xd030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy3_lane0_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy3_lane0_tx_clk = { + .halt_reg = 0xd080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd080, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy3_lane0_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy3_lane1_rx_clk = { + .halt_reg = 0xd034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy3_lane1_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy3_lane1_tx_clk = { + .halt_reg = 0xd084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd084, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy3_lane1_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy3_lane2_rx_clk = { + .halt_reg = 0xd038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd038, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy3_lane2_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy3_lane2_tx_clk = { + .halt_reg = 0xd088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd088, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy3_lane2_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy3_lane3_rx_clk = { + .halt_reg = 0xd03c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd03c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy3_lane3_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy3_lane3_tx_clk = { + .halt_reg = 0xd08c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd08c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy3_lane3_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy4_lane0_rx_clk = { + .halt_reg = 0xd040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy4_lane0_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy4_lane0_tx_clk = { + .halt_reg = 0xd090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy4_lane0_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy4_lane1_rx_clk = { + .halt_reg = 0xd044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy4_lane1_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy4_lane1_tx_clk = { + .halt_reg = 0xd094, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd094, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy4_lane1_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy4_lane2_rx_clk = { + .halt_reg = 0xd048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy4_lane2_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy4_lane2_tx_clk = { + .halt_reg = 0xd098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd098, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy4_lane2_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy4_lane3_rx_clk = { + .halt_reg = 0xd04c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd04c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy4_lane3_rx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch ecpri_cc_phy4_lane3_tx_clk = { + .halt_reg = 0xd09c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xd09c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "ecpri_cc_phy4_lane3_tx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *ecpri_cc_qdu1000_clocks[] = { + [ECPRI_CC_ECPRI_CG_CLK] = &ecpri_cc_ecpri_cg_clk.clkr, + [ECPRI_CC_ECPRI_CLK_SRC] = &ecpri_cc_ecpri_clk_src.clkr, + [ECPRI_CC_ECPRI_DMA_CLK] = &ecpri_cc_ecpri_dma_clk.clkr, + [ECPRI_CC_ECPRI_DMA_CLK_SRC] = &ecpri_cc_ecpri_dma_clk_src.clkr, + [ECPRI_CC_ECPRI_DMA_NOC_CLK] = &ecpri_cc_ecpri_dma_noc_clk.clkr, + [ECPRI_CC_ECPRI_FAST_CLK] = &ecpri_cc_ecpri_fast_clk.clkr, + [ECPRI_CC_ECPRI_FAST_CLK_SRC] = &ecpri_cc_ecpri_fast_clk_src.clkr, + [ECPRI_CC_ECPRI_FAST_DIV2_CLK] = &ecpri_cc_ecpri_fast_div2_clk.clkr, + [ECPRI_CC_ECPRI_FAST_DIV2_CLK_SRC] = &ecpri_cc_ecpri_fast_div2_clk_src.clkr, + [ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK] = &ecpri_cc_ecpri_fast_div2_noc_clk.clkr, + [ECPRI_CC_ECPRI_FR_CLK] = &ecpri_cc_ecpri_fr_clk.clkr, + [ECPRI_CC_ECPRI_ORAN_CLK_SRC] = &ecpri_cc_ecpri_oran_clk_src.clkr, + [ECPRI_CC_ECPRI_ORAN_DIV2_CLK] = &ecpri_cc_ecpri_oran_div2_clk.clkr, + [ECPRI_CC_ETH_100G_C2C0_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr, + [ECPRI_CC_ETH_100G_C2C0_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_c2c0_udp_fifo_clk.clkr, + [ECPRI_CC_ETH_100G_C2C1_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_c2c1_udp_fifo_clk.clkr, + [ECPRI_CC_ETH_100G_C2C_0_HM_FF_0_CLK] = &ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk.branch.clkr, + [ECPRI_CC_ETH_100G_C2C_0_HM_FF_1_CLK] = &ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk.branch.clkr, + [ECPRI_CC_ETH_100G_C2C_HM_FF_0_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_C2C_HM_FF_1_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK] = &ecpri_cc_eth_100g_c2c_hm_macsec_clk.branch.clkr, + [ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_c2c_hm_macsec_clk_src.clkr, + [ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_CLK] = + &ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk.branch.clkr, + [ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_CLK] = + &ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk.branch.clkr, + [ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr, + [ECPRI_CC_ETH_100G_DBG_C2C_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk.clkr, + [ECPRI_CC_ETH_100G_FH0_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH0_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_fh0_macsec_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH1_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH1_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_fh1_macsec_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH2_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH2_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_fh2_macsec_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_0_HM_FF_0_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_0_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_0_HM_FF_0_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_0_HM_FF_1_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_1_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_0_HM_FF_1_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_0_HM_FF_2_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_2_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_0_HM_FF_2_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_0_HM_FF_3_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_3_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_0_HM_FF_3_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_0_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_fh_0_udp_fifo_clk.clkr, + [ECPRI_CC_ETH_100G_FH_1_HM_FF_0_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_0_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_1_HM_FF_0_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_1_HM_FF_1_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_1_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_1_HM_FF_1_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_1_HM_FF_2_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_2_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_1_HM_FF_2_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_1_HM_FF_3_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_3_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_1_HM_FF_3_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_1_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_fh_1_udp_fifo_clk.clkr, + [ECPRI_CC_ETH_100G_FH_2_HM_FF_0_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_0_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_2_HM_FF_0_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_2_HM_FF_1_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_1_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_2_HM_FF_1_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_2_HM_FF_2_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_2_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_2_HM_FF_2_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_2_HM_FF_3_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_3_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_2_HM_FF_3_DIV_CLK_SRC] = + &ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src.clkr, + [ECPRI_CC_ETH_100G_FH_2_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_fh_2_udp_fifo_clk.clkr, + [ECPRI_CC_ETH_100G_FH_MACSEC_0_CLK] = &ecpri_cc_eth_100g_fh_macsec_0_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_MACSEC_1_CLK] = &ecpri_cc_eth_100g_fh_macsec_1_clk.branch.clkr, + [ECPRI_CC_ETH_100G_FH_MACSEC_2_CLK] = &ecpri_cc_eth_100g_fh_macsec_2_clk.branch.clkr, + [ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_c2c_hm_ref_clk.branch.clkr, + [ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src.clkr, + [ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK] = + &ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk.branch.clkr, + [ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK_SRC] = + &ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src.clkr, + [ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_fh0_hm_ref_clk.branch.clkr, + [ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src.clkr, + [ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_fh1_hm_ref_clk.branch.clkr, + [ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src.clkr, + [ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_fh2_hm_ref_clk.branch.clkr, + [ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src.clkr, + [ECPRI_CC_ETH_DBG_NFAPI_AXI_CLK] = &ecpri_cc_eth_dbg_nfapi_axi_clk.clkr, + [ECPRI_CC_ETH_DBG_NOC_AXI_CLK] = &ecpri_cc_eth_dbg_noc_axi_clk.clkr, + [ECPRI_CC_ETH_PHY_0_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_0_ock_sram_clk.branch.clkr, + [ECPRI_CC_ETH_PHY_1_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_1_ock_sram_clk.branch.clkr, + [ECPRI_CC_ETH_PHY_2_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_2_ock_sram_clk.branch.clkr, + [ECPRI_CC_ETH_PHY_3_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_3_ock_sram_clk.branch.clkr, + [ECPRI_CC_ETH_PHY_4_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_4_ock_sram_clk.branch.clkr, + [ECPRI_CC_MSS_EMAC_CLK] = &ecpri_cc_mss_emac_clk.clkr, + [ECPRI_CC_MSS_EMAC_CLK_SRC] = &ecpri_cc_mss_emac_clk_src.clkr, + [ECPRI_CC_MSS_ORAN_CLK] = &ecpri_cc_mss_oran_clk.clkr, + [ECPRI_CC_PHY0_LANE0_RX_CLK] = &ecpri_cc_phy0_lane0_rx_clk.clkr, + [ECPRI_CC_PHY0_LANE0_TX_CLK] = &ecpri_cc_phy0_lane0_tx_clk.clkr, + [ECPRI_CC_PHY0_LANE1_RX_CLK] = &ecpri_cc_phy0_lane1_rx_clk.clkr, + [ECPRI_CC_PHY0_LANE1_TX_CLK] = &ecpri_cc_phy0_lane1_tx_clk.clkr, + [ECPRI_CC_PHY0_LANE2_RX_CLK] = &ecpri_cc_phy0_lane2_rx_clk.clkr, + [ECPRI_CC_PHY0_LANE2_TX_CLK] = &ecpri_cc_phy0_lane2_tx_clk.clkr, + [ECPRI_CC_PHY0_LANE3_RX_CLK] = &ecpri_cc_phy0_lane3_rx_clk.clkr, + [ECPRI_CC_PHY0_LANE3_TX_CLK] = &ecpri_cc_phy0_lane3_tx_clk.clkr, + [ECPRI_CC_PHY1_LANE0_RX_CLK] = &ecpri_cc_phy1_lane0_rx_clk.clkr, + [ECPRI_CC_PHY1_LANE0_TX_CLK] = &ecpri_cc_phy1_lane0_tx_clk.clkr, + [ECPRI_CC_PHY1_LANE1_RX_CLK] = &ecpri_cc_phy1_lane1_rx_clk.clkr, + [ECPRI_CC_PHY1_LANE1_TX_CLK] = &ecpri_cc_phy1_lane1_tx_clk.clkr, + [ECPRI_CC_PHY1_LANE2_RX_CLK] = &ecpri_cc_phy1_lane2_rx_clk.clkr, + [ECPRI_CC_PHY1_LANE2_TX_CLK] = &ecpri_cc_phy1_lane2_tx_clk.clkr, + [ECPRI_CC_PHY1_LANE3_RX_CLK] = &ecpri_cc_phy1_lane3_rx_clk.clkr, + [ECPRI_CC_PHY1_LANE3_TX_CLK] = &ecpri_cc_phy1_lane3_tx_clk.clkr, + [ECPRI_CC_PHY2_LANE0_RX_CLK] = &ecpri_cc_phy2_lane0_rx_clk.clkr, + [ECPRI_CC_PHY2_LANE0_TX_CLK] = &ecpri_cc_phy2_lane0_tx_clk.clkr, + [ECPRI_CC_PHY2_LANE1_RX_CLK] = &ecpri_cc_phy2_lane1_rx_clk.clkr, + [ECPRI_CC_PHY2_LANE1_TX_CLK] = &ecpri_cc_phy2_lane1_tx_clk.clkr, + [ECPRI_CC_PHY2_LANE2_RX_CLK] = &ecpri_cc_phy2_lane2_rx_clk.clkr, + [ECPRI_CC_PHY2_LANE2_TX_CLK] = &ecpri_cc_phy2_lane2_tx_clk.clkr, + [ECPRI_CC_PHY2_LANE3_RX_CLK] = &ecpri_cc_phy2_lane3_rx_clk.clkr, + [ECPRI_CC_PHY2_LANE3_TX_CLK] = &ecpri_cc_phy2_lane3_tx_clk.clkr, + [ECPRI_CC_PHY3_LANE0_RX_CLK] = &ecpri_cc_phy3_lane0_rx_clk.clkr, + [ECPRI_CC_PHY3_LANE0_TX_CLK] = &ecpri_cc_phy3_lane0_tx_clk.clkr, + [ECPRI_CC_PHY3_LANE1_RX_CLK] = &ecpri_cc_phy3_lane1_rx_clk.clkr, + [ECPRI_CC_PHY3_LANE1_TX_CLK] = &ecpri_cc_phy3_lane1_tx_clk.clkr, + [ECPRI_CC_PHY3_LANE2_RX_CLK] = &ecpri_cc_phy3_lane2_rx_clk.clkr, + [ECPRI_CC_PHY3_LANE2_TX_CLK] = &ecpri_cc_phy3_lane2_tx_clk.clkr, + [ECPRI_CC_PHY3_LANE3_RX_CLK] = &ecpri_cc_phy3_lane3_rx_clk.clkr, + [ECPRI_CC_PHY3_LANE3_TX_CLK] = &ecpri_cc_phy3_lane3_tx_clk.clkr, + [ECPRI_CC_PHY4_LANE0_RX_CLK] = &ecpri_cc_phy4_lane0_rx_clk.clkr, + [ECPRI_CC_PHY4_LANE0_TX_CLK] = &ecpri_cc_phy4_lane0_tx_clk.clkr, + [ECPRI_CC_PHY4_LANE1_RX_CLK] = &ecpri_cc_phy4_lane1_rx_clk.clkr, + [ECPRI_CC_PHY4_LANE1_TX_CLK] = &ecpri_cc_phy4_lane1_tx_clk.clkr, + [ECPRI_CC_PHY4_LANE2_RX_CLK] = &ecpri_cc_phy4_lane2_rx_clk.clkr, + [ECPRI_CC_PHY4_LANE2_TX_CLK] = &ecpri_cc_phy4_lane2_tx_clk.clkr, + [ECPRI_CC_PHY4_LANE3_RX_CLK] = &ecpri_cc_phy4_lane3_rx_clk.clkr, + [ECPRI_CC_PHY4_LANE3_TX_CLK] = &ecpri_cc_phy4_lane3_tx_clk.clkr, + [ECPRI_CC_PLL0] = &ecpri_cc_pll0.clkr, + [ECPRI_CC_PLL1] = &ecpri_cc_pll1.clkr, +}; + +static const struct qcom_reset_map ecpri_cc_qdu1000_resets[] = { + [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR] = { 0x9000 }, + [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR] = { 0x80a8 }, + [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR] = { 0x8000 }, + [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR] = { 0x8038 }, + [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR] = { 0x8070 }, + [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR] = { 0x8104 }, + [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR] = { 0xe000 }, + [ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR] = { 0xf000 }, +}; + +static const struct regmap_config ecpri_cc_qdu1000_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x31bf0, + .fast_io = true, +}; + +static const struct qcom_cc_desc ecpri_cc_qdu1000_desc = { + .config = &ecpri_cc_qdu1000_regmap_config, + .clks = ecpri_cc_qdu1000_clocks, + .num_clks = ARRAY_SIZE(ecpri_cc_qdu1000_clocks), + .resets = ecpri_cc_qdu1000_resets, + .num_resets = ARRAY_SIZE(ecpri_cc_qdu1000_resets), +}; + +static const struct of_device_id ecpri_cc_qdu1000_match_table[] = { + { .compatible = "qcom,qdu1000-ecpricc" }, + { } +}; +MODULE_DEVICE_TABLE(of, ecpri_cc_qdu1000_match_table); + +static int ecpri_cc_qdu1000_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &ecpri_cc_qdu1000_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_evo_pll_configure(&ecpri_cc_pll0, regmap, &ecpri_cc_pll0_config); + clk_lucid_evo_pll_configure(&ecpri_cc_pll1, regmap, &ecpri_cc_pll1_config); + + return qcom_cc_really_probe(pdev, &ecpri_cc_qdu1000_desc, regmap); +} + +static struct platform_driver ecpri_cc_qdu1000_driver = { + .probe = ecpri_cc_qdu1000_probe, + .driver = { + .name = "ecpri_cc-qdu1000", + .of_match_table = ecpri_cc_qdu1000_match_table, + }, +}; + +module_platform_driver(ecpri_cc_qdu1000_driver); + +MODULE_DESCRIPTION("QTI ECPRICC QDU1000 Driver"); +MODULE_LICENSE("GPL"); From patchwork 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Wed, 22 Nov 2023 22:49:05 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783336425121921159 X-GMAIL-MSGID: 1783336425121921159 Add device node for ECPRI clock controller on qcom QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 1c0e5d271e91..1552b5c119bb 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -381,6 +381,20 @@ gcc: clock-controller@80000 { #power-domain-cells = <1>; }; + ecpricc: clock-controller@280000 { + compatible = "qcom,qdu1000-ecpricc"; + reg = <0x0 0x00280000 0x0 0x31c00>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + gpi_dma0: dma-controller@900000 { compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0x0 0x900000 0x0 0x60000>;