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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id s4-20020a05622a1a8400b004236f267ac1si568320qtc.69.2023.11.22.22.10.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 22:10:18 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=gApf3NF8; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3E7503858C36 for ; Thu, 23 Nov 2023 06:10:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 41D243858D37 for ; Thu, 23 Nov 2023 06:09:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 41D243858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 41D243858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.100 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700719795; cv=none; b=fAzu2K5OzQ69ZmIsyMYIpwuVIqcL2OKAudQsc6PxNqd4hDleyU8fsRiF4OMvYUz7g7Pit998rMaq7qSqY9DPvAifntBV6CdGbblcpyC7395NIy5WX2pR3+6mxiAGu3MR5UFPFAmd/KZlTbOIcDXXAYj+6jGtgMOZwc6Lq6yqROI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700719795; c=relaxed/simple; bh=lcevEquvryfCYxLw8oF5QN9e4M309KWG0mTJTlhMF1s=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=MvdFZ2GLcIaEUUXMYxPGif7hxHQxceglLyW45VTkdyBUwR0gOHcokMrA2cheaIu/nx2pNSGAfFopszm6lGXHMfyxJeYcKEpaUEfjLnFogxJYCc9h/PKca8seVYyyFA52MoR3bqTmfGNGdg+XhzP/vER4KH3RLyK4mSwktO813jc= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700719793; x=1732255793; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=lcevEquvryfCYxLw8oF5QN9e4M309KWG0mTJTlhMF1s=; b=gApf3NF8K3hMMxYJ4e5RfSNpWHD+dRiqgs0joKn3ucWba6uUFeT7qwi3 BMVKKlfk/xoRFiTcBm5qNWNXdWdeJZdN+wTFQ+CAfUfRpobR8rMo3oOnR Vsep4znM1eC4aJq31ecL19Ua0v8INqGMdajGGuFFr4rZtmkxl29U7emt+ SUwOj/nUzRkgedbtBAAlk/aNz/jFWheS8NpWUXGdCYFWVIAR8wa30kydS FfGlIlbXXoMmsW/7KOMqWXvhzg3sEoHzhOtxf7nA7K7gTE/SO6lTrS848 v0ZEQGjNn6u5RtYiTZG7GQ2/OWs1rGi/3RX4BdI0yArB/dc5Cx+E9cYIj Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="458703060" X-IronPort-AV: E=Sophos;i="6.04,220,1695711600"; d="scan'208";a="458703060" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2023 22:09:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="884876955" X-IronPort-AV: E=Sophos;i="6.04,220,1695711600"; d="scan'208";a="884876955" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 22 Nov 2023 22:09:49 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 1D3AA1005701; Thu, 23 Nov 2023 14:09:49 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] i386: Fix AVX512 and AVX10 option issues Date: Thu, 23 Nov 2023 14:09:49 +0800 Message-Id: <20231123060949.618089-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783333984421835002 X-GMAIL-MSGID: 1783333984421835002 Hi all, This patch should be able to fix the current issue mentioned in PR112643. Also, I fixed some legacy issues in code related to AVX512/AVX10. Ok for trunk? Thx, Haochen gcc/ChangeLog: PR target/112643 * config/i386/driver-i386.cc (check_avx10_avx512_features): Renamed to ... (check_avx512_features): this and remove avx10 check. (host_detect_local_cpu): Never append -mno-avx10.1-{256,512} to avoid emitting warnings when building GCC with native arch. * config/i386/i386-builtin.def (BDESC): Add missing AVX512VL for 128/256 bit builtin for AVX512VP2INTERSECT. * config/i386/i386-options.cc (ix86_option_override_internal): Also check whether the AVX512 flags is set when trying to reset. * config/i386/i386.h (PTA_SKYLAKE_AVX512): Add missing PTA_EVEX512. (PTA_ZNVER4): Ditto. --- gcc/config/i386/driver-i386.cc | 19 +++++++++---------- gcc/config/i386/i386-builtin.def | 8 ++++---- gcc/config/i386/i386-options.cc | 8 +++++--- gcc/config/i386/i386.h | 4 ++-- 4 files changed, 20 insertions(+), 19 deletions(-) diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index ae67efc49c3..204600e128a 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -377,15 +377,10 @@ detect_caches_intel (bool xeon_mp, unsigned max_level, enabled and the other disabled. Add this function to avoid push "-mno-" options under this scenario for -march=native. */ -bool check_avx10_avx512_features (__processor_model &cpu_model, - unsigned int (&cpu_features2)[SIZE_OF_CPU_FEATURES], - const enum processor_features feature) +bool check_avx512_features (__processor_model &cpu_model, + unsigned int (&cpu_features2)[SIZE_OF_CPU_FEATURES], + const enum processor_features feature) { - if (has_feature (FEATURE_AVX512F) - && ((feature == FEATURE_AVX10_1_256) - || (feature == FEATURE_AVX10_1_512))) - return false; - if (has_feature (FEATURE_AVX10_1_256) && ((feature == FEATURE_AVX512F) || (feature == FEATURE_AVX512CD) @@ -900,8 +895,12 @@ const char *host_detect_local_cpu (int argc, const char **argv) options = concat (options, " ", isa_names_table[i].option, NULL); } - else if (check_avx10_avx512_features (cpu_model, cpu_features2, - isa_names_table[i].feature)) + /* Never push -mno-avx10.1-{256,512} under -march=native to + avoid unnecessary warnings when building librarys. */ + else if ((isa_names_table[i].feature != FEATURE_AVX10_1_256) + && (isa_names_table[i].feature != FEATURE_AVX10_1_512) + && check_avx512_features (cpu_model, cpu_features2, + isa_names_table[i].feature)) options = concat (options, neg_option, isa_names_table[i].option + 2, NULL); } diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 19fa5c107c7..7a5f2676999 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -301,10 +301,10 @@ BDESC (OPTION_MASK_ISA_AVX512BW, OPTION_MASK_ISA2_EVEX512, CODE_FOR_avx512bw_sto /* AVX512VP2INTERSECT */ BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT | OPTION_MASK_ISA2_EVEX512, CODE_FOR_nothing, "__builtin_ia32_2intersectd512", IX86_BUILTIN_2INTERSECTD512, UNKNOWN, (int) VOID_FTYPE_PUHI_PUHI_V16SI_V16SI) BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT | OPTION_MASK_ISA2_EVEX512, CODE_FOR_nothing, "__builtin_ia32_2intersectq512", IX86_BUILTIN_2INTERSECTQ512, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V8DI_V8DI) -BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectd256", IX86_BUILTIN_2INTERSECTD256, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V8SI_V8SI) -BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectq256", IX86_BUILTIN_2INTERSECTQ256, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V4DI_V4DI) -BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectd128", IX86_BUILTIN_2INTERSECTD128, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V4SI_V4SI) -BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectq128", IX86_BUILTIN_2INTERSECTQ128, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V2DI_V2DI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectd256", IX86_BUILTIN_2INTERSECTD256, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V8SI_V8SI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectq256", IX86_BUILTIN_2INTERSECTQ256, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V4DI_V4DI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectd128", IX86_BUILTIN_2INTERSECTD128, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V4SI_V4SI) +BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectq128", IX86_BUILTIN_2INTERSECTQ128, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V2DI_V2DI) /* AVX512VL */ BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_loadv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCSHORT_V16HI_UHI) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index dd5df559c84..a41bfe546b9 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -2691,10 +2691,12 @@ ix86_option_override_internal (bool main_args_p, { opts->x_ix86_isa_flags = (~avx512_isa_flags & opts->x_ix86_isa_flags) - | (avx512_isa_flags & opts->x_ix86_isa_flags_explicit); - opts->x_ix86_isa_flags2 = (~avx512_isa_flags + | (avx512_isa_flags & opts->x_ix86_isa_flags + & opts->x_ix86_isa_flags_explicit); + opts->x_ix86_isa_flags2 = (~avx512_isa_flags2 & opts->x_ix86_isa_flags2) - | (avx512_isa_flags2 & opts->x_ix86_isa_flags2_explicit); + | (avx512_isa_flags2 & opts->x_ix86_isa_flags2 + & opts->x_ix86_isa_flags2_explicit); } } } diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 9c74b3ebd90..47340c6a4ad 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2375,7 +2375,7 @@ constexpr wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SGX; constexpr wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU - | PTA_CLWB; + | PTA_CLWB | PTA_EVEX512; constexpr wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VNNI; constexpr wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16; @@ -2441,7 +2441,7 @@ constexpr wide_int_bitmask PTA_ZNVER3 = PTA_ZNVER2 | PTA_VAES | PTA_VPCLMULQDQ constexpr wide_int_bitmask PTA_ZNVER4 = PTA_ZNVER3 | PTA_AVX512F | PTA_AVX512DQ | PTA_AVX512IFMA | PTA_AVX512CD | PTA_AVX512BW | PTA_AVX512VL | PTA_AVX512BF16 | PTA_AVX512VBMI | PTA_AVX512VBMI2 | PTA_GFNI - | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ; + | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ | PTA_EVEX512; constexpr wide_int_bitmask PTA_LUJIAZUI = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES