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Wed, 22 Nov 2023 19:13:58 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AMJDvpL031615 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 19:13:57 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 22 Nov 2023 11:13:53 -0800 From: Krishna Kurapati To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , CC: , , , , , , Krishna Kurapati Subject: [PATCH 1/6] dt-bindings: usb: dwc3: Clean up hs_phy_irq in bindings Date: Thu, 23 Nov 2023 00:43:35 +0530 Message-ID: <20231122191335.3058-1-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: eV3Adt5Fftgy3sGq-qajQRMzVYkWxWxV X-Proofpoint-ORIG-GUID: eV3Adt5Fftgy3sGq-qajQRMzVYkWxWxV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_13,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 mlxscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220139 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 22 Nov 2023 11:14:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783292708894991678 X-GMAIL-MSGID: 1783292708894991678 The high speed related interrupts present on QC targets are as follows: dp/dm Irq's These IRQ's directly reflect changes on the DP/DM pads of the SoC. These are used as wakeup interrupts only on SoCs with non-QUSBb2 targets with exception of SDM670/SDM845/SM6350. qusb2_phy irq SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL register. The required DPSE/DMSE configuration is done in QUSB2PHY_INTR_CTRL register of phy address space. hs_phy_irq This is completely different from the above two and is present on all targets with exception of a few IPQ ones. The interrupt is not enabled by default and its functionality is mutually exclusive of qusb2_phy on QUSB targets and DP/DM on femto phy targets. The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq" when they should have been "qusb2_phy_irq". On Femto phy targets, the "hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event", neither of which would never be triggered directly are non-functional currently. The implementation tries to clean up this issue by addressing the discrepencies involved and fixing the hs_phy_irq's in respective DT's. Signed-off-by: Krishna Kurapati --- .../devicetree/bindings/usb/qcom,dwc3.yaml | 125 ++++++++++-------- 1 file changed, 69 insertions(+), 56 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index e889158ca205..4a46346e2ead 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -17,20 +17,25 @@ properties: - qcom,ipq5018-dwc3 - qcom,ipq5332-dwc3 - qcom,ipq6018-dwc3 + - qcom,ipq6018-dwc3-sec - qcom,ipq8064-dwc3 - qcom,ipq8074-dwc3 - qcom,ipq9574-dwc3 - qcom,msm8953-dwc3 - qcom,msm8994-dwc3 - qcom,msm8996-dwc3 + - qcom,msm8996-dwc3-sec - qcom,msm8998-dwc3 - qcom,qcm2290-dwc3 - qcom,qcs404-dwc3 - qcom,sa8775p-dwc3 + - qcom,sa8775p-dwc3-ter - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 + - qcom,sc7280-dwc3-sec - qcom,sc8280xp-dwc3 - qcom,sdm660-dwc3 + - qcom,sdm660-dwc3-sec - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 @@ -98,11 +103,11 @@ properties: interrupts: minItems: 1 - maxItems: 4 + maxItems: 5 interrupt-names: minItems: 1 - maxItems: 4 + maxItems: 5 qcom,select-utmi-as-pipe-clk: description: @@ -175,10 +180,13 @@ allOf: - qcom,ipq9574-dwc3 - qcom,msm8953-dwc3 - qcom,msm8996-dwc3 + - qcom,msm8996-dwc3-sec - qcom,msm8998-dwc3 - qcom,sa8775p-dwc3 + - qcom,sa8775p-dwc3-ter - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 + - qcom,sc7280-dwc3-sec - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 @@ -203,6 +211,7 @@ allOf: contains: enum: - qcom,ipq6018-dwc3 + - qcom,ipq6018-dwc3-sec then: properties: clocks: @@ -285,6 +294,7 @@ allOf: contains: enum: - qcom,sdm660-dwc3 + - qcom,sdm660-dwc3-sec then: properties: clocks: @@ -357,20 +367,15 @@ allOf: compatible: contains: enum: - - qcom,ipq4019-dwc3 - - qcom,ipq6018-dwc3 - - qcom,ipq8064-dwc3 - - qcom,ipq8074-dwc3 - - qcom,msm8994-dwc3 - - qcom,qcs404-dwc3 + - qcom,sc8280xp-dwc3 + - qcom,sa8775p-dwc3 - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 - - qcom,sm4250-dwc3 - - qcom,sm6125-dwc3 - qcom,sm6350-dwc3 - qcom,sm8150-dwc3 - qcom,sm8250-dwc3 @@ -381,16 +386,37 @@ allOf: properties: interrupts: items: + - description: Wakeup event on DM line. + - description: Wakeup event on DP line. - description: The interrupt that is asserted - when a wakeup event is received on USB2 bus. + based on linestates. Is enabled if qscratch + registers are configured appropirately. This + interrupt functionality is mutually exclusive + to that of {dp/d}_hs_phy_irq) + - description: Wakeup based on power events. - description: The interrupt that is asserted when a wakeup event is received on USB3 bus. - - description: Wakeup event on DM line. - - description: Wakeup event on DP line. interrupt-names: items: + - const: dm_hs_phy_irq + - const: dp_hs_phy_irq - const: hs_phy_irq + - const: pwr_event - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-dwc3-sec + - qcom,sa8775p-ter + then: + properties: + interrupt-names: + items: + - const: pwr_event + - const: hs_phy_irq - const: dm_hs_phy_irq - const: dp_hs_phy_irq @@ -399,36 +425,29 @@ allOf: compatible: contains: enum: - - qcom,msm8953-dwc3 - - qcom,msm8996-dwc3 - - qcom,msm8998-dwc3 - - qcom,sm6115-dwc3 + - qcom,ipq6018-dwc3-sec then: properties: - interrupts: - maxItems: 2 interrupt-names: items: - - const: hs_phy_irq - - const: ss_phy_irq + - const: pwr_event + - const: qusb2_phy - if: properties: compatible: contains: enum: - - qcom,ipq5018-dwc3 - - qcom,ipq5332-dwc3 - - qcom,sdm660-dwc3 + - qcom,ipq6018-dwc3 + - qcom,ipq8074-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8998-dwc3 then: properties: - interrupts: - minItems: 1 - maxItems: 2 interrupt-names: - minItems: 1 items: - - const: hs_phy_irq + - const: pwr_event + - const: qusb2_phy - const: ss_phy_irq - if: @@ -436,55 +455,48 @@ allOf: compatible: contains: enum: - - qcom,sc7280-dwc3 + - qcom,msm8996-dwc3 + - qcom,sdm660-dwc3 + - qcom,sm4250-dwc3 + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 then: properties: - interrupts: - minItems: 3 - maxItems: 4 interrupt-names: - minItems: 3 items: - const: hs_phy_irq - - const: dp_hs_phy_irq - - const: dm_hs_phy_irq + - const: pwr_event + - const: qusb2_phy - const: ss_phy_irq - - if: properties: compatible: contains: enum: - - qcom,sc8280xp-dwc3 + - qcom,sdm660-dwc3-sec + - qcom,msm8996-dwc3-sec + - qcom,qcs404-dwc3 then: properties: - interrupts: - maxItems: 4 interrupt-names: items: + - const: hs_phy_irq - const: pwr_event - - const: dp_hs_phy_irq - - const: dm_hs_phy_irq - - const: ss_phy_irq + - const: qusb2_phy - if: properties: compatible: contains: enum: - - qcom,sa8775p-dwc3 + - qcom,ipq5332-dwc3 then: properties: - interrupts: - minItems: 3 - maxItems: 4 interrupt-names: - minItems: 3 items: - - const: pwr_event - const: dp_hs_phy_irq - const: dm_hs_phy_irq - - const: ss_phy_irq + - const: pwr_event additionalProperties: false @@ -519,12 +531,13 @@ examples: <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + interrupts = , + , + , + , + ; + interrupt-names = "dm_hs_phy_irq", "dp_hs_phy_irq", + "hs_phy_irq", "pwr_event", "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; From patchwork Wed Nov 22 19:14:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 168524 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1553559vqb; Wed, 22 Nov 2023 11:14:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IHdR7GhoB5rM8tmwv51kfROMx17kZOPBF6oMyzr7hyM39heqm9H876ilBuk1fVNMybRYJq4 X-Received: by 2002:a92:290c:0:b0:357:a1cd:a16 with SMTP id l12-20020a92290c000000b00357a1cd0a16mr3591525ilg.6.1700680475105; Wed, 22 Nov 2023 11:14:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700680475; cv=none; d=google.com; s=arc-20160816; b=P3Ut8W2GnJY2quVc1Sn+Yrb6lqCS7iLMIJp7JxVJyiGma6U9IzwG5ixQfF3Po+ZFL4 tF2JVqnOBPVMFCXR5Rtzni8/RyjbPGKbF11fH842HvDLpW/fHaR/EqxNOy+O4l8pum8w gu2hS9HbGIZ6GepZCdvyfe0k3bslzBUy6S+BuFzg8asdEnkvcOrAtDoEzYH2OjVEcD4z d/4bWBS8jNBWKmxi6Y+RTTq+DS7h8rBB3eJRzP9EUd0odVUGSlOPRhOljDRrp8FEQTct cjLDXqGLOEOdw6iEtTERyrZmFZNgTnJ/Vx78p+7epy13iCBRGecnPN/TOt4OQMCj5ybw sU1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=/tZNbBJRcR14VoBJO8pRBORmDeuMBzs1JSkfpqU+k/U=; fh=EtXJBMIHeO+qqwqGVNUePQVI5zLYvhCe51LCcxlruSs=; b=QV6+7I73f/DySQ6rob58rkrUtsLWTTpchpFZRD2633PgIiPqO5BDrKpv69sM3Co63V vNCclnvJ8/xOfHAAXzdepeSN2S2skqG2Tpc9teczyCNlK77NDOaLjXPaGe8MmW+/fm60 FPlArXjo9i+WmAfF/OsmJCWgv11Zi2jS0yyzO1DGcRZEdH29GX3U3BXwwIfIxg3a4Mh9 RRVRH8vUtZO4dZmcfUmsr6+X8dJJmOqcnHo6X3DQEF1mVqmcok+ARjylp9h4D0wv89dd /gHGjnUJClibTxBktJqfpAZJ6SgALOjwj4PgfNovt0phKVKQH5B952vmkBwCV6tYP4Zy tztQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=AkrhsjM3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from agentk.vger.email (agentk.vger.email. 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Wed, 22 Nov 2023 11:14:31 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783292729534962576 X-GMAIL-MSGID: 1783292729534962576 For wakeup to work, driver needs to enable interrupts that depict what is happening on th DP/DM lines. On QUSB targets, this is identified by qusb2_phy whereas on SoCs using Femto PHY, separate {dp,dm}_hs_phy_irq's are used instead. The implementation incorrectly names qusb2_phy interrupts as "hs_phy_irq". Clean this up so that driver would be using only qusb2/(dp & dm) for wakeup purposes. Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/dwc3-qcom.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 3de43df6bbe8..11be8faf5f58 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -57,7 +57,7 @@ struct dwc3_acpi_pdata { u32 qscratch_base_offset; u32 qscratch_base_size; u32 dwc3_core_base_size; - int hs_phy_irq_index; + int qusb2_phy_irq_index; int dp_hs_phy_irq_index; int dm_hs_phy_irq_index; int ss_phy_irq_index; @@ -73,7 +73,7 @@ struct dwc3_qcom { int num_clocks; struct reset_control *resets; - int hs_phy_irq; + int qusb2_phy_irq; int dp_hs_phy_irq; int dm_hs_phy_irq; int ss_phy_irq; @@ -372,7 +372,7 @@ static void dwc3_qcom_disable_wakeup_irq(int irq) static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) { - dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq); + dwc3_qcom_disable_wakeup_irq(qcom->qusb2_phy_irq); if (qcom->usb2_speed == USB_SPEED_LOW) { dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); @@ -389,7 +389,7 @@ static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) { - dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0); + dwc3_qcom_enable_wakeup_irq(qcom->qusb2_phy_irq, 0); /* * Configure DP/DM line interrupts based on the USB2 device attached to @@ -542,20 +542,20 @@ static int dwc3_qcom_setup_irq(struct platform_device *pdev) int irq; int ret; - irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq", - pdata ? pdata->hs_phy_irq_index : -1); + irq = dwc3_qcom_get_irq(pdev, "qusb2_phy", + pdata ? pdata->qusb2_phy_irq_index : -1); if (irq > 0) { /* Keep wakeup interrupts disabled until suspend */ irq_set_status_flags(irq, IRQ_NOAUTOEN); ret = devm_request_threaded_irq(qcom->dev, irq, NULL, qcom_dwc3_resume_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - "qcom_dwc3 HS", qcom); + "qcom_dwc3 QUSB2_HS", qcom); if (ret) { - dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret); + dev_err(qcom->dev, "qusb2_phy failed: %d\n", ret); return ret; } - qcom->hs_phy_irq = irq; + qcom->qusb2_phy_irq = irq; } irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq", @@ -1033,7 +1033,7 @@ static const struct dwc3_acpi_pdata sdm845_acpi_pdata = { .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, .qscratch_base_size = SDM845_QSCRATCH_SIZE, .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, - .hs_phy_irq_index = 1, + .qusb2_phy_irq_index = 1, .dp_hs_phy_irq_index = 4, .dm_hs_phy_irq_index = 3, .ss_phy_irq_index = 2 @@ -1043,7 +1043,7 @@ static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = { .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, .qscratch_base_size = SDM845_QSCRATCH_SIZE, .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, - .hs_phy_irq_index = 1, + .qusb2_phy_irq_index = 1, .dp_hs_phy_irq_index = 4, .dm_hs_phy_irq_index = 3, .ss_phy_irq_index = 2, From patchwork Wed Nov 22 19:14:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 168525 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1553745vqb; Wed, 22 Nov 2023 11:14:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IHkaPvpBsSod2HBkwwEom5XRaunBB64HnWr3AiEQT8sxMxOU3A1vi3WiEFryqeCgkOcWr4A X-Received: by 2002:a05:6a20:3ca8:b0:177:690a:7978 with SMTP id b40-20020a056a203ca800b00177690a7978mr3446130pzj.33.1700680493563; Wed, 22 Nov 2023 11:14:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700680493; cv=none; d=google.com; s=arc-20160816; b=V1W991wyf7goPeUAl1xeHajZQio0jyOYNIynLpXrC7dMX/iEBdJYA/+5T5+BScHZET ON29qh11bkQyo0hTOMvYn2MYIEivdEBMbpfW8Wn/wUGhoT4bK0He/jk/avBPvQ6A7vh9 QLEiJLLN2ljSUNpn3COqIoLGsq4DSNU8SoZld3zMXTLhVX0QKmblNYmeCVKTy9Evkmw5 hTxMFcwBbsRisf7XDEAVtG6Qu58P23YKS22bYo8Gqocepvv+Ny2aQigXAMKzS/nTeEPq 8k3+KBuWx+CZdAa+ytED4hzMpdCqaZu10vULmHld9U2NfwFMdqMRa2OD6woT/lHqMoUw yM+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=lV5CUkjp0mJjA1MdbbLRFvxGUyuxj7niHvM/mYwrlnw=; fh=g59wItzuETADk8OZfORxAwr46gy/vgBLrfymtIBb3vA=; b=HR4ndiN12am62wxZJkOBAXrR9cTLf7yWfXGqOE0KsKgFbuyoIUQnzBadZDf8OCECmH 2hVrdCSPdL9xBUX/YzaZX6eZiRZXx0As4toZLg7ZuoUQ3weUfkdfAks/daUBTgExHITd 3EoVE3fDou5it7P2Yg1V17xq4v1MTXip4OGGZOezMOeEJHLCmEQ3sDTr6EwxgFUUInZZ utFYcz54mLSQs8jLdzB63wxS0ogdLyS+bzQXj9u5oo9ucNuCfFCUxFXdXZ7SEIvkOodK 1/O4QsfTt0T9k6qGHe9L0GHskHl8+1s+wcAdyMgdTx5gcapbWAa4CPfBtbf4W+cckL98 U3uQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=CORhtxzX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. 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Wed, 22 Nov 2023 11:14:48 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783292748961090114 X-GMAIL-MSGID: 1783292748961090114 On several QUSB2 Targets, the hs_phy_irq mentioned is actually qusb2_phy interrupt specific to QUSB2 Phy's. Rename hs_phy_irq to qusb_phy for such targets. In actuality, the hs_phy_irq is also present in these targets, but kept in for debug purposes in hw test environments. This is not triggered by default and its functionality is mutually exclusive to that of qusb2_phy interrupt. Add missing hs_phy_irq's, pwr_event irq's for qusb2 phy targets. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 ++++++++++++++- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +++++-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 19 ++++++++++++++----- arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +++++-- arch/arm64/boot/dts/qcom/sdm630.dtsi | 19 ++++++++++++++----- arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++-- arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 +++++++++ 8 files changed, 82 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9aec89d5e095..4edad51e0481 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -395,7 +395,7 @@ tcsr: syscon@1937000 { }; usb2: usb@70f8800 { - compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + compatible = "qcom,ipq6018-dwc3-sec", "qcom,dwc3"; reg = <0x0 0x070f8800 0x0 0x400>; #address-cells = <2>; #size-cells = <2>; @@ -411,6 +411,12 @@ usb2: usb@70f8800 { <&gcc GCC_USB1_MOCK_UTMI_CLK>; assigned-clock-rates = <133330000>, <24000000>; + + interrupts-extended = , + ; + interrupt-names = "pwr_event", + "qusb2_phy"; + resets = <&gcc GCC_USB1_BCR>; status = "disabled"; @@ -559,6 +565,13 @@ usb3: usb@8af8800 { <133330000>, <20000000>; + interrupts-extended = , + , + ; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + resets = <&gcc GCC_USB0_BCR>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5d05819f356d..2977ef424986 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -619,6 +619,13 @@ usb_0: usb@8af8800 { <133330000>, <19200000>; + interrupts-extended = , + , + ; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + power-domains = <&gcc USB0_GDSC>; resets = <&gcc GCC_USB0_BCR>; @@ -661,6 +668,13 @@ usb_1: usb@8cf8800 { <133330000>, <19200000>; + interrupts-extended = , + , + ; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + power-domains = <&gcc USB1_GDSC>; resets = <&gcc GCC_USB1_BCR>; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index e7de7632669a..29a6f9ad3df3 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1118,9 +1118,12 @@ usb3: usb@70f8800 { #size-cells = <1>; ranges; - interrupts = , + interrupts = , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, <&gcc GCC_USB30_MASTER_CLK>, diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 6ba9da9e6a8b..a5400d7dfb9c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3026,9 +3026,14 @@ usb3: usb@6af8800 { #size-cells = <1>; ranges; - interrupts = , + interrupts = , + , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy", + "ss_phy_irq"; clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, <&gcc GCC_USB30_MASTER_CLK>, @@ -3382,14 +3387,18 @@ blsp2_spi6: spi@75ba000 { }; usb2: usb@76f8800 { - compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + compatible = "qcom,msm8996-dwc3-sec", "qcom,dwc3"; reg = <0x076f8800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges; - interrupts = ; - interrupt-names = "hs_phy_irq"; + interrupts = , + , + ; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy"; clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, <&gcc GCC_USB20_MASTER_CLK>, diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index b485bf925ce6..9b7d22c4f197 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2135,9 +2135,12 @@ usb3: usb@a8f8800 { <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <120000000>; - interrupts = , + interrupts = , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "pwr_event", + "qusb2_phy", + "ss_phy_irq"; power-domains = <&gcc USB_30_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 775700f78e0f..5be337c07393 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1303,9 +1303,14 @@ usb3: usb@a8f8800 { assigned-clock-rates = <19200000>, <120000000>, <19200000>; - interrupts = , + interrupts = , + , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy", + "ss_phy_irq"; power-domains = <&gcc USB_30_GDSC>; qcom,select-utmi-as-pipe-clk; @@ -1467,7 +1472,7 @@ opp-384000000 { }; usb2: usb@c2f8800 { - compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; + compatible = "qcom,sdm660-dwc3-sec", "qcom,dwc3"; reg = <0x0c2f8800 0x400>; status = "disabled"; #address-cells = <1>; @@ -1485,8 +1490,12 @@ usb2: usb@c2f8800 { <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <60000000>; - interrupts = ; - interrupt-names = "hs_phy_irq"; + interrupts = , + , + ; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy"; qcom,select-utmi-as-pipe-clk; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 839c60351240..748dfb4dc6c7 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1301,9 +1301,14 @@ usb: usb@4ef8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <66666667>; - interrupts = , + interrupts = , + , + , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy", + "ss_phy_irq"; resets = <&gcc GCC_USB30_PRIM_BCR>; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index eb07eca3a48d..d5b6ee4e104c 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1185,6 +1185,15 @@ usb3: usb@4ef8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <66666667>; + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy", + "ss_phy_irq"; + power-domains = <&gcc USB30_PRIM_GDSC>; qcom,select-utmi-as-pipe-clk; status = "disabled"; From patchwork Wed Nov 22 19:14:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 168526 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1554498vqb; Wed, 22 Nov 2023 11:16:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IHYv3fx/4kDD6TN1fCjjKssyir3ezqsyBF/D7AEeivJtDEWU4uDvrl2HVYy7XptaZvZXVeq X-Received: by 2002:a05:6a20:8423:b0:187:f083:2cb2 with SMTP id c35-20020a056a20842300b00187f0832cb2mr4300250pzd.31.1700680567639; Wed, 22 Nov 2023 11:16:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700680567; cv=none; d=google.com; s=arc-20160816; b=F5ser/EwqsPPYEiLpzrvziswBRpE8psQuYTysJAMkIhsPrDzazMlvTPs8leB/Twv2s rO3383umWLaV5fNzrkMk3A0wLpZMrHpsUJWX28U+5Mc5dOI64Cfzgjm/kSB8/ICg3Ora wwYgKYzhuU2bx5VFcAeHTvF0LTNqvGShmiTO+CIk4NUpLC4sCrtMzOLc+WInWntoGj2s PM4q0zICES3bKFJ8UpZ3jlYJ9a+UhyBe+ir0k7bBWm93VR5ohJtVXYGQOui9kcCZtpAG MzYT/Fn2jn5AH33XHTm/OOOt+lxz07jaUveKxd/yFWBZmWrLsHjpbnCusrdN1xlpmFHc of9A== ARC-Message-Signature: i=1; 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Wed, 22 Nov 2023 11:15:03 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783292826584486348 X-GMAIL-MSGID: 1783292826584486348 On non-QUSB2 targets (like the ones that use femto phys, M31 phy, eusb2 phy), many of the QCOM DTs are missing the IRQ for either hs_phy_irq or pwr_event. In one case, the hs_phy_irq was incorrectly defined with the latter's IRQ number. Since the DT must describe the hw whether or not the driver uses these interrupts, fix and add the missing entries in order to describe the HW completely and accurately. Signed-off-by: Krishna Kurapati --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 ++++- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 20 +++++++++++++------- arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++++- arch/arm64/boot/dts/qcom/sm6375.dtsi | 4 +++- arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 +++- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 +++- 11 files changed, 51 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 2aa5089a8513..7962d28cff01 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -586,10 +586,13 @@ usb: usb@a6f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts = , + , , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", + "pwr_event", + "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_GDSC>; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index e559adaaeee7..e6b3cfa5a575 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -499,10 +499,12 @@ usb: usb@a6f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, <&pdc 18 IRQ_TYPE_EDGE_BOTH>, <&pdc 19 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", + "pwr_event", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 13dd44dd9ed1..14dd916e6566 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1614,11 +1614,13 @@ usb_0: usb@a6f8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&pdc 15 IRQ_TYPE_EDGE_RISING>, <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "hs_phy_irq", + "pwr_event", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -1701,11 +1703,13 @@ usb_1: usb@a8f8800 { <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, <&pdc 8 IRQ_TYPE_EDGE_RISING>, <&pdc 7 IRQ_TYPE_EDGE_RISING>, <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "hs_phy_irq", + "pwr_event", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -1747,7 +1751,7 @@ usb_2_hsphy: phy@88e7000 { }; usb_2: usb@a4f8800 { - compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; + compatible = "qcom,sa8775p-dwc3-ter", "qcom,dwc3"; reg = <0 0x0a4f8800 0 0x400>; #address-cells = <2>; #size-cells = <2>; @@ -1764,10 +1768,12 @@ usb_2: usb@a4f8800 { <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_RISING>, <&pdc 9 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "pwr_event", + interrupt-names = "hs_phy_irq", + "pwr_event", "dp_hs_phy_irq", "dm_hs_phy_irq"; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 11f353d416b4..87c346127abb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2965,10 +2965,11 @@ usb_1: usb@a6f8800 { assigned-clock-rates = <19200000>, <150000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, <&pdc 8 IRQ_TYPE_LEVEL_HIGH>, <&pdc 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", "pwr_event","ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 04bf85b0399a..5b7ad3890018 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3433,7 +3433,7 @@ usb_dp_qmpphy_dp_in: endpoint { }; usb_2: usb@8cf8800 { - compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; + compatible = "qcom,sc7280-dwc3-sec", "qcom,dwc3"; reg = <0 0x08cf8800 0 0x400>; status = "disabled"; #address-cells = <2>; @@ -3457,9 +3457,11 @@ usb_2: usb@8cf8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_RISING>, <&pdc 13 IRQ_TYPE_EDGE_RISING>; interrupt-names = "hs_phy_irq", + "pwr_event", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -3712,10 +3714,12 @@ usb_1: usb@a6f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", + "pwr_event", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 2fba0e7ea4e6..45be399dca8e 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1403,11 +1403,13 @@ usb_1: usb@4ef8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <133333333>; - interrupts = , + interrupts = , + , , , ; interrupt-names = "hs_phy_irq", + "pwr_event", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 97623af13464..2e19ce0c738f 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3566,10 +3566,13 @@ usb_1: usb@a6f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts = , + , , , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", + "pwr_event", + "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -3619,10 +3622,13 @@ usb_2: usb@a8f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts = , + , , , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", + "pwr_event", + "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index be970472f6c4..ac0e96152aa7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4132,10 +4132,12 @@ usb_1: usb@a6f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", + "pwr_event", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; @@ -4200,10 +4202,12 @@ usb_2: usb@a8f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", + "pwr_event", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index b46236235b7f..dfe87affe57d 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2322,10 +2322,12 @@ usb_1: usb@a6f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", + "pwr_event", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; @@ -2395,10 +2397,12 @@ usb_2: usb@a8f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", + "pwr_event", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index bde9c1093384..be8e28c53098 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4302,11 +4302,13 @@ usb_1: usb@a6f8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", + "pwr_event", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7bafb3d88d69..06dcfba46cd7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2926,11 +2926,13 @@ usb_1: usb@a6f8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_RISING>, <&pdc 14 IRQ_TYPE_EDGE_RISING>; interrupt-names = "hs_phy_irq", + "pwr_event", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; From patchwork Wed Nov 22 19:14:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 168527 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1554530vqb; Wed, 22 Nov 2023 11:16:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IHYktjo7Iw18jokn57BhprwM/yAMCvu0eATc89klFm+S1uQNc2euSNgYK1pIYNwQqxIWrjl X-Received: by 2002:a05:6a20:be9c:b0:187:200a:713f with SMTP id gf28-20020a056a20be9c00b00187200a713fmr2402042pzb.23.1700680570265; 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Wed, 22 Nov 2023 19:15:07 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AMJF65h005461 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 19:15:06 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 22 Nov 2023 11:15:01 -0800 From: Krishna Kurapati To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , Krishna Kurapati Subject: [PATCH 5/6] arm64: dts: qcom: Fix hs_phy_irq for SDM670/SDM845/SM6350 Date: Thu, 23 Nov 2023 00:44:52 +0530 Message-ID: <20231122191452.3183-1-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 01symdIODD-064Tlo4RYvqdIl2p6ltn7 X-Proofpoint-GUID: 01symdIODD-064Tlo4RYvqdIl2p6ltn7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_13,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=628 lowpriorityscore=0 spamscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220139 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 22 Nov 2023 11:15:27 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783292829333858156 X-GMAIL-MSGID: 1783292829333858156 For sm6350/sdm670/sdm845, although they are qusb2 phy targets, dp/dm interrupts are used for wakeup instead of qusb2_phy irq. These targets were part of a generation that were the last ones to implement QUSB2 PHY and the design incorporated dedicated DP/DM interrupts which eventually carried forward to the newer femto based targets. Add the missing pwr_event irq for these targets. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++-- arch/arm64/boot/dts/qcom/sm6350.dtsi | 7 +++++-- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 6d9843d05cb3..b8888f71b1d6 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1296,10 +1296,13 @@ usb_1: usb@a6f8800 { assigned-clock-rates = <19200000>, <150000000>; interrupts = , + , , , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", + "pwr_event", + "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index bf5e6eb9d313..c3e90e54e329 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4054,10 +4054,13 @@ usb_1: usb@a6f8800 { assigned-clock-rates = <19200000>, <150000000>; interrupts = , + , , , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", + "pwr_event", + "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; @@ -4105,10 +4108,13 @@ usb_2: usb@a8f8800 { assigned-clock-rates = <19200000>, <150000000>; interrupts = , + , , , ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", + "pwr_event", + "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 8fd6f4d03490..af788e30eb45 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1839,12 +1839,15 @@ usb_1: usb@a6f8800 { "sleep", "mock_utmi"; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", + interrupt-names = "hs_phy_irq", + "pwr_event", + "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; From patchwork Wed Nov 22 19:15:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 168528 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1554541vqb; Wed, 22 Nov 2023 11:16:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IH2w92EdxcFCgbBOjb6noqhzmUgXukZxEVKFQe3LiAzUxy5PK1WRCJ5Ca/In0CsAy0GazMD X-Received: by 2002:a05:6a00:6c8e:b0:690:3b59:cc7b with SMTP id jc14-20020a056a006c8e00b006903b59cc7bmr3954625pfb.32.1700680571844; Wed, 22 Nov 2023 11:16:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700680571; cv=none; d=google.com; s=arc-20160816; b=VL/wxLdibxuUvfNgSlXElaVsMl+lXXkgVUsrPuLSi7NUv4dH7h7BMPYUEYiEE6LP6R fZfDJMjGYAlsyFAhaRASEVKkxI4wHwL18lOQca56WTUYM8cQNBd2NvjB+lS5gN7SlH+6 /Mns9oSHN6EVgIVQAIzC+3l/JBS1f3+ppU9MaSrkDxC7ITeegu9Z02AnkMmuKO/D9V6J ssbhtJ3js7Zzztd7zNdt+6Oqxu61h4oVJMMlgvsVITEhKYMci8BqKAs9pfzZzS8v2Fe1 eSKCez3y1wiiAjE8wiMIeklmXfMEwEQ8Q1VRmT5bi0EgI06Jew2oKtqfzbOlzfE7lgZx qcPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=utClqEmr27MkAijHvuNBs9lgq/CJJo8GkpIWHdMoop0=; fh=g59wItzuETADk8OZfORxAwr46gy/vgBLrfymtIBb3vA=; b=Hp9NFFuDVEreWEYhdy4WMfl3Zjc2T27CJqiGJSxfhCh8izgFZda/izY82+fxmZXiSl plOIoWa1QN9aEWo4Rz932kduBTrcHqq+tq45kE8erkPI3DNL4iCL/f2Pg32MCFTKfFaU +IkVpNtWNJW1FCPMPplB5mlE9yTx8t93oqI1TYC7Lc/z4UM1tdqMEUn6clHeHrP4YvKR 0ifctIfzYmkTQPeWdRkdcOqdcH1ISNxHgIsk9ZYdr2fNOQdLpae4k1nUkrNaHzXNPtRZ zsBIY9Mk8BH9w+V/oVw1b7DwaGzKh2Sfkg/eqsuFZ6hYxftVJs1nQxsw69BFREn1roSQ 5/zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=QTpgUJPV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from agentk.vger.email (agentk.vger.email. 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Add them to ensure they are in accordance to bindings. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 8 ++++++-- arch/arm64/boot/dts/qcom/qcs404.dtsi | 16 ++++++++++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 42e2e48b2bc3..79e0c763637f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -320,8 +320,12 @@ usb: usb@8af8800 { compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; reg = <0x08af8800 0x400>; - interrupts = ; - interrupt-names = "hs_phy_irq"; + interrupts = , + , + ; + interrupt-names = "dp_hs_phy_irq", + "dm_hs_phy_irq", + "pwr_event"; clocks = <&gcc GCC_USB0_MASTER_CLK>, <&gcc GCC_SNOC_USB_CLK>, diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 2721f32dfb71..20a5bc291a43 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -684,6 +684,14 @@ usb3: usb@7678800 { assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; + + interrupts = , + , + ; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy"; + status = "disabled"; usb3_dwc3: usb@7580000 { @@ -713,6 +721,14 @@ usb2: usb@79b8800 { assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>; assigned-clock-rates = <19200000>, <133333333>; + + interrupts = , + , + ; + interrupt-names = "hs_phy_irq", + "pwr_event", + "qusb2_phy"; + status = "disabled"; usb@78c0000 {