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Wed, 22 Nov 2023 05:42:19 -0800 (PST) From: Abel Vesa Date: Wed, 22 Nov 2023 15:42:12 +0200 Subject: [PATCH 1/2] dt-bindings: clock: qcom: Document the X1E80100 TCSR Clock Controller MIME-Version: 1.0 Message-Id: <20231122-x1e80100-clk-tcsrcc-v1-1-43078c6d6452@linaro.org> References: <20231122-x1e80100-clk-tcsrcc-v1-0-43078c6d6452@linaro.org> In-Reply-To: <20231122-x1e80100-clk-tcsrcc-v1-0-43078c6d6452@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2897; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=ABrzOdHYRscdBJgZXnNOaPRIjzqaXUQAEaqk/uMwhbk=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBlXgU3PRluQqdUeuBzlGbnF7n829L6a1tCWnvwM l1wl0OXeC6JAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZV4FNwAKCRAbX0TJAJUV VtitD/9TZeupU1efniF1r1nYwFg6Coy5n1fYHyAkyNUxMDoU7aWqQHBf0QqPKbQ1RUC4HfGnQe+ y/62OKh8F2Ok24X/oOZH/Bj2BaYoYzWDzVcrFssNssowTSMJ1ky2lUW/IJt6b0VGO1hHQaOFx0U RWqwWcJrlkTY4xfsRhKU7s3faWzQsWQLlE7mnS/pUQ1bJ1jB+O3UU9LAFPKoFnoWyRgPrfjopTg 5cWvmF17Wo+QGrk//X3rh9kCzyg2uZbY4P6QBr5uUznskb8nNPjl7FrczqMW5c3u2GObbsJJdRO kmI3kt1xSnZ63yUSrnpX5XtslugIAwKVl66ALQE5Xtdcb9FOjxzLVJWzHqGp4yTFIbSmy0uZzcV JAEnq5DjJ1lqs1VMi24XncNZXl/nprtmF7uEsffpd1Baf7upISet2zqDygwAJjsDmieTzCjaWzK i5mHSYrSTTz0ghybcTKOhNwxefGozxfWwqYtXchlOu8zPZNTPtL0ncZmPCYVmuqp8aXN7KyRplM uLQarmeVBZHtklb8FpltnT52BI1g3CJhOqiJdG3WZoAH3lZkVwPh0xk45gKdySlodKgGBfpseoX UZYdrYXez2koW/TYgZf/es5eRtN1kGv/aF7exvXbWSl67NLA79qB8s8Z4WkqhGVDk8l/iWqTnCJ QiLGkhC3aLdHH+Q== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 22 Nov 2023 05:42:30 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783271916668392905 X-GMAIL-MSGID: 1783271916668392905 Add bindings documentation for the X1E80100 TCSR Clock Controller. Co-developed-by: Rajendra Nayak Signed-off-by: Rajendra Nayak Signed-off-by: Abel Vesa --- .../bindings/clock/qcom,x1e80100-tcsr.yaml | 55 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,x1e80100-tcsr.h | 23 +++++++++ 2 files changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-tcsr.yaml new file mode 100644 index 000000000000..4adc8ee0287c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-tcsr.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,x1e80100-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on X1E80100 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on X1E80100 + + See also:: include/dt-bindings/clock/qcom,x1e80100-tcsr.h + +properties: + compatible: + items: + - const: qcom,x1e80100-tcsr + - const: syscon + + clocks: + items: + - description: TCXO pad clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + + clock-controller@1fc0000 { + compatible = "qcom,x1e80100-tcsr", "syscon"; + reg = <0x1fc0000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,x1e80100-tcsr.h b/include/dt-bindings/clock/qcom,x1e80100-tcsr.h new file mode 100644 index 000000000000..bae2c4654ee2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,x1e80100-tcsr.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H +#define _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H + +/* TCSR CC clocks */ +#define TCSR_PCIE_2L_4_CLKREF_EN 0 +#define TCSR_PCIE_2L_5_CLKREF_EN 1 +#define TCSR_PCIE_8L_CLKREF_EN 2 +#define TCSR_USB3_MP0_CLKREF_EN 3 +#define TCSR_USB3_MP1_CLKREF_EN 4 +#define TCSR_USB2_1_CLKREF_EN 5 +#define TCSR_UFS_PHY_CLKREF_EN 6 +#define TCSR_USB4_1_CLKREF_EN 7 +#define TCSR_USB4_2_CLKREF_EN 8 +#define TCSR_USB2_2_CLKREF_EN 9 +#define TCSR_PCIE_4L_CLKREF_EN 10 +#define TCSR_EDP_CLKREF_EN 11 + +#endif From patchwork Wed Nov 22 13:42:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 168376 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1331517vqb; Wed, 22 Nov 2023 05:43:48 -0800 (PST) X-Google-Smtp-Source: AGHT+IEXtkBuf+H8FtvdAe3J3l443cNTzY9B+aZRCLN++FrrRlwfO4yTMn6/GEO/ij5HpmOrOEk/ X-Received: by 2002:a05:6a20:8e0a:b0:18a:d4c5:2842 with SMTP id y10-20020a056a208e0a00b0018ad4c52842mr2341869pzj.33.1700660628380; Wed, 22 Nov 2023 05:43:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700660628; cv=none; d=google.com; s=arc-20160816; b=AcZDzSeU7BkQoKqi/PxcJCwRAbc169Ma+2ORASuFodBOF0XsiML+S7uCk5FTY0ymBe fFibRJFJsngPeRnIYCFk1nAeSQSnbIuonKG+FbOhgh1QqEJAZ6ZlBY5EkhPFIzt3hMMq DS2BCwyz2gZjEcMcbgYJN6ME34pm1adyDUNTkuKjgjXDnuGrsHXy777HNip1lTrXsPj6 hYJ1YQQVkTpJzQto50n0p3E6TK8dF770j9bqunSkuuhUlOEcHN6uuIPN+f9BlAytUgsV WVcRtbkREzBQSsIBuOhKAAjATPnFQVG4zoGIugS9UlhWO88yPIrRYN5mtuyOtXQ4iNMv PSVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=H6mwhJa9jnygGPwNgYYVXv0NiFDAvRFSYIV1gmbnIDI=; fh=anfNoCkYQeYStPV3P7wyVFOgRxdurOe+IG9YQOxaBrQ=; b=wa8mctoI4SdbE2Mm6K9LPQG7pb4WIWYwwNDSXNhKrgE0hDW8zo28Y0WKlXV/PzVbYM UUuPyz+Kz6EKXM4gyVjfmIdj9pWlRBF8vMUSG4mpmfKFZ143phplv8PAzU55b+UeL7TH 6XdgVcMmm5AcQNIAZ2xw6LPLK4F3kIPDpj8vP9p5juoTK5cAR0UlemWvGGBtr5IGrb7w Rfd02h9awwLR35PbG0CZIQCPIDO8Fnzj8P+BSUnt8mvdF9gnpXAO/LWIMY4MqbYDazsE KffJ0H3Il/9vHtejlLTKZ4e/ZhN1y8cQC8WWHgI/QekTfdu7O+cr39SmBbDwkh1bZuLJ AIpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oUlEpnlG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from snail.vger.email (snail.vger.email. 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Wed, 22 Nov 2023 05:42:21 -0800 (PST) From: Abel Vesa Date: Wed, 22 Nov 2023 15:42:13 +0200 Subject: [PATCH 2/2] clk: qcom: Add TCSR clock driver for x1e80100 MIME-Version: 1.0 Message-Id: <20231122-x1e80100-clk-tcsrcc-v1-2-43078c6d6452@linaro.org> References: <20231122-x1e80100-clk-tcsrcc-v1-0-43078c6d6452@linaro.org> In-Reply-To: <20231122-x1e80100-clk-tcsrcc-v1-0-43078c6d6452@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9515; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=Esmm2wUqNRcvaHakdFYdG/85Jq1N7KHQoM0n4w+Psoo=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBlXgU4ThMIEf2RqEc32R0glteHL9NG9wjaAEF5M nTCWUUIzt+JAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZV4FOAAKCRAbX0TJAJUV Vvm8EADNl/p9Cuhv6uozcS849Yd6Hg6d8BEGawc9l327vcppFQlrdeBoGGpYbepEZ22diIUzh/E hKdmfrjkieGSGyTotdXzxcFhlrYRMl645LsuWbDiHhnbOmFU1GRY4kY343RpKPe6fzT7l6awO7P zMJLso7XZA30rk0pA7h3nit01GF2JqUKkzan0OpSqcdJTTMfsO/hTQ2Do7XM7hy4Dyp/BmreFWP Y0ofgUL25SIJdAI3PCQGBToQeQ7tCAEsOOJWUJ55FXosCSSDkqNWxfRW86/87yE3PgeQ7sKnzKb IusBAfHs+sFLM9lcuGpcspvXBV3ZcMXL0nFCtFRv5sSAH7ujDd6YVQZuPXldqYXbXUO5oyJW3+M NqVDybeqtrOw9AAftSa49i/nQ84/qJNyFwwmKwhQGZxcMLbUsaEojilyylLUyiOxzFXHfah3BcU IbZb22VSrUET8nh7PgiXGmv7JfVnubI1EPC752P4UGobP1Fvz2s8WfnXiZAv5vRBwHVdT2DEV/2 prlZuUmniHAzgJqwyCJqEhIb2V6gxtmnK1+YIuLMVRABj+pO+VM85I/s0b+2/oX8y7hKTQO+3ev dArkDP1ZEVH5nUxhDFC5Vn1dXJf4DQT+S75upcZiR9qGLpjOG30XRIZZA5gbm0bH+lfaZ7bXa7g m565ofnzcJohpcg== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 22 Nov 2023 05:42:43 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783271918995700317 X-GMAIL-MSGID: 1783271918995700317 The TCSR clock controller found on X1E80100 provides refclks for PCIE, USB and UFS. Add clock driver for it. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/tcsrcc-x1e80100.c | 295 +++++++++++++++++++++++++++++++++++++ 3 files changed, 304 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ad1acd9b7426..6ed9c89d9070 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1116,4 +1116,12 @@ config SM_VIDEOCC_8450 SM8450 devices. Say Y if you want to support video devices and functionality such as video encode/decode. + +config X1E_TCSRCC_80100 + tristate "X1E80100 TCSR Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the TCSR clock controller on X1E80100 devices. + Say Y if you want to use peripheral devices such as SD/UFS. endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 17edd73f9839..4931a1470137 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -140,3 +140,4 @@ obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) += hfpll.o obj-$(CONFIG_KRAITCC) += krait-cc.o +obj-$(CONFIG_X1E_TCSRCC_80100) += tcsrcc-x1e80100.o diff --git a/drivers/clk/qcom/tcsrcc-x1e80100.c b/drivers/clk/qcom/tcsrcc-x1e80100.c new file mode 100644 index 000000000000..2ec142c3d1f9 --- /dev/null +++ b/drivers/clk/qcom/tcsrcc-x1e80100.c @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO_PAD, +}; + +static struct clk_branch tcsr_edp_clkref_en = { + .halt_reg = 0x15130, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x15130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "tcsr_edp_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_2l_4_clkref_en = { + .halt_reg = 0x15100, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x15100, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_pcie_2l_4_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_2l_5_clkref_en = { + .halt_reg = 0x15104, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x15104, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_pcie_2l_5_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_8l_clkref_en = { + .halt_reg = 0x15108, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x15108, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_pcie_8l_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_mp0_clkref_en = { + .halt_reg = 0x1510c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1510c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb3_mp0_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb3_mp1_clkref_en = { + .halt_reg = 0x15110, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x15110, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb3_mp1_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_1_clkref_en = { + .halt_reg = 0x15114, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x15114, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb2_1_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_ufs_phy_clkref_en = { + .halt_reg = 0x15118, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x15118, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_ufs_phy_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb4_1_clkref_en = { + .halt_reg = 0x15120, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x15120, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb4_1_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb4_2_clkref_en = { + .halt_reg = 0x15124, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x15124, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb4_2_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_usb2_2_clkref_en = { + .halt_reg = 0x15128, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x15128, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_usb2_2_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch tcsr_pcie_4l_clkref_en = { + .halt_reg = 0x1512c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1512c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_pcie_4l_clkref_en", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO_PAD, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *tcsr_cc_x1e80100_clocks[] = { + [TCSR_EDP_CLKREF_EN] = &tcsr_edp_clkref_en.clkr, + [TCSR_PCIE_2L_4_CLKREF_EN] = &tcsr_pcie_2l_4_clkref_en.clkr, + [TCSR_PCIE_2L_5_CLKREF_EN] = &tcsr_pcie_2l_5_clkref_en.clkr, + [TCSR_PCIE_8L_CLKREF_EN] = &tcsr_pcie_8l_clkref_en.clkr, + [TCSR_USB3_MP0_CLKREF_EN] = &tcsr_usb3_mp0_clkref_en.clkr, + [TCSR_USB3_MP1_CLKREF_EN] = &tcsr_usb3_mp1_clkref_en.clkr, + [TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr, + [TCSR_UFS_PHY_CLKREF_EN] = &tcsr_ufs_phy_clkref_en.clkr, + [TCSR_USB4_1_CLKREF_EN] = &tcsr_usb4_1_clkref_en.clkr, + [TCSR_USB4_2_CLKREF_EN] = &tcsr_usb4_2_clkref_en.clkr, + [TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr, + [TCSR_PCIE_4L_CLKREF_EN] = &tcsr_pcie_4l_clkref_en.clkr, +}; + +static const struct regmap_config tcsr_cc_x1e80100_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x2f000, + .fast_io = true, +}; + +static const struct qcom_cc_desc tcsr_cc_x1e80100_desc = { + .config = &tcsr_cc_x1e80100_regmap_config, + .clks = tcsr_cc_x1e80100_clocks, + .num_clks = ARRAY_SIZE(tcsr_cc_x1e80100_clocks), +}; + +static const struct of_device_id tcsr_cc_x1e80100_match_table[] = { + { .compatible = "qcom,x1e80100-tcsr" }, + { } +}; +MODULE_DEVICE_TABLE(of, tcsr_cc_x1e80100_match_table); + +static int tcsr_cc_x1e80100_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &tcsr_cc_x1e80100_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return qcom_cc_really_probe(pdev, &tcsr_cc_x1e80100_desc, regmap); +} + +static struct platform_driver tcsr_cc_x1e80100_driver = { + .probe = tcsr_cc_x1e80100_probe, + .driver = { + .name = "tcsr_cc-x1e80100", + .of_match_table = tcsr_cc_x1e80100_match_table, + }, +}; + +static int __init tcsr_cc_x1e80100_init(void) +{ + return platform_driver_register(&tcsr_cc_x1e80100_driver); +} +subsys_initcall(tcsr_cc_x1e80100_init); + +static void __exit tcsr_cc_x1e80100_exit(void) +{ + platform_driver_unregister(&tcsr_cc_x1e80100_driver); +} +module_exit(tcsr_cc_x1e80100_exit); + +MODULE_DESCRIPTION("QTI TCSRCC X1E80100 Driver"); +MODULE_LICENSE("GPL");