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Wed, 22 Nov 2023 02:56:00 -0800 (PST) From: Abel Vesa Date: Wed, 22 Nov 2023 12:55:48 +0200 Subject: [PATCH 1/2] dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles MIME-Version: 1.0 Message-Id: <20231122-phy-qualcomm-edp-x1e80100-v1-1-a9938990edb3@linaro.org> References: <20231122-phy-qualcomm-edp-x1e80100-v1-0-a9938990edb3@linaro.org> In-Reply-To: <20231122-phy-qualcomm-edp-x1e80100-v1-0-a9938990edb3@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abhinav Kumar Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=766; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=47x4DceRm3tCQ84A+H24YQKTKXLsUy4vs1DvIZFUxYo=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBlXd47jtfoUWWWq1bSqU5Il/tnuIoOdQpW46XIB ejEpLcuctSJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZV3eOwAKCRAbX0TJAJUV VjfFEACOweqBEkv+85EBXxiL/6SI2rTG89ykNUyuIxr/hAg7E8yEfgJQNU+DFBDZrbP4NsbgRQr GDwgrFa3N2TkZSq/XJxsZ535oofKqv30jeGqLGEDd4lEctQKR58ey0OUBreHNxm4imBIgOo1O4P PIAzNgkhwTvbIKTcWzxKaolAwctveJRGAW9ivxIP2I6aOv7AqPnKDzqa+7X+69t2A9dLn5xHKGs LEKTHQJi593z5YY/aPOirGjuoUH+Cb+/ScS/iDfdIPz7756NWP+4RvZFK5D7veybgrf3x9WurMx jbKQLGPL4Jm2Iu8/lGQfc/8eapOXzt5t0FEJdFhr6r9Ct4wuGxv5SC07F6hXgXlSb0Q984DgEA4 sbQzAPWVycUoG/bpnSmwE1m/aJ5WpiAhLjoNvvE9zO+Hzcr5dXCe+WpuXiS0cZaaebwBN7xYKAq Er7BFU+IsuEe1BVm32KNZ2IEgf0SwcB8Qy7CqP7UwNZ86bDZTr5LKkaR1OJyDuR2ntNhX4sezlu 7iQy3zr6NKkvhH+BGZlDsOD2PJnAM4yeDSSJobyeBY+/T9C34/oyNrHz5O26fL61bfKQ7DA5aSm Hvnyc74+Yl+E2eCrL5Ai6uXx5GZrdTGcavIRaznNSNXZgbrYvknQxoz6sw+5LbXV6KgZMuCdcss Yfc2gvdMo9RqZ9g== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 22 Nov 2023 02:56:41 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783261406750363819 X-GMAIL-MSGID: 1783261406750363819 The Qualcomm X1E80100 platform has both eDP and DP PHYs, add compatibles for these. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml index 6566353f1a02..190f61c1d0f9 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -21,6 +21,8 @@ properties: - qcom,sc8180x-edp-phy - qcom,sc8280xp-dp-phy - qcom,sc8280xp-edp-phy + - qcom,x1e80100-dp-phy + - qcom,x1e80100-edp-phy reg: items: From patchwork Wed Nov 22 10:55:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 168306 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1235623vqb; Wed, 22 Nov 2023 02:57:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IGtBBHnvP8M0DKkYMQBYSlc9vyWE4KOZz5bbZFzAA+JUuqDeRv/PiegNx+6Tt56gYK78Kiz X-Received: by 2002:a05:6a00:1993:b0:693:3851:bd3e with SMTP id d19-20020a056a00199300b006933851bd3emr2227452pfl.3.1700650626294; Wed, 22 Nov 2023 02:57:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700650626; cv=none; d=google.com; s=arc-20160816; b=CUBk9RNBi9ycNfkqr9FTIxv1X9SCTnQ2WIok7NR32dMLRJGm2695RKSqEdOIIT9tmv BVP9yKJYW5zOdkMPbC/6ydaYbztXSgXpvABWX7rR66w6YykMdjlURYEpQboyMmG1QA/u RQh3teFf5AZmtdFDni3fVQvP36g9KxnKh8gyT4U0olnFgpIwhGCPJkb2lWEBLxqALhHF +IAm0bnseoIW7AUEGVnEEIZPIeWVbNSnCVfKbG7oJB1VZn2xCuObGUgNzyD/77bap3fN bX1AOU2JT8Mnf5sGOjVhEiZTZb9sjwglUUkg0CgxvTa3Pm+b0SKCMTYY4Eci3t6NgaM7 PXjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=l8v79Ra7yNmy/zYFfkwbdCIxwjcgjrpT8Dlidgl8zj0=; fh=dQDR6SoLhUV1cAs9fWD+rtP/iFpTaXxaH8LbEX7jsD0=; b=t8Y+Oe/S4vpFULJ/MwYtMGLnst1gYbSczXyXnKirRzojOK9301TTMcZJNGzCO8DMnv eDWAWVAh2YfQi/mhQWrFq7r7zRJOfv94kF4IMpxNMOliEHluFUeirKhugbwwC+XzQPyL 3PVxf0gXXum6tL+QU+67hr0hCXJXiTRFyEvecr0PvrdPQbG/ZoI2kYW4/pjrT04tnVUH eeExAVz5Qk5uW9AqkGPup1RFE/WF+BaKADGU8drj7kNNS3tt8jYHSyqpat7T9tmu2xOT TtPZZrY2vWfLFvRFr4BhiRjS2jZT7O+xgVcVXSNPZDC/mbD1qaYfUcQhLOWaiok68MwU ghNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WZtnSYLg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from groat.vger.email (groat.vger.email. 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Wed, 22 Nov 2023 02:56:01 -0800 (PST) From: Abel Vesa Date: Wed, 22 Nov 2023 12:55:49 +0200 Subject: [PATCH 2/2] phy: qcom: edp: Add X1E80100 eDP and DP PHYs MIME-Version: 1.0 Message-Id: <20231122-phy-qualcomm-edp-x1e80100-v1-2-a9938990edb3@linaro.org> References: <20231122-phy-qualcomm-edp-x1e80100-v1-0-a9938990edb3@linaro.org> In-Reply-To: <20231122-phy-qualcomm-edp-x1e80100-v1-0-a9938990edb3@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abhinav Kumar Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=18444; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=4YKbDtZQj3SgbS35Bun/mHMEGFn9U/6lt6EhrBBnQXc=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBlXd48t8DQXYXx9bRMWIiawcBiZKo4U4qtXSRiv FEoHgidtaOJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZV3ePAAKCRAbX0TJAJUV VoeGD/48JqTTxvCjYqRYnioUvjxe4YZc1T3PaPeRy2RRgzUOdsV1JyvEan6EfUUBtPon4LBo1Bn 3pDlxAOm2ERngGBILoi/CsBtj7qVo1XcUVJ4nCZHIq80XnFnYUXo1hG8O6hp/7HdL7zxEcvth7S 9gmu/rKwsMJp0BIT4kGjHPhzZB7kluEOYNWxBs+IbOnRkdvz0flGc/KeqGPTRxUjjWW4WDpDaDZ PxSbz6uAz6fS3do+bThsDvrs76rEKiiPeAPMdURFuFHz21k/0JgKT/s+h2BeDDRrSLv3WPGazep gefT96VCjvetR+YgHWyf2epWIW4XSMuOCyUojjrCAoWa9IcWT72wbznLZkAF5HRrOHyNOH/JS2v cPHZUEg/6Uv5tGKIKa5ZK4Mx5lrfFQV5rnCKLnU+lkA2MjmdhSVUOC/rh2ZDp4gMPbpg6GJRdBN CHlBG/qKaOEf8Lu2QSFYm1PAjk+vYtaCQY7kfXkr3cCV6Xe1dt4UDrD1WLr08fqHw0HA44qAIvT GD/RuaLJwwoWV3jlJ/EnCXkRJp5NYffLHKkU/TH6Qh0cIBuiZsGYw4xa1ar3kNB9zr3+AE5nvbS TinSm565e4DmZiTiWHZ06ez3tVGKGoNbtGFEQvxwT18LNXF7shV+NIQW4ZNwWUP8JXdfH09+hJN jz+/LWunEe9VcwA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 22 Nov 2023 02:57:02 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783261431254231669 X-GMAIL-MSGID: 1783261431254231669 The Qualcomm X1E80100 platform has a number of eDP and DP PHY instances, add support for these. Co-developed-by: Abhinav Kumar Signed-off-by: Abhinav Kumar Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-edp.c | 305 +++++++++++++++++++++++++++--------- 1 file changed, 231 insertions(+), 74 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index 8e5078304646..9eca9a8f8824 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -23,6 +23,9 @@ #include "phy-qcom-qmp.h" +#define QSERDES_V4 0 +#define QSERDES_V6 1 + /* EDP_PHY registers */ #define DP_PHY_CFG 0x0010 #define DP_PHY_CFG_1 0x0014 @@ -70,6 +73,7 @@ struct qcom_edp_cfg { bool is_dp; + int qserdes_version; /* DP PHY swing and pre_emphasis tables */ const u8 (*swing_hbr_rbr)[4][4]; @@ -94,7 +98,7 @@ struct qcom_edp { struct phy_configure_opts_dp dp_opts; - struct clk_bulk_data clks[2]; + struct clk_bulk_data clks[3]; struct regulator_bulk_data supplies[2]; }; @@ -126,8 +130,18 @@ static const u8 dp_pre_emp_hbr2_hbr3[4][4] = { { 0x04, 0xff, 0xff, 0xff } }; -static const struct qcom_edp_cfg dp_phy_cfg = { +static const struct qcom_edp_cfg dp_v4_phy_cfg = { .is_dp = true, + .qserdes_version = QSERDES_V4, + .swing_hbr_rbr = &dp_swing_hbr_rbr, + .swing_hbr3_hbr2 = &dp_swing_hbr2_hbr3, + .pre_emphasis_hbr_rbr = &dp_pre_emp_hbr_rbr, + .pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3, +}; + +static const struct qcom_edp_cfg dp_v6_phy_cfg = { + .is_dp = true, + .qserdes_version = QSERDES_V6, .swing_hbr_rbr = &dp_swing_hbr_rbr, .swing_hbr3_hbr2 = &dp_swing_hbr2_hbr3, .pre_emphasis_hbr_rbr = &dp_pre_emp_hbr_rbr, @@ -162,8 +176,18 @@ static const u8 edp_pre_emp_hbr2_hbr3[4][4] = { { 0x00, 0xff, 0xff, 0xff } }; -static const struct qcom_edp_cfg edp_phy_cfg = { +static const struct qcom_edp_cfg edp_v4_phy_cfg = { + .is_dp = false, + .qserdes_version = QSERDES_V4, + .swing_hbr_rbr = &edp_swing_hbr_rbr, + .swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3, + .pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr, + .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3, +}; + +static const struct qcom_edp_cfg edp_v6_phy_cfg = { .is_dp = false, + .qserdes_version = QSERDES_V6, .swing_hbr_rbr = &edp_swing_hbr_rbr, .swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3, .pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr, @@ -190,7 +214,10 @@ static int qcom_edp_phy_init(struct phy *phy) edp->edp + DP_PHY_PD_CTL); /* Turn on BIAS current for PHY/PLL */ - writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); + if (cfg->qserdes_version == QSERDES_V4) + writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); + else if (cfg->qserdes_version == QSERDES_V6) + writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); msleep(20); @@ -205,6 +232,8 @@ static int qcom_edp_phy_init(struct phy *phy) else cfg8 = 0x37; + cfg8 = 0x37; + writel(0xfc, edp->edp + DP_PHY_MODE); writel(0x00, edp->edp + DP_PHY_AUX_CFG0); @@ -261,7 +290,10 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configur if (swing == 0xff || emph == 0xff) return -EINVAL; - ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0; + if (cfg->qserdes_version == QSERDES_V4) + ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0; + else if (cfg->qserdes_version == QSERDES_V6) + ldo_config |= 0x91; writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); writel(swing, edp->tx0 + TXn_TX_DRV_LVL); @@ -291,6 +323,7 @@ static int qcom_edp_phy_configure(struct phy *phy, union phy_configure_opts *opt static int qcom_edp_configure_ssc(const struct qcom_edp *edp) { const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; + const struct qcom_edp_cfg *cfg = edp->cfg; u32 step1; u32 step2; @@ -298,13 +331,24 @@ static int qcom_edp_configure_ssc(const struct qcom_edp *edp) case 1620: case 2700: case 8100: - step1 = 0x45; - step2 = 0x06; + if (cfg->qserdes_version == QSERDES_V4) { + step1 = 0x45; + step2 = 0x06; + } else if (cfg->qserdes_version == QSERDES_V6) { + step1 = 0x92; + step2 = 0x01; + } break; case 5400: - step1 = 0x5c; - step2 = 0x08; + if (cfg->qserdes_version == QSERDES_V4) { + step1 = 0x5c; + step2 = 0x08; + } else if (cfg->qserdes_version == QSERDES_V6) { + step1 = 0x18; + step2 = 0x02; + } + break; default: @@ -312,12 +356,21 @@ static int qcom_edp_configure_ssc(const struct qcom_edp *edp) return -EINVAL; } - writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER); - writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1); - writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1); - writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2); - writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0); - writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0); + if (cfg->qserdes_version == QSERDES_V4) { + writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER); + writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1); + writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1); + writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2); + writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0); + writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0); + } else if (cfg->qserdes_version == QSERDES_V6) { + writel(0x01, edp->pll + QSERDES_V6_COM_SSC_EN_CENTER); + writel(0x00, edp->pll + QSERDES_V6_COM_SSC_ADJ_PER1); + writel(0x6b, edp->pll + QSERDES_V6_COM_SSC_PER1); + writel(0x02, edp->pll + QSERDES_V6_COM_SSC_PER2); + writel(step1, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0); + writel(step2, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0); + } return 0; } @@ -325,48 +378,99 @@ static int qcom_edp_configure_ssc(const struct qcom_edp *edp) static int qcom_edp_configure_pll(const struct qcom_edp *edp) { const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; + const struct qcom_edp_cfg *cfg = edp->cfg; u32 div_frac_start2_mode0; u32 div_frac_start3_mode0; u32 dec_start_mode0; u32 lock_cmp1_mode0; u32 lock_cmp2_mode0; + u32 code1_mode0; + u32 code2_mode0; u32 hsclk_sel; switch (dp_opts->link_rate) { case 1620: hsclk_sel = 0x5; - dec_start_mode0 = 0x69; - div_frac_start2_mode0 = 0x80; - div_frac_start3_mode0 = 0x07; - lock_cmp1_mode0 = 0x6f; - lock_cmp2_mode0 = 0x08; + + if (cfg->qserdes_version == QSERDES_V4) { + dec_start_mode0 = 0x69; + div_frac_start2_mode0 = 0x80; + div_frac_start3_mode0 = 0x07; + lock_cmp1_mode0 = 0x6f; + lock_cmp2_mode0 = 0x08; + } else if (cfg->qserdes_version == QSERDES_V6) { + dec_start_mode0 = 0x34; + div_frac_start2_mode0 = 0xc0; + div_frac_start3_mode0 = 0x0b; + lock_cmp1_mode0 = 0x37; + lock_cmp2_mode0 = 0x04; + code1_mode0 = 0x71; + code2_mode0 = 0x0C; + } + break; case 2700: hsclk_sel = 0x3; - dec_start_mode0 = 0x69; - div_frac_start2_mode0 = 0x80; - div_frac_start3_mode0 = 0x07; - lock_cmp1_mode0 = 0x0f; - lock_cmp2_mode0 = 0x0e; + + if (cfg->qserdes_version == QSERDES_V4) { + dec_start_mode0 = 0x69; + div_frac_start2_mode0 = 0x80; + div_frac_start3_mode0 = 0x07; + lock_cmp1_mode0 = 0x0f; + lock_cmp2_mode0 = 0x0e; + } else if (cfg->qserdes_version == QSERDES_V6) { + dec_start_mode0 = 0x34; + div_frac_start2_mode0 = 0xc0; + div_frac_start3_mode0 = 0x0b; + lock_cmp1_mode0 = 0x07; + lock_cmp2_mode0 = 0x07; + code1_mode0 = 0x71; + code2_mode0 = 0x0C; + } + break; case 5400: hsclk_sel = 0x1; - dec_start_mode0 = 0x8c; - div_frac_start2_mode0 = 0x00; - div_frac_start3_mode0 = 0x0a; - lock_cmp1_mode0 = 0x1f; - lock_cmp2_mode0 = 0x1c; + + if (cfg->qserdes_version == QSERDES_V4) { + dec_start_mode0 = 0x8c; + div_frac_start2_mode0 = 0x00; + div_frac_start3_mode0 = 0x0a; + lock_cmp1_mode0 = 0x1f; + lock_cmp2_mode0 = 0x1c; + } else if (cfg->qserdes_version == QSERDES_V6) { + dec_start_mode0 = 0x46; + div_frac_start2_mode0 = 0x00; + div_frac_start3_mode0 = 0x05; + lock_cmp1_mode0 = 0x0f; + lock_cmp2_mode0 = 0x0e; + code1_mode0 = 0x97; + code2_mode0 = 0x10; + } + break; case 8100: hsclk_sel = 0x0; - dec_start_mode0 = 0x69; - div_frac_start2_mode0 = 0x80; - div_frac_start3_mode0 = 0x07; - lock_cmp1_mode0 = 0x2f; - lock_cmp2_mode0 = 0x2a; + + if (cfg->qserdes_version == QSERDES_V4) { + dec_start_mode0 = 0x69; + div_frac_start2_mode0 = 0x80; + div_frac_start3_mode0 = 0x07; + lock_cmp1_mode0 = 0x2f; + lock_cmp2_mode0 = 0x2a; + } else if (cfg->qserdes_version == QSERDES_V6) { + dec_start_mode0 = 0x34; + div_frac_start2_mode0 = 0xc0; + div_frac_start3_mode0 = 0x0b; + lock_cmp1_mode0 = 0x17; + lock_cmp2_mode0 = 0x15; + code1_mode0 = 0x71; + code2_mode0 = 0x0C; + } + break; default: @@ -374,36 +478,70 @@ static int qcom_edp_configure_pll(const struct qcom_edp *edp) return -EINVAL; } - writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL); - writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL); - writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL); - writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1); - writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE); - writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT); - writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL); - writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO); - writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN); - writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0); - writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0); - writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0); - writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0); - writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0); - writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0); - writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0); - writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG); - writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0); - writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0); - writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP); - writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0); - writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0); - - writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER); - writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0); - writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL); - writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); - writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN); - writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0); - writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0); + if (cfg->qserdes_version == QSERDES_V4) { + writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL); + writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL); + writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL); + writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1); + writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE); + writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT); + writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL); + writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO); + writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN); + writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0); + writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0); + writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0); + writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0); + writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0); + writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0); + writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0); + writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG); + writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0); + writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0); + writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP); + writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0); + writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0); + + writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER); + writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0); + writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL); + writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); + writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN); + writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0); + writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0); + } else if (cfg->qserdes_version == QSERDES_V6) { + writel(0x01, edp->pll + QSERDES_V6_COM_SVS_MODE_CLK_SEL); + writel(0x0b, edp->pll + QSERDES_V6_COM_SYSCLK_EN_SEL); + writel(0x02, edp->pll + QSERDES_V6_COM_SYS_CLK_CTRL); + writel(0x0c, edp->pll + QSERDES_V6_COM_CLK_ENABLE1); + writel(0x06, edp->pll + QSERDES_V6_COM_SYSCLK_BUF_ENABLE); + writel(0x30, edp->pll + QSERDES_V6_COM_CLK_SELECT); + writel(hsclk_sel, edp->pll + QSERDES_V6_COM_HSCLK_SEL_1); + writel(0x07, edp->pll + QSERDES_V6_COM_PLL_IVCO); + writel(0x08, edp->pll + QSERDES_V6_COM_LOCK_CMP_EN); + writel(0x36, edp->pll + QSERDES_V6_COM_PLL_CCTRL_MODE0); + writel(0x16, edp->pll + QSERDES_V6_COM_PLL_RCTRL_MODE0); + writel(0x6, edp->pll + QSERDES_V6_COM_CP_CTRL_MODE0); + writel(dec_start_mode0, edp->pll + QSERDES_V6_COM_DEC_START_MODE0); + writel(0x00, edp->pll + QSERDES_V6_COM_DIV_FRAC_START1_MODE0); + writel(div_frac_start2_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START2_MODE0); + writel(div_frac_start3_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START3_MODE0); + writel(0x12, edp->pll + QSERDES_V6_COM_CMN_CONFIG_1); + writel(0x3f, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0); + writel(0x00, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0); + writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_MAP); + writel(lock_cmp1_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP1_MODE0); + writel(lock_cmp2_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP2_MODE0); + + writel(0x0a, edp->pll + QSERDES_V6_COM_BG_TIMER); + writel(0x14, edp->pll + QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0); + writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_CTRL); + writel(0x17, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); + writel(0x0f, edp->pll + QSERDES_V6_COM_CORE_CLK_EN); + + writel(code1_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0); + writel(code2_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0); + } return 0; } @@ -462,13 +600,21 @@ static int qcom_edp_phy_power_on(struct phy *phy) edp->edp + DP_PHY_PD_CTL); writel(0xfc, edp->edp + DP_PHY_MODE); - timeout = readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS, - val, val & BIT(7), 5, 200); + if (cfg->qserdes_version == QSERDES_V4) { + timeout = readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS, + val, val & BIT(7), 5, 200); + } else if (cfg->qserdes_version == QSERDES_V6) { + timeout = readl_poll_timeout(edp->pll + QSERDES_V6_COM_CMN_STATUS, + val, val & BIT(7), 5, 200); + } if (timeout) return timeout; - ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0; + if (cfg->qserdes_version == QSERDES_V4) + ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0; + else if (cfg->qserdes_version == QSERDES_V6) + ldo_config |= 0x91; writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); @@ -512,10 +658,18 @@ static int qcom_edp_phy_power_on(struct phy *phy) writel(0x01, edp->edp + DP_PHY_CFG); writel(0x09, edp->edp + DP_PHY_CFG); - writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); + if (cfg->qserdes_version == QSERDES_V4) { + writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); + + timeout = readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS, + val, val & BIT(0), 500, 10000); + } else if (cfg->qserdes_version == QSERDES_V6) { + writel(0x20, edp->pll + QSERDES_V6_COM_RESETSM_CNTRL); + + timeout = readl_poll_timeout(edp->pll + QSERDES_V6_COM_C_READY_STATUS, + val, val & BIT(0), 500, 10000); + } - timeout = readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS, - val, val & BIT(0), 500, 10000); if (timeout) return timeout; @@ -744,7 +898,6 @@ static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np) data = devm_kzalloc(edp->dev, struct_size(data, hws, 2), GFP_KERNEL); if (!data) return -ENOMEM; - data->num = 2; snprintf(name, sizeof(name), "%s::link_clk", dev_name(edp->dev)); init.ops = &qcom_edp_dp_link_clk_ops; @@ -764,6 +917,7 @@ static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np) data->hws[0] = &edp->dp_link_hw; data->hws[1] = &edp->dp_pixel_hw; + data->num = 2; return devm_of_clk_add_hw_provider(edp->dev, of_clk_hw_onecell_get, data); } @@ -806,6 +960,7 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) edp->supplies[0].supply = "vdda-phy"; edp->supplies[1].supply = "vdda-pll"; + edp->clks[2].id = "tcsr"; ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(edp->supplies), edp->supplies); if (ret) return ret; @@ -841,8 +996,10 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) static const struct of_device_id qcom_edp_phy_match_table[] = { { .compatible = "qcom,sc7280-edp-phy" }, { .compatible = "qcom,sc8180x-edp-phy" }, - { .compatible = "qcom,sc8280xp-dp-phy", .data = &dp_phy_cfg }, - { .compatible = "qcom,sc8280xp-edp-phy", .data = &edp_phy_cfg }, + { .compatible = "qcom,sc8280xp-dp-phy", .data = &dp_v4_phy_cfg }, + { .compatible = "qcom,sc8280xp-edp-phy", .data = &edp_v4_phy_cfg }, + { .compatible = "qcom,x1e80100-dp-phy", .data = &dp_v6_phy_cfg }, + { .compatible = "qcom,x1e80100-edp-phy", .data = &edp_v6_phy_cfg }, { } }; MODULE_DEVICE_TABLE(of, qcom_edp_phy_match_table);