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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id p2-20020a0cfd82000000b00677b0bbcce3si10663048qvr.159.2023.11.22.02.53.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Nov 2023 02:53:56 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7CCE63858419 for ; Wed, 22 Nov 2023 10:53:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by sourceware.org (Postfix) with ESMTPS id A42053858D35 for ; Wed, 22 Nov 2023 10:53:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A42053858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A42053858D35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=18.132.163.193 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700650414; cv=none; b=vCAE0u38JyVxguVUbYEG9QG2ytHggYmE8S/edEc5JSE6qWZI8aG706CSaZeOWBrsl8Pv49JT4LvjXjMCCdz5pj/UazQQTKiwMGpc6yLGkq+plg3a4R3j8ZO1ekV5Uk0Y7UtvXup0f9Pn97lv9lX81SrjWoGfCxuYAOLtugPBgJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700650414; c=relaxed/simple; bh=YJ0Fi9wZwJTN7ld84AsQ/QNiLZmMvWqs06WIFDMylCI=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=SIuJe+VMDO0jgLDmqEwpzfqTFpng5ri5XZfjky2uw4KSEYtFqmh8dWpAf0ao13zKNnfuWNtk6RB9qbbvucabZ75QRZO/Kr1XhRj0CB0vTvuhsh2aCFlmE8o1bhkdtQH6FeGmeqeYlKV/Tsfa8pCY7nuc5DlgAKwd17z9n1dHZOw= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp72t1700650405t2y4wju8 Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Nov 2023 18:53:23 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: LrCnY+iDm+OPGz9DFUkTm9klnAzAtHs5Hj/TLniyHKafxO7gNSUKmuC5cNufS /qdhQDiIeJpgsKTXYTrAILfG+TfPRVRH+9W/giu3Kqq0f/f0z8Eahu83/3WKlbIa4lTbe58 QWKYpWtOVOc6RB1QeoyWHOL1NiLdTfHgQE6BBC6F9ROH2g9LedqTi6BOSH12BaPZRtWbYJJ GEJeAu4skghZPOHgREQDHBLsAMe/enHkX8KM3+3PFRfpY+K90zxaDDQjylcpZWUsK30yk8/ L9pkFrsGl3b0ggloXeURnbrI96hQUbneXSEu307GDwGPMesbViceTnI9VZ9/vp0gPqcUGiA yRl951Cq2ABJmvFoUL2dF6pleHk3mjPzx5gbNg0LzzILRD+SUEdPvlaDigj7Trx7AwUuOnD Fr0gwNCsU4w= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 15130413574638789503 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix incorrect use of vcompress in permutation auto-vectorization Date: Wed, 22 Nov 2023 18:53:22 +0800 Message-Id: <20231122105322.1478693-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783261232414631444 X-GMAIL-MSGID: 1783261232414631444 This patch fixes following FAILs on zvl512b of RV32 system: FAIL: gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c execution test FAIL: gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c execution test The root cause is that for permutation indice = {0,3,7,0} use vcompress optimization which is incorrect. Fix vcompress optimization bug. PR target/112598 gcc/ChangeLog: * config/riscv/riscv-v.cc (shuffle_compress_patterns): Fix vcompress bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112598-3.c: New test. --- gcc/config/riscv/riscv-v.cc | 15 ++++++------- .../gcc.target/riscv/rvv/autovec/pr112598-3.c | 21 +++++++++++++++++++ 2 files changed, 29 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-3.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 7d6d0821d87..7d3e8038dab 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3005,14 +3005,15 @@ shuffle_compress_patterns (struct expand_vec_perm_d *d) if (compress_point < 0) return false; - /* It must be series increasing from compress point. */ - if (!d->perm.series_p (compress_point, 1, d->perm[compress_point], 1)) - return false; - /* We can only apply compress approach when all index values from 0 to compress point are increasing. */ for (int i = 1; i < compress_point; i++) - if (known_le (d->perm[i], d->perm[i - 1])) + if (maybe_le (d->perm[i], d->perm[i - 1])) + return false; + + /* It must be series increasing from compress point. */ + for (int i = 1 + compress_point; i < vlen; i++) + if (maybe_ne (d->perm[i], d->perm[i - 1] + 1)) return false; /* Success! */ @@ -3080,10 +3081,10 @@ shuffle_compress_patterns (struct expand_vec_perm_d *d) if (need_slideup_p) { int slideup_cnt = vlen - (d->perm[vlen - 1].to_constant () % vlen) - 1; - rtx ops[] = {d->target, d->op1, gen_int_mode (slideup_cnt, Pmode)}; + merge = gen_reg_rtx (vmode); + rtx ops[] = {merge, d->op1, gen_int_mode (slideup_cnt, Pmode)}; insn_code icode = code_for_pred_slide (UNSPEC_VSLIDEUP, vmode); emit_vlmax_insn (icode, BINARY_OP, ops); - merge = d->target; } insn_code icode = code_for_pred_compress (vmode); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-3.c new file mode 100644 index 00000000000..231a068c680 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvfh_zfh_zvl512b -mabi=ilp32d -O3 -ftree-vectorize -std=c99 -fno-vect-cost-model" } */ + +#include +#define TYPE uint64_t +#define ITYPE int64_t + +void __attribute__ ((noinline, noclone)) +foo (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + d[i * 3] = a[i]; + d[i * 3 + 1] = b[i]; + d[i * 3 + 2] = c[i]; + } +} + +/* We don't want vcompress.vv. */ +/* { dg-final { scan-assembler-not {vcompress\.vv} } } */