From patchwork Wed Nov 22 07:10:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 168122 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1145620vqb; Tue, 21 Nov 2023 23:12:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IHtTuAn66EsPIFzfcst8djT3kpr3NxKKu0nYVa2KJh0uvM5p5tPdbX/sy09qHKekVubq1X5 X-Received: by 2002:a9d:7481:0:b0:6b8:f588:2c79 with SMTP id t1-20020a9d7481000000b006b8f5882c79mr1644288otk.1.1700637137422; Tue, 21 Nov 2023 23:12:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700637137; cv=none; d=google.com; s=arc-20160816; b=R5ZTGy55ZIg8D2NXXO/JpNpfnbZ8TaceYvpRMmZFm9qAJ7e/YPHRrw+Ke3zuI+g5JN zc9vfxnS0kxMeUMlKQY3Hn7GFQs1c68RejWuGosLCdDFf3/3IMCPNvOBjmE+h6M8KKBT HP6GQJAEEzfnm3r9FSI7u+FcSDpZpFKeLYUuZ16qwP9NsMo9t7kNkUuSk7jOQPh4uoDO Fa/ZFUP/fOxnRpXd4jWNSNVBdnSaM1HZT6BZJ05bFErkCpS7YRjbixvja3hKP6+S8Jhl PLKS4y0t22gF3410YBc8ZYt1YXFw1wrSOVlc7hOiEIRNuubwZ+pxuvndBVoGoGjLOo6c fUbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=eGdUvC/zd6Q/5MxjneStcUeitt7DJD3M5D51wFgBbyI=; fh=8SdF4K1KK7pEKn38j7q5d1etiWtimrbQeeFaAR6jIjM=; b=suwNWuXNI+cKxpDpzCuVflv/wtSZ3O1YJ3rEBltkxc9zACEPG0pB8iNdlzs6D5Qt0q zH8zsVxUmKtjKzmbbyuu73faGwsGudToDa9Awf6BlAUioP6xd03PnFP124dy7Nkl1sc9 +P3ZUAhy877YqW2NXmux2LWEzF3aVYizeUYwdv0tmYLabqwetO/KeqXe4X3TUZPKcE5k JsWUkd9pp7t+KhkowxorDryqC3I0rP02PAv18PZmBgJSN37faGx6RBwvnTN4S14jbUMs NGLuAMzisOsKP6HxVjQnwoGv2QVCBLBCHRtRlY/0PHWcFNNfUIawmwKyRPNFuWIk3MXY XROw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=QPD6tiiI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from fry.vger.email (fry.vger.email. [23.128.96.38]) by mx.google.com with ESMTPS id v6-20020a63f206000000b005b95ccd1b4dsi11145175pgh.82.2023.11.21.23.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 23:12:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=QPD6tiiI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 5FCAA80FE2B6; Tue, 21 Nov 2023 23:12:01 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234984AbjKVHLu (ORCPT + 99 others); Wed, 22 Nov 2023 02:11:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229991AbjKVHLk (ORCPT ); Wed, 22 Nov 2023 02:11:40 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2046BD58; Tue, 21 Nov 2023 23:11:35 -0800 (PST) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AM4g1DJ021863; Wed, 22 Nov 2023 07:11:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=eGdUvC/zd6Q/5MxjneStcUeitt7DJD3M5D51wFgBbyI=; b=QPD6tiiIWvhkvGmOEnbhquKnx9gU4usCXAANMJ2MFIRtaDFGQe8GlYQEkEgTzhpUY16w phGtBdDMo3kkuAxp60jhPGMDZIWdgFzxuVDHwf2Wji2lz+UsBMl/KcGA/xovFjjY6PkR 0LZvT1nWZFdnlYwAjZ4AiMaoccvgv06gHMmBfh/w93Qqd0lUmMvo+iFG7mTE9ZJq0sRk kTJh8R8flGnVkxl19iSgrn9nfzCP+EFHhphN41F8DxvaV3kVJiNtLfcgUMIJky5zifCc /F48E21ERWFyNwkTMEWIMWKVG6susB5VDDarH5l/CcvIQwxATx9dCpHyKU3JGAtpqre8 eA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugu54avpc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 07:11:02 +0000 Received: from pps.filterd (NASANPPMTA01.qualcomm.com [127.0.0.1]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AM77DSn031708; Wed, 22 Nov 2023 07:11:00 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA01.qualcomm.com (PPS) with ESMTP id 3ughrm95w8-1; Wed, 22 Nov 2023 07:11:00 +0000 Received: from NASANPPMTA01.qualcomm.com (NASANPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AM78owC002034; Wed, 22 Nov 2023 07:11:00 GMT Received: from stor-dylan.qualcomm.com (stor-dylan.qualcomm.com [192.168.140.207]) by NASANPPMTA01.qualcomm.com (PPS) with ESMTP id 3AM7B0uI007401; Wed, 22 Nov 2023 07:11:00 +0000 Received: by stor-dylan.qualcomm.com (Postfix, from userid 359480) id 4597320A65; Tue, 21 Nov 2023 23:11:00 -0800 (PST) From: Can Guo To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com Cc: Alim Akhtar , "James E.J. Bottomley" , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Matthias Brugger , AngeloGioacchino Del Regno , Keoseong Park , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Brian Masney , Andrew Halaney , linux-scsi@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-kernel@vger.kernel.org (open list), linux-mediatek@lists.infradead.org (moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-arm-msm@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...) Subject: [PATCH v3 01/11] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params Date: Tue, 21 Nov 2023 23:10:32 -0800 Message-Id: <1700637042-11104-2-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: mzi5evwiVGEvnFLWlvcfetX9KFf9aUrM X-Proofpoint-ORIG-GUID: mzi5evwiVGEvnFLWlvcfetX9KFf9aUrM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_04,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 mlxscore=0 bulkscore=0 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220050 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:12:01 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247286473130713 X-GMAIL-MSGID: 1783247286473130713 Structure ufs_dev_params is actually used in UFS host vendor drivers to declare host specific power mode parameters, like ufs__params or host_cap, which makes the code not very straightforward to read. Rename the structure ufs_dev_params to ufs_host_params and unify the declarations in all vendor drivers to host_params. In addition, rename the two functions ufshcd_init_pwr_dev_param() and ufshcd_get_pwr_dev_param() which work based on the ufs_host_params to ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to avoid confusions. This change does not change any functionalities or logic. Acked-by: Andrew Halaney Signed-off-by: Can Guo --- drivers/ufs/host/ufs-exynos.c | 7 ++-- drivers/ufs/host/ufs-hisi.c | 11 +++---- drivers/ufs/host/ufs-mediatek.c | 12 +++---- drivers/ufs/host/ufs-qcom.c | 12 +++---- drivers/ufs/host/ufshcd-pltfrm.c | 69 ++++++++++++++++++++-------------------- drivers/ufs/host/ufshcd-pltfrm.h | 10 +++--- 6 files changed, 57 insertions(+), 64 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 71bd6db..674f2f4 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -765,7 +765,7 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, { struct exynos_ufs *ufs = ufshcd_get_variant(hba); struct phy *generic_phy = ufs->phy; - struct ufs_dev_params ufs_exynos_cap; + struct ufs_host_params host_params; int ret; if (!dev_req_params) { @@ -774,10 +774,9 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, goto out; } - ufshcd_init_pwr_dev_param(&ufs_exynos_cap); + ufshcd_init_host_param(&host_params); - ret = ufshcd_get_pwr_dev_param(&ufs_exynos_cap, - dev_max_params, dev_req_params); + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params); if (ret) { pr_err("%s: failed to determine capabilities\n", __func__); goto out; diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c index 0229ac0..bb0c9a7 100644 --- a/drivers/ufs/host/ufs-hisi.c +++ b/drivers/ufs/host/ufs-hisi.c @@ -293,9 +293,9 @@ static int ufs_hisi_link_startup_notify(struct ufs_hba *hba, return err; } -static void ufs_hisi_set_dev_cap(struct ufs_dev_params *hisi_param) +static void ufs_hisi_set_dev_cap(struct ufs_host_params *host_params) { - ufshcd_init_pwr_dev_param(hisi_param); + ufshcd_init_host_param(host_params); } static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba) @@ -365,7 +365,7 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba, struct ufs_pa_layer_attr *dev_max_params, struct ufs_pa_layer_attr *dev_req_params) { - struct ufs_dev_params ufs_hisi_cap; + struct ufs_host_params host_params; int ret = 0; if (!dev_req_params) { @@ -377,9 +377,8 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba, switch (status) { case PRE_CHANGE: - ufs_hisi_set_dev_cap(&ufs_hisi_cap); - ret = ufshcd_get_pwr_dev_param(&ufs_hisi_cap, - dev_max_params, dev_req_params); + ufs_hisi_set_dev_cap(&host_params); + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params); if (ret) { dev_err(hba->dev, "%s: failed to determine capabilities\n", __func__); diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index fc61790..016067d 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -996,16 +996,14 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba, struct ufs_pa_layer_attr *dev_req_params) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); - struct ufs_dev_params host_cap; + struct ufs_host_params host_params; int ret; - ufshcd_init_pwr_dev_param(&host_cap); - host_cap.hs_rx_gear = UFS_HS_G5; - host_cap.hs_tx_gear = UFS_HS_G5; + ufshcd_init_host_param(&host_params); + host_params.hs_rx_gear = UFS_HS_G5; + host_params.hs_tx_gear = UFS_HS_G5; - ret = ufshcd_get_pwr_dev_param(&host_cap, - dev_max_params, - dev_req_params); + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params); if (ret) { pr_info("%s: failed to determine capabilities\n", __func__); diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 96cb8b5..aee66a3 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, struct ufs_pa_layer_attr *dev_req_params) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct ufs_dev_params ufs_qcom_cap; + struct ufs_host_params host_params; int ret = 0; if (!dev_req_params) { @@ -908,15 +908,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, switch (status) { case PRE_CHANGE: - ufshcd_init_pwr_dev_param(&ufs_qcom_cap); - ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE; + ufshcd_init_host_param(&host_params); + host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE; /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ - ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba); + host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba); - ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap, - dev_max_params, - dev_req_params); + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params); if (ret) { dev_err(hba->dev, "%s: failed to determine capabilities\n", __func__); diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c index da2558e..9ec11b9 100644 --- a/drivers/ufs/host/ufshcd-pltfrm.c +++ b/drivers/ufs/host/ufshcd-pltfrm.c @@ -285,61 +285,60 @@ static int ufshcd_parse_operating_points(struct ufs_hba *hba) } /** - * ufshcd_get_pwr_dev_param - get finally agreed attributes for - * power mode change - * @pltfrm_param: pointer to platform parameters + * ufshcd_negotiate_pwr_param - find power mode settings that are supported by + both the controller and the device + * @host_param: pointer to host parameters * @dev_max: pointer to device attributes * @agreed_pwr: returned agreed attributes * * Return: 0 on success, non-zero value on failure. */ -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param, - const struct ufs_pa_layer_attr *dev_max, - struct ufs_pa_layer_attr *agreed_pwr) +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param, + const struct ufs_pa_layer_attr *dev_max, + struct ufs_pa_layer_attr *agreed_pwr) { - int min_pltfrm_gear; + int min_host_gear; int min_dev_gear; bool is_dev_sup_hs = false; - bool is_pltfrm_max_hs = false; + bool is_host_max_hs = false; if (dev_max->pwr_rx == FAST_MODE) is_dev_sup_hs = true; - if (pltfrm_param->desired_working_mode == UFS_HS_MODE) { - is_pltfrm_max_hs = true; - min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear, - pltfrm_param->hs_tx_gear); + if (host_param->desired_working_mode == UFS_HS_MODE) { + is_host_max_hs = true; + min_host_gear = min_t(u32, host_param->hs_rx_gear, + host_param->hs_tx_gear); } else { - min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear, - pltfrm_param->pwm_tx_gear); + min_host_gear = min_t(u32, host_param->pwm_rx_gear, + host_param->pwm_tx_gear); } /* - * device doesn't support HS but - * pltfrm_param->desired_working_mode is HS, - * thus device and pltfrm_param don't agree + * device doesn't support HS but host_param->desired_working_mode is HS, + * thus device and host_param don't agree */ - if (!is_dev_sup_hs && is_pltfrm_max_hs) { + if (!is_dev_sup_hs && is_host_max_hs) { pr_info("%s: device doesn't support HS\n", __func__); return -ENOTSUPP; - } else if (is_dev_sup_hs && is_pltfrm_max_hs) { + } else if (is_dev_sup_hs && is_host_max_hs) { /* * since device supports HS, it supports FAST_MODE. - * since pltfrm_param->desired_working_mode is also HS + * since host_param->desired_working_mode is also HS * then final decision (FAST/FASTAUTO) is done according * to pltfrm_params as it is the restricting factor */ - agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs; + agreed_pwr->pwr_rx = host_param->rx_pwr_hs; agreed_pwr->pwr_tx = agreed_pwr->pwr_rx; } else { /* - * here pltfrm_param->desired_working_mode is PWM. + * here host_param->desired_working_mode is PWM. * it doesn't matter whether device supports HS or PWM, - * in both cases pltfrm_param->desired_working_mode will + * in both cases host_param->desired_working_mode will * determine the mode */ - agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm; + agreed_pwr->pwr_rx = host_param->rx_pwr_pwm; agreed_pwr->pwr_tx = agreed_pwr->pwr_rx; } @@ -349,9 +348,9 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param, * the same decision will be made for rx */ agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx, - pltfrm_param->tx_lanes); + host_param->tx_lanes); agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx, - pltfrm_param->rx_lanes); + host_param->rx_lanes); /* device maximum gear is the minimum between device rx and tx gears */ min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx); @@ -364,26 +363,26 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param, * what is the gear, as it is the one that also decided previously what * pwr the device will be configured to. */ - if ((is_dev_sup_hs && is_pltfrm_max_hs) || - (!is_dev_sup_hs && !is_pltfrm_max_hs)) { + if ((is_dev_sup_hs && is_host_max_hs) || + (!is_dev_sup_hs && !is_host_max_hs)) { agreed_pwr->gear_rx = - min_t(u32, min_dev_gear, min_pltfrm_gear); + min_t(u32, min_dev_gear, min_host_gear); } else if (!is_dev_sup_hs) { agreed_pwr->gear_rx = min_dev_gear; } else { - agreed_pwr->gear_rx = min_pltfrm_gear; + agreed_pwr->gear_rx = min_host_gear; } agreed_pwr->gear_tx = agreed_pwr->gear_rx; - agreed_pwr->hs_rate = pltfrm_param->hs_rate; + agreed_pwr->hs_rate = host_param->hs_rate; return 0; } -EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param); +EXPORT_SYMBOL_GPL(ufshcd_negotiate_pwr_param); -void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param) +void ufshcd_init_host_param(struct ufs_host_params *host_param) { - *dev_param = (struct ufs_dev_params){ + *host_param = (struct ufs_host_params){ .tx_lanes = UFS_LANE_2, .rx_lanes = UFS_LANE_2, .hs_rx_gear = UFS_HS_G3, @@ -398,7 +397,7 @@ void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param) .desired_working_mode = UFS_HS_MODE, }; } -EXPORT_SYMBOL_GPL(ufshcd_init_pwr_dev_param); +EXPORT_SYMBOL_GPL(ufshcd_init_host_param); /** * ufshcd_pltfrm_init - probe routine of the driver diff --git a/drivers/ufs/host/ufshcd-pltfrm.h b/drivers/ufs/host/ufshcd-pltfrm.h index a86a3ad..2d4d047 100644 --- a/drivers/ufs/host/ufshcd-pltfrm.h +++ b/drivers/ufs/host/ufshcd-pltfrm.h @@ -10,7 +10,7 @@ #define UFS_PWM_MODE 1 #define UFS_HS_MODE 2 -struct ufs_dev_params { +struct ufs_host_params { u32 pwm_rx_gear; /* pwm rx gear to work in */ u32 pwm_tx_gear; /* pwm tx gear to work in */ u32 hs_rx_gear; /* hs rx gear to work in */ @@ -25,10 +25,10 @@ struct ufs_dev_params { u32 desired_working_mode; }; -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *dev_param, - const struct ufs_pa_layer_attr *dev_max, - struct ufs_pa_layer_attr *agreed_pwr); -void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param); +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param, + const struct ufs_pa_layer_attr *dev_max, + struct ufs_pa_layer_attr *agreed_pwr); +void ufshcd_init_host_param(struct ufs_host_params *host_param); int ufshcd_pltfrm_init(struct platform_device *pdev, const struct ufs_hba_variant_ops *vops); int ufshcd_populate_vreg(struct device *dev, const char *name, From patchwork Wed Nov 22 07:10:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 168126 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1146042vqb; Tue, 21 Nov 2023 23:13:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IH7KTRWAltq3R45WTsXmGS6JsGQYQZBeoxqtq7ggVOlk1ERuIfim2QhKv0kAhYxj/f9yNac X-Received: by 2002:a9d:67c1:0:b0:6d7:e216:35bd with SMTP id c1-20020a9d67c1000000b006d7e21635bdmr1846606otn.11.1700637204075; Tue, 21 Nov 2023 23:13:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700637204; cv=none; d=google.com; s=arc-20160816; b=phA18NHLGD9b2iCJ3CLiRMnfCC8ae9F/ThZ+BLFM3UGlFR4UPKj83krV5WDI/IYcnj nYZt7pgvjS0fO7+XJDW6TKmfNlMXAoj/tPbwS1rXpEWqfZ0bJpPwewnH+GvnwfV+9NA9 c7TxtM102gE659xG1lihA7REgsCUSQ7tmJC6yexB3cHwYa/B6JaHtj5LIxNjxQb6QVj2 nbacHCPMeb+vp5jZZ6yqiAN0YDzRI1+eL3M0Bm9DDwgTgzmddMthpxxgeDvVa7uMXXV4 b8dkxuFuaCDQZu3yO5PPJUS/Ql+90EU/Er/OcpExG9jvwmZfUtjqGr8ST86NB/klc+QR ivHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=mP3Zh3ghe1QobYCFwkdhcpkOdhL0iT2Q9aPGVoVes/U=; fh=fyPT5phGKeBfoOC/BOPzKJl/xgSxxu2I+EcBl6g/Bns=; b=Q/O77bJmgSzptIqbbPSZKhWlKz0VVq4d5JTkROzHbVJX2Av5qqnIEcadxIy5ubbZDk P3SFIbz2k0EEzRw9ObOniLeU2SJr+0oOc3fWxqinut0sS0wMjOfTj12Iqtzyv4XTGwEt kizN+lFITG3S25zZEie1REa7PO1TQ5wgJT3zRlaADywTx7mqqlcdLGbBqKsmPifqrviV MwXLhhLV+VYsSu6sehvO+3ix1vPIKvs4T3HDxrCw0blDZLyEeSwjkOAOhriDNUPj5U7C 995cxeEIVMjp3tKoMupFG9mPb3v0wqELfD+Qgp28vO3VimQk0wWwQJG1OZAattiDou+F xWmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=GfdqENGF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id h20-20020a63c014000000b005c1e7583b8csi12285942pgg.96.2023.11.21.23.13.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 23:13:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=GfdqENGF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 81127819FC62; Tue, 21 Nov 2023 23:11:53 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234943AbjKVHLr (ORCPT + 99 others); Wed, 22 Nov 2023 02:11:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230079AbjKVHLk (ORCPT ); Wed, 22 Nov 2023 02:11:40 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24CA4A1; Tue, 21 Nov 2023 23:11:36 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AM5n30l021040; Wed, 22 Nov 2023 07:11:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=mP3Zh3ghe1QobYCFwkdhcpkOdhL0iT2Q9aPGVoVes/U=; b=GfdqENGF/++ld/M9Gy502zOtgS61nuXBlyPOowHGhhyHJI4iNdO4ySw/TuN2MGGTzbrl BZ6+5SRZAZYkpYlT6pNXLKU9zWlC04Q1pnStfs7cBiYuVyzSmF/RBZjOPnVnJXqogUAp dSQOIUtSxI7FuP9PX2awZGOZQCEQC/h0b73TNgSpDG8hj3xgRS3tGWBLlRAl2yx9EMcl loYbzmGZMg2EK4uYlgjjwwFW4Y659nvXxwddBplxb9W9CCtWelCrKvBj8Re9Oa2bkeOV xUE46CZEimLWa0/squ8isjPuZvPiA8m7OqTsytkQPUYPs/Nl7Wxub42AyISp5gDkrS1Y rw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugr85uagx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 07:11:03 +0000 Received: from pps.filterd (NASANPPMTA02.qualcomm.com [127.0.0.1]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AM77Vp8004501; Wed, 22 Nov 2023 07:11:01 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA02.qualcomm.com (PPS) with ESMTP id 3uepbmy81m-1; Wed, 22 Nov 2023 07:11:01 +0000 Received: from NASANPPMTA02.qualcomm.com (NASANPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AM7AKdX008797; Wed, 22 Nov 2023 07:11:01 GMT Received: from stor-dylan.qualcomm.com (stor-dylan.qualcomm.com [192.168.140.207]) by NASANPPMTA02.qualcomm.com (PPS) with ESMTP id 3AM7B1lk011118; Wed, 22 Nov 2023 07:11:01 +0000 Received: by stor-dylan.qualcomm.com (Postfix, from userid 359480) id 2334420A65; Tue, 21 Nov 2023 23:11:01 -0800 (PST) From: Can Guo To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , "James E.J. Bottomley" , linux-arm-msm@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-scsi@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 02/11] scsi: ufs: ufs-qcom: No need to set hs_rate after ufshcd_init_host_param() Date: Tue, 21 Nov 2023 23:10:33 -0800 Message-Id: <1700637042-11104-3-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rYFiWK0aYSPSxGgKwapL5SNeKC--5urQ X-Proofpoint-ORIG-GUID: rYFiWK0aYSPSxGgKwapL5SNeKC--5urQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_04,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220050 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:11:53 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247356839774901 X-GMAIL-MSGID: 1783247356839774901 In ufs_qcom_pwr_change_notify(), host_params.hs_rate has been set to PA_HS_MODE_B by ufshcd_init_host_param(), hence remove the duplicated line of work. Meanwhile, removed the macro UFS_QCOM_LIMIT_HS_RATE as it is only used here. Signed-off-by: Can Guo --- drivers/ufs/host/ufs-qcom.c | 1 - drivers/ufs/host/ufs-qcom.h | 2 -- 2 files changed, 3 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index aee66a3..cc30ad9 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -909,7 +909,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, switch (status) { case PRE_CHANGE: ufshcd_init_host_param(&host_params); - host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE; /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba); diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 9950a00..82cd143 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -27,8 +27,6 @@ #define SLOW 1 #define FAST 2 -#define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B - /* QCOM UFS host controller vendor specific registers */ enum { REG_UFS_SYS1CLK_1US = 0xC0, From patchwork Wed Nov 22 07:10:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 168120 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1145385vqb; Tue, 21 Nov 2023 23:11:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IGIt1Tinvq4ArdgKWmMtFo7oYESM6M/MDoqR9GQ1YCsYKk4kUPjX0ZXAmCZ2eVpw8CKkEVl X-Received: by 2002:a05:6a20:7349:b0:181:6f91:efe with SMTP id v9-20020a056a20734900b001816f910efemr1387478pzc.19.1700637104017; Tue, 21 Nov 2023 23:11:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700637104; cv=none; d=google.com; s=arc-20160816; b=IjYFRBevRLnquY6XRm1ecUMOVwjqCbtrqEoRU0vbSD8Fcxlo5USI9jviZSKTqhu2P0 onJ9KemlR62OS9WoIBrwRZ4vJBqcqWWJKqwBZrBtHuuugaHs+OnPRKZ3lNEYIR6lBklf 7e4ZjnYYBHK+tTu5/uNTm+dMdvj0C3cGDyfwbppdeHuKoiFict8s49Cv4XI4PWcyYkLl ePwqxhIfITh5FBgkyQZHapWAoIPAX4r1WaR3ifwrbd6tgyk8QIsTF5DUk2bQaslOjp9Y rIEfQtHuFpXLWlQFM1a4MIAAu1MBtzxLxZjVPo9Rw9EabVg8sqkJKuHS1hVX839GSJfx JDiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Bo886srp5MIVH1wCxiVYC/PHqeZIjQZkwCjvvESOKhI=; fh=VJn8EvDNRqY66dcuESX+dJKNMGWQYVtVCKlSrOaAsF8=; b=TS9nBiMxNGU7wdkluj0ldIUQ1KZlhbpz2v3lvq3az6yDT76VuXLMo/PqQjTlZ2pLxj 4eYA3XkkXCU/B76EjWve8MqPoUGBEOqsdu6YVo8+KKklTm1CFofJYnqjtrzBXjlxEatJ 6HSXlXqQejjTalNSbtAm6YtXJPRfxkRxT5+8DdOh4LJ0Li6mmBC078oYequiYbSyY2Vw toVJYPdMEq41sfeHEhE7sJa9g9WUsN/dvHg0xfQiAchABB/v/yoDjEqVCVf4aSbeuy28 xlDMnHIS9gl/8bP/wvGp/a1ZbK8WZXCq1uRMvVtWGR2zB7U664+k5d0Oge+cgiaGNqHr r0rQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=m1o0SJtb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id ls8-20020a17090b350800b0028516fe2bffsi901091pjb.186.2023.11.21.23.11.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 23:11:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=m1o0SJtb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 6891581972FB; Tue, 21 Nov 2023 23:11:38 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234924AbjKVHLi (ORCPT + 99 others); Wed, 22 Nov 2023 02:11:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229991AbjKVHLb (ORCPT ); Wed, 22 Nov 2023 02:11:31 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0314F1AA; Tue, 21 Nov 2023 23:11:27 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AM4u8vM016527; Wed, 22 Nov 2023 07:11:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=Bo886srp5MIVH1wCxiVYC/PHqeZIjQZkwCjvvESOKhI=; b=m1o0SJtbfSaBIfymAP+XBDcS/KH+4/ejPr6oz1vy2plynrVNBweN9UguKSbRvP9YoBhX mJw+iKS8XSESKHh4IfpvH+mLmF4kbwDn36tRl7iI4vzbyW9vSWtSdxHcxQt3hqQmnOtv BqAc2VFIBgHPPalOM1j+IXk4iibT5cGGtqNZ5SVodjDahhxjV0V/jtXMWMibSsANBm2D i4PuX4DGLu2rcIcgeyHlPPPK0JX7Ce3U/ztHBOTawruTnbRqOjyp6+nfEPlUC4RBcTYK xiw7fjjyavcC7kibG1QbmM0t0cXkqMRkr9GzhqDmSyzml2OrfNhc9e4uS9B99bZpOB4X GA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugr85uah1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 07:11:05 +0000 Received: from pps.filterd (NASANPPMTA05.qualcomm.com [127.0.0.1]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AM71nw6012999; Wed, 22 Nov 2023 07:11:04 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA05.qualcomm.com (PPS) with ESMTP id 3uhcusg3y4-1; Wed, 22 Nov 2023 07:11:04 +0000 Received: from NASANPPMTA05.qualcomm.com (NASANPPMTA05.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AM75bsG019002; Wed, 22 Nov 2023 07:11:03 GMT Received: from stor-dylan.qualcomm.com (stor-dylan.qualcomm.com [192.168.140.207]) by NASANPPMTA05.qualcomm.com (PPS) with ESMTP id 3AM7B3va027624; Wed, 22 Nov 2023 07:11:03 +0000 Received: by stor-dylan.qualcomm.com (Postfix, from userid 359480) id 06F0820A65; Tue, 21 Nov 2023 23:11:01 -0800 (PST) From: Can Guo To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com Cc: "Bao D . Nguyen" , Andy Gross , Bjorn Andersson , Konrad Dybcio , "James E.J. Bottomley" , linux-arm-msm@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-scsi@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 03/11] scsi: ufs: ufs-qcom: Setup host power mode during init Date: Tue, 21 Nov 2023 23:10:34 -0800 Message-Id: <1700637042-11104-4-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rXay6qRCkP64GWd54eDRqsgUstZIJzLb X-Proofpoint-ORIG-GUID: rXay6qRCkP64GWd54eDRqsgUstZIJzLb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_04,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220050 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:11:38 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247251965139022 X-GMAIL-MSGID: 1783247251965139022 Setup host power mode and its limitations during UFS host driver init to avoid repetitive work during every power mode change. Acked-by: Andrew Halaney Co-developed-by: Bao D. Nguyen Signed-off-by: Bao D. Nguyen Signed-off-by: Can Guo --- drivers/ufs/host/ufs-qcom.c | 21 ++++++++++++++------- drivers/ufs/host/ufs-qcom.h | 1 + 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index cc30ad9..cc0eb37 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, struct ufs_pa_layer_attr *dev_req_params) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct ufs_host_params host_params; + struct ufs_host_params *host_params = &host->host_params; int ret = 0; if (!dev_req_params) { @@ -908,12 +908,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, switch (status) { case PRE_CHANGE: - ufshcd_init_host_param(&host_params); - - /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ - host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba); - - ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params); + ret = ufshcd_negotiate_pwr_param(host_params, dev_max_params, dev_req_params); if (ret) { dev_err(hba->dev, "%s: failed to determine capabilities\n", __func__); @@ -1048,6 +1043,17 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; } +static void ufs_qcom_set_host_params(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct ufs_host_params *host_params = &host->host_params; + + ufshcd_init_host_param(host_params); + + /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ + host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba); +} + static void ufs_qcom_set_caps(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); @@ -1272,6 +1278,7 @@ static int ufs_qcom_init(struct ufs_hba *hba) ufs_qcom_set_caps(hba); ufs_qcom_advertise_quirks(hba); + ufs_qcom_set_host_params(hba); err = ufs_qcom_ice_init(host); if (err) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 82cd143..11419eb 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -238,6 +238,7 @@ struct ufs_qcom_host { struct gpio_desc *device_reset; + struct ufs_host_params host_params; u32 phy_gear; bool esi_enabled; From patchwork Wed Nov 22 07:10:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 168130 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1147616vqb; Tue, 21 Nov 2023 23:17:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IFcwp7NbXezZD/2anXJqNH1S5ric2MgdnQXx5f3SiJD3s/NblAsnt3VRgAb79DZj95ncH4B X-Received: by 2002:a05:6830:18f:b0:6c1:7927:6550 with SMTP id q15-20020a056830018f00b006c179276550mr1703662ota.2.1700637441649; Tue, 21 Nov 2023 23:17:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700637441; cv=none; d=google.com; s=arc-20160816; b=0dm0fq6xbpQ/V0drDjZN1sGJxawTc/CJ7/A5fvRmJ4zNHl9QWMz/FTXQdjYc1lvpXv G4HHSp3OF77R/dy2Yqo0kjLPsbYePh/s9MxaYaJwxDhO5cka4c8h12EkCA8wor3lgGvC +1lmQ6uZL4CXfd3O1MMEA0qvF57AIaHtTbGmbVLlXAh6sj7YQTCnNKcpiQzMpWvAbGdn 4ANt3sjk1TyJKkzpt+b1wOllmlaTvqys1f/pWFEewU0s4iGf1dgm8KZil/9fUfM88WAO vKkiq0odrFYIFkItZXHphbiOHy1KSdSK9oV6I2hoDGxZRB49UR+dQj7/Ns+woUyTKn3i 0Qxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=zN12TslWlABlp9K+YRCFNUDSGb7EOJnrGrpMh/GCmsY=; fh=mJ3TwjsM0jR8M6BCUfh0Zwa24JwaSdFjkXPrcnC2hcc=; b=LBprp54D+mTlgA/GSZS8BkQGoY5wDHNSjPLnFXxAK1v0b8iBn2BIX/62PygR1X+kt9 l2imwLzzEBHdq1jrRcbKvSKfeeNsFpICHnZEmN5YoKdi+bzQMAkelGO2wgDB5W3fCDzC QtA99mL8t58SPtnB8SO2CE7taiLawvuoHWhco1cZhXFL/8E4tGu5+Lix5/qpNMd02o4i qluhDzUjIjLbqm29HxDeSPAQdyU3ZRpceTeRqOHnV9GVijwbIC9DVzHnyffeODOYtoZp iKS05ve5q1jx1T7MNKNRFtOeEdiI5oDtYTWpTZFng5C89PEpcyj3sTbirjR/+z3T/WgV xLoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Fd1LRf9l; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from agentk.vger.email (agentk.vger.email. [23.128.96.32]) by mx.google.com with ESMTPS id q36-20020a631f64000000b0059f0cebd04csi11633314pgm.722.2023.11.21.23.17.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 23:17:21 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Fd1LRf9l; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 92174804C49F; Tue, 21 Nov 2023 23:16:16 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233968AbjKVHQQ (ORCPT + 99 others); Wed, 22 Nov 2023 02:16:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230042AbjKVHQP (ORCPT ); Wed, 22 Nov 2023 02:16:15 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58D8790; Tue, 21 Nov 2023 23:16:11 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AM5k8nD026875; Wed, 22 Nov 2023 07:11:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=zN12TslWlABlp9K+YRCFNUDSGb7EOJnrGrpMh/GCmsY=; b=Fd1LRf9lkkBjS/sazsPqq3FEigQ6QD2Rvzn/WMBrDXa8ZiTM9rKzCRtlpwiKKWfwDCvn Rzr7RS/rxqKDUjPjvwi4SdAv/G+msNQW7lTw26uMT6xaZETVZrLDgF1kaUBYvaeBafGO 3nHK/B3n6jAWfR+egOBFZK6GfVtsZGWbBMFvBaE0gXXYLK/xuC22jcJhT1OWOsDZGF3x lN05shZNCkqL0fal1xBAI/kjcUe8qhA9M413EDMjRO0Wuah33Xu5f2U86S27lAutYVgI DopEIOK9pJa9LYu46D9TPhXXpD7I4cP6cpopn7z2o9tW/vh4+4BB0bRWQ8EcgBlidXNy YQ== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uhbsp86pt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 07:11:05 +0000 Received: from pps.filterd (NASANPPMTA04.qualcomm.com [127.0.0.1]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AM72Y14020842; Wed, 22 Nov 2023 07:11:03 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA04.qualcomm.com (PPS) with ESMTP id 3uepbmyg7y-1; Wed, 22 Nov 2023 07:11:03 +0000 Received: from NASANPPMTA04.qualcomm.com (NASANPPMTA04.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AM7B3fE002480; Wed, 22 Nov 2023 07:11:03 GMT Received: from stor-dylan.qualcomm.com (stor-dylan.qualcomm.com [192.168.140.207]) by NASANPPMTA04.qualcomm.com (PPS) with ESMTP id 3AM7B34G002475; Wed, 22 Nov 2023 07:11:03 +0000 Received: by stor-dylan.qualcomm.com (Postfix, from userid 359480) id B408720A68; Tue, 21 Nov 2023 23:11:02 -0800 (PST) From: Can Guo To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , "James E.J. Bottomley" , linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT), linux-scsi@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 04/11] scsi: ufs: ufs-qcom: Limit negotiated gear to selected PHY gear Date: Tue, 21 Nov 2023 23:10:35 -0800 Message-Id: <1700637042-11104-5-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: PVg95SGpqZAOrBj-K17GVeoupE8iGtK- X-Proofpoint-GUID: PVg95SGpqZAOrBj-K17GVeoupE8iGtK- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_04,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 phishscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220050 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:16:16 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247606139021800 X-GMAIL-MSGID: 1783247606139021800 In the dual init scenario, the initial PHY gear is set to HS-G2, and the first Power Mode Change (PMC) is meant to find the best matching PHY gear for the 2nd init. However, for the first PMC, if the negotiated gear (say HS-G4) is higher than the initial PHY gear, we cannot go ahead let PMC to the negotiated gear happen, because the programmed UFS PHY settings may not support the negotiated gear. Fix it by overwriting the negotiated gear with the PHY gear. Signed-off-by: Can Guo --- drivers/ufs/host/ufs-qcom.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index cc0eb37..d4edf58 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -920,8 +920,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, * because, the PHY gear settings are backwards compatible and we only need to * change the PHY gear settings while scaling to higher gears. */ - if (dev_req_params->gear_tx > host->phy_gear) + if (dev_req_params->gear_tx > host->phy_gear) { + u32 old_phy_gear = host->phy_gear; + host->phy_gear = dev_req_params->gear_tx; + dev_req_params->gear_tx = old_phy_gear; + dev_req_params->gear_rx = old_phy_gear; + } /* enable the device ref clock before changing to HS mode */ if (!ufshcd_is_hs_mode(&hba->pwr_info) && From patchwork Wed Nov 22 07:10:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 168127 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1146095vqb; Tue, 21 Nov 2023 23:13:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IFIG/CM7pcN7vX1fNtktijxoq8umzg9IAvd8+KByaarhLqMi6+xgRox6V1tRKN/5DODTuf8 X-Received: by 2002:a05:6808:13c1:b0:3af:cc96:cb6d with SMTP id d1-20020a05680813c100b003afcc96cb6dmr2164630oiw.46.1700637209527; Tue, 21 Nov 2023 23:13:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700637209; cv=none; d=google.com; s=arc-20160816; b=VPXTVRLlPXEsNCv1t7W/JSPIF60qYZlTySZaM9YEcEvJhwgQbVZBwA+UZum474ODOm aHCG8ON1FQEkHRtTSlwaYCibieXW9N1D82mR5QxuXLsCBB/u/wPgTxWcnEzYxEEjXbxE Y/6le1YSHQ2pEqGfQNVV2EKkMBEqaFwLnT+ixSMUJWDB1NPMZP0u0Uh4m7Mo463lM9xl d7LvI5iq9mq7b8rf4JHtKPjXtS5wS3htbJe8kWsggnpMhwgu78peTjgNRHgG/FopaI/v Al1/yFUmJRjxH4vJJOIf6RqYb6fpcgw3e4xDF/dsnRRo9q5GIrO8p7b58WCy1+okEzuO QGKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=ZhwV3737hVFopoyIktTqMRJOFfXUF17oXq/72ZAucXQ=; fh=mJ3TwjsM0jR8M6BCUfh0Zwa24JwaSdFjkXPrcnC2hcc=; b=GL0i/0/FAMe514fF4D5byoaiW7bW//HAXzvcJsstodF4jhvGP973avTdiwNW/chHjP UQkQcbLIYvnpHE/Eaw7r5CKyA2tRWCLcZem4Re2xaNSbi7Gyr0cBwYRepg8R0G4Nx5Ac TINvHmaFLSsn9qB4nahLFsB/K2mwUEStvalvJWDqviQlhw8xNsovlnu8LOt28OTU53L/ 6NBy0RrS49PpmBa1RC8VlIKxZbRLm3zG5EIj/GythPqPcUsdM3CEbR2xk7fjd5FOIMHF B5oa+8FDH8acVDr48qswyHqBC+6nYBMdq0SJ+XtyM2UHI41ymIIJdIiLGSnRzXIs81RJ nKpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=BSnA2uFA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id bz16-20020a056a02061000b005bdd8af5a1csi13934975pgb.499.2023.11.21.23.13.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 23:13:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=BSnA2uFA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 4EB63819FC7A; Tue, 21 Nov 2023 23:12:19 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235003AbjKVHL5 (ORCPT + 99 others); Wed, 22 Nov 2023 02:11:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234881AbjKVHLl (ORCPT ); Wed, 22 Nov 2023 02:11:41 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83E0290; Tue, 21 Nov 2023 23:11:37 -0800 (PST) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AM63WSg022671; Wed, 22 Nov 2023 07:11:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=ZhwV3737hVFopoyIktTqMRJOFfXUF17oXq/72ZAucXQ=; b=BSnA2uFAGCZQmjWiIBtJkobRMAuEEc1HPB5ajG4iQ0ygwvbqUuUwYfu5Bbdk9pkkRsUu AYjpEOmPqfj4qNFzPuwfjWFHb9l657yGHO6Uf3Dj8tJ+dqua7wrnMlC9rKb2H87RK2es sm3pOLTf4IwuWdh1t38gdCX63uOs530wVQF92Te4uyO8eeUkPBd24t7NlqGv7AthtTrc CxCkH1R4+cC4fu/7bmhIR4dx6v6MTxqH3pw4i/Wt4rbwev5szDCXGOEjRgOppfFVt54H tB4XKR09aR22WwsJV0bzBOal4xIbPTFuyz8Y1k1C1c0EfThl+hjpj5u2i7bzKvy5E5lZ DA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugu54avph-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 07:11:05 +0000 Received: from pps.filterd (NASANPPMTA01.qualcomm.com [127.0.0.1]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AM6rxPd011128; Wed, 22 Nov 2023 07:11:04 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA01.qualcomm.com (PPS) with ESMTP id 3ughrm95xc-1; Wed, 22 Nov 2023 07:11:04 +0000 Received: from NASANPPMTA01.qualcomm.com (NASANPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AM78owE002034; Wed, 22 Nov 2023 07:11:04 GMT Received: from stor-dylan.qualcomm.com (stor-dylan.qualcomm.com [192.168.140.207]) by NASANPPMTA01.qualcomm.com (PPS) with ESMTP id 3AM7B3ed007472; Wed, 22 Nov 2023 07:11:04 +0000 Received: by stor-dylan.qualcomm.com (Postfix, from userid 359480) id 6F11E20A6B; Tue, 21 Nov 2023 23:11:03 -0800 (PST) From: Can Guo To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , "James E.J. Bottomley" , linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT), linux-scsi@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 05/11] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear Date: Tue, 21 Nov 2023 23:10:36 -0800 Message-Id: <1700637042-11104-6-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 6KsogeN2tgZJkhBkhn94DnEQTTf-vQNc X-Proofpoint-ORIG-GUID: 6KsogeN2tgZJkhBkhn94DnEQTTf-vQNc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_04,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 bulkscore=0 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220050 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:12:19 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247362473337173 X-GMAIL-MSGID: 1783247362473337173 During host driver init, the phy_gear is set to the minimum supported gear (HS_G2). Then, during the first power mode change, the negotiated gear, say HS-G4, is updated to the phy_gear variable so that in the second init the updated phy_gear can be used to program the PHY. But the current code only allows update the phy_gear to a higher value. If one wants to start the first init with the maximum support gear, say HS-G4, the phy_gear is not updated to HS-G3 if the device only supports HS-G3. The original check added there is intend to make sure the phy_gear won't be updated when gear is scaled down (during clock scaling). Update the check so that one can start the first init with the maximum support gear without breaking the original fix by checking the ufshcd_state, that is, allow update to phy_gear only if power mode change is invoked from ufshcd_probe_hba(). This change is a preparation patch for the next patches in the same series. Signed-off-by: Can Guo --- drivers/ufs/host/ufs-qcom.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index d4edf58..9613ad9 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -916,16 +916,19 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, } /* - * Update phy_gear only when the gears are scaled to a higher value. This is - * because, the PHY gear settings are backwards compatible and we only need to - * change the PHY gear settings while scaling to higher gears. + * During UFS driver probe, always update the PHY gear to match the negotiated + * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled, + * the second init can program the optimal PHY settings. This allows one to start + * the first init with either the minimum or the maximum support gear. */ - if (dev_req_params->gear_tx > host->phy_gear) { + if (hba->ufshcd_state == UFSHCD_STATE_RESET) { u32 old_phy_gear = host->phy_gear; host->phy_gear = dev_req_params->gear_tx; - dev_req_params->gear_tx = old_phy_gear; - dev_req_params->gear_rx = old_phy_gear; + if (dev_req_params->gear_tx > old_phy_gear) { + dev_req_params->gear_tx = old_phy_gear; + dev_req_params->gear_rx = old_phy_gear; + } } /* enable the device ref clock before changing to HS mode */ From patchwork Wed Nov 22 07:10:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 168129 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1147489vqb; Tue, 21 Nov 2023 23:17:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IGAH5dFcSRnuR9++pUbsGg8CaiOOFYhsZLoV9bMP+nKW4U5YcMZimz6mHk/oXiYLh/xFypZ X-Received: by 2002:a17:902:7805:b0:1c9:e68a:1b58 with SMTP id p5-20020a170902780500b001c9e68a1b58mr1223515pll.54.1700637422087; Tue, 21 Nov 2023 23:17:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700637422; cv=none; d=google.com; s=arc-20160816; b=0GNOcl0lRiC73++xFIL6Cj7VOK8k1towYO2HLMs8YjQYvLBiNG4pD3EZb0LYmAbO40 mJ9zBaiXwVj2zhJBsgaoDlUI+Cv2kAtQDf6PstBohGWr8zXI65+EB37me5b/kw7UbuWn JcP9PrgSJ2U2Bt63ulpy+G3PciOa/VUT0N/6n5MsI4YM8EOQm9JFGt02vaC0oLdGHLjA nKlXY5AHTNtVyQLCljKdVRBFiJUjmeBWOxNW3mZ581RXTAzg3WkilJgHq4AwxihtR5gA sFJRyG5vTP5d9ZyfM2xsv+NV3vtMY4XFJt2tWh+eCeoTNFro7ETDhs5LKfW3EkYnjHV8 GvaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=bOrJSSNFsLGbiSSB8YF589JZQLsAbNb5oTKc3fog6kw=; fh=fyPT5phGKeBfoOC/BOPzKJl/xgSxxu2I+EcBl6g/Bns=; b=syafN8L7wzh1LMsdOW632IRRodYcrAoOJn4XQSEL/cdYTHnw4GLRAe5IXYT/lbB1+0 V89y9Wv4lwm4P6CGg4qVmf+0utuS/S/E0ZVEGpnVCo7Ri8/W8fpx/goJ/r7RRvsVTVHD sQjjOJC2ib+eJaSJ3A2ffxTM1V++UORiLC+eYmvbF6GguE7MkxgAefCIUZLBtWjI3Eef qZeujQEwGUJyAZsOUfxMxhvuyG/RHz7kxpsKIXTpUSQjGvB7A8dck2WH87lR2Gqy6uZe s0Tj4+UV5KTaN3RV/70KxO1uVJOSg4T4cmF4SLUA9nPJOE0ZIRmvhccq2rzsxvMjelVU 8kog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=WjPDWZKN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id k15-20020a170902c40f00b001c3a06b4fd7si12704442plk.561.2023.11.21.23.17.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 23:17:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=WjPDWZKN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 446F58026684; Tue, 21 Nov 2023 23:16:59 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234924AbjKVHQY (ORCPT + 99 others); Wed, 22 Nov 2023 02:16:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234910AbjKVHQW (ORCPT ); Wed, 22 Nov 2023 02:16:22 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B100B1A8; Tue, 21 Nov 2023 23:16:18 -0800 (PST) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AM4xPue013945; Wed, 22 Nov 2023 07:11:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=bOrJSSNFsLGbiSSB8YF589JZQLsAbNb5oTKc3fog6kw=; b=WjPDWZKN/09jQNKi0ah89tf8VfXL+XzGG/wO2yVFtESpANDgG/dFj64ETThHf5OJFtRV u78Ww2WW1OF4kfnUId1lGZJB9OvuCuz6qZs4xB57bt8bKncnruRuaMLK38SIsFhfkDK6 i/4wXANO6B+IAYH5zlYX+5wrFSJ++5l6wMyT3v8shpR4niuZmJ0D//lpI+SBGFbM4Iqa seHjn7xGtz44B8olkMeSyxK0ZwQITvLzmn1DCds1EZ65gZ9MI4QV892XzB6JL6D3Iolm Q0/8uvGq4xx8RX74S7odEsqEnE1waYYJnzp/kLI82rYc5HVoA85q/Vhl89dOA+lqHUys Bw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugxn8hy5w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 07:11:07 +0000 Received: from pps.filterd (NASANPPMTA03.qualcomm.com [127.0.0.1]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AM77S71012224; Wed, 22 Nov 2023 07:11:05 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA03.qualcomm.com (PPS) with ESMTP id 3uepbmpxr0-1; Wed, 22 Nov 2023 07:11:05 +0000 Received: from NASANPPMTA03.qualcomm.com (NASANPPMTA03.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AM76Fsr010658; Wed, 22 Nov 2023 07:11:04 GMT Received: from stor-dylan.qualcomm.com (stor-dylan.qualcomm.com [192.168.140.207]) by NASANPPMTA03.qualcomm.com (PPS) with ESMTP id 3AM7B4mO019539; Wed, 22 Nov 2023 07:11:04 +0000 Received: by stor-dylan.qualcomm.com (Postfix, from userid 359480) id 2C1EE20A65; Tue, 21 Nov 2023 23:11:04 -0800 (PST) From: Can Guo To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , "James E.J. Bottomley" , linux-arm-msm@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-scsi@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 06/11] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5 Date: Tue, 21 Nov 2023 23:10:37 -0800 Message-Id: <1700637042-11104-7-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _kxPYoqIHKLwuKA_tJ5i_nnB7zFiYxyw X-Proofpoint-GUID: _kxPYoqIHKLwuKA_tJ5i_nnB7zFiYxyw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_04,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 impostorscore=0 adultscore=0 mlxlogscore=744 clxscore=1015 spamscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220050 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:16:59 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247585445351411 X-GMAIL-MSGID: 1783247585445351411 Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, so that the subsequent power mode changes shall stick to Rate-A. Signed-off-by: Can Guo --- drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 9613ad9..6756f8d 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct ufs_host_params *host_params = &host->host_params; struct phy *phy = host->generic_phy; + enum phy_mode mode; int ret; + /* + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations. + * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A, + * so that the subsequent power mode change shall stick to Rate-A. + */ + if (host->hw_ver.major == 0x5) { + if (host->phy_gear == UFS_HS_G5) + host_params->hs_rate = PA_HS_MODE_A; + else + host_params->hs_rate = PA_HS_MODE_B; + } + + mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; + /* Reset UFS Host Controller and PHY */ ret = ufs_qcom_host_reset(hba); if (ret) @@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) return ret; } - phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear); + phy_set_mode_ext(phy, mode, host->phy_gear); /* power on phy - start serdes and phy's power and clocks */ ret = phy_power_on(phy); From patchwork Wed Nov 22 07:10:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 168128 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1146110vqb; Tue, 21 Nov 2023 23:13:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IEdebJDOnMukfQtENT/0bNPpEOvIyEjxx46sbREGA/qyLImn5JbAOMb5iRNcZD+3SiiO6xO X-Received: by 2002:a05:6808:abb:b0:3a7:330d:93da with SMTP id r27-20020a0568080abb00b003a7330d93damr1779897oij.19.1700637210955; Tue, 21 Nov 2023 23:13:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700637210; cv=none; d=google.com; s=arc-20160816; b=F+Yw7Sq7oLgpb3gB88NBrs+m30nNvm5NL738X03W8t2CRNqS5rYeef8bRkcAbq3VO7 +WwzhjBk7eUIsROQsur16LvFdmzsZ5a6qAjmwF9LtLg6vIjP6+04MR2hgCFyRNBlMU2e ahtNV7Qd55+aNhrvE9QWYVGP5pgf2YNkVsxOo+Etgp1UVueMupL6R7VuY3S9ocTaZagl CLIuU7cQ28qOrXsj/++nEAI0eRcSz823F8TEw0cVpY0A4AECbnNveahYBonVdynvV75m qq1RD6dWizZmAyXt8bt4j0fj2KSj8HugbJ+YxKvATDeEuHhrTweDDuteObge8iBwDPkt SsEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=IwN62VLEShy+VSKK0jRx0klroKj4fpZ9T+/MVP2hILs=; fh=mJ3TwjsM0jR8M6BCUfh0Zwa24JwaSdFjkXPrcnC2hcc=; b=Xs4qI/PMMbwDnDvCYq0nzqk+zxNC6yQCSkX8+r9U0wVUXbJzyPXYcqiuidrddDk5mm IgpV0Exfe8SEpqKa67kpu+RDKzYEDQP9M0nbfPlhinlsPOErENM9jTxsorHsPbuPJcAQ AFbv8NNX2R/rCwxg6ALSXLJmXN20BRE8Qmbltlt0XIA0BUH6l/xZFq2S91/5ERW3SSzO g6+QTGSX2C2IqbwNh6P7sQnbr1+04T3UBcpfB0ybSUPzdlROLCdK2Fj1cLH46k4JQy8V cDjWgDwGYuaUAOcWI69pszUTtJK9lDTEGVRUJQbD4/Z7bpdE8T4L8W+r8+KJTM6o1vQ3 eSMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=YHrVGg+h; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id s4-20020a056a00194400b00690f191430csi12075084pfk.56.2023.11.21.23.13.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 23:13:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=YHrVGg+h; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 9EE0C81A1E82; Tue, 21 Nov 2023 23:12:32 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235115AbjKVHMY (ORCPT + 99 others); Wed, 22 Nov 2023 02:12:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234904AbjKVHMQ (ORCPT ); Wed, 22 Nov 2023 02:12:16 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FCA610DB; Tue, 21 Nov 2023 23:11:46 -0800 (PST) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AM6nuw5028736; Wed, 22 Nov 2023 07:11:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=IwN62VLEShy+VSKK0jRx0klroKj4fpZ9T+/MVP2hILs=; b=YHrVGg+hSW1nE5WeiOGQgCzjhE96bQJ3HehjglH51FdNm8Jy4Rk+wLyIYRtatWhHn8IT sn9TjMixX1LE5mhDb9Yajf56asOhQprnICAgDQn8/JUs7cn2zpejlNktSLGUzjBS7Ozq k4uVsyfTMcyhBZtW8MgFIat/rre8TBMFMeAbWSM8d9zaSaLQ+Nj1HNd0X8pRfS21smy2 owgK4Qa6AiEmzKpicZuLlhn/xzqhalWNkh6iS5nKIItIrbmgDA9yy6IWc7bUb7slzf5O pEBsIKa8xITQwyLfCFltukKZ6LAJQ/eZnpBUluicZI2jhJ21v4QCPOnduw1v9ie4+1Wo MQ== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uh0b49kqp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 07:11:07 +0000 Received: from pps.filterd (NASANPPMTA03.qualcomm.com [127.0.0.1]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AM77S72012224; Wed, 22 Nov 2023 07:11:05 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA03.qualcomm.com (PPS) with ESMTP id 3uepbmpxr6-1; Wed, 22 Nov 2023 07:11:05 +0000 Received: from NASANPPMTA03.qualcomm.com (NASANPPMTA03.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AM7AcTR017314; Wed, 22 Nov 2023 07:11:05 GMT Received: from stor-dylan.qualcomm.com (stor-dylan.qualcomm.com [192.168.140.207]) by NASANPPMTA03.qualcomm.com (PPS) with ESMTP id 3AM7B5si019556; Wed, 22 Nov 2023 07:11:05 +0000 Received: by stor-dylan.qualcomm.com (Postfix, from userid 359480) id DF93820A68; Tue, 21 Nov 2023 23:11:04 -0800 (PST) From: Can Guo To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , "James E.J. Bottomley" , linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT), linux-scsi@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 07/11] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer Date: Tue, 21 Nov 2023 23:10:38 -0800 Message-Id: <1700637042-11104-8-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Zi5tR-U_dm7ne0i6H3NfCD3y6lQghk6p X-Proofpoint-GUID: Zi5tR-U_dm7ne0i6H3NfCD3y6lQghk6p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_04,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 clxscore=1015 phishscore=0 spamscore=0 impostorscore=0 mlxscore=0 adultscore=0 priorityscore=1501 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220050 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:12:32 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247364143161947 X-GMAIL-MSGID: 1783247364143161947 Set the initial PHY gear to max HS gear for hosts with HW ver 5 and newer. This patch is not changing any functionalities or logic but only a preparation patch for the next patch in this series. Signed-off-by: Can Guo --- drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 6756f8d..7bbccf4 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1067,6 +1067,20 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; } +static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) +{ + struct ufs_host_params *host_params = &host->host_params; + + host->phy_gear = host_params->hs_tx_gear; + + /* + * Power up the PHY using the minimum supported gear (UFS_HS_G2). + * Switching to max gear will be performed during reinit if supported. + */ + if (host->hw_ver.major < 0x5) + host->phy_gear = UFS_HS_G2; +} + static void ufs_qcom_set_host_params(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); @@ -1303,6 +1317,7 @@ static int ufs_qcom_init(struct ufs_hba *hba) ufs_qcom_set_caps(hba); ufs_qcom_advertise_quirks(hba); ufs_qcom_set_host_params(hba); + ufs_qcom_set_phy_gear(host); err = ufs_qcom_ice_init(host); if (err) @@ -1320,12 +1335,6 @@ static int ufs_qcom_init(struct ufs_hba *hba) dev_warn(dev, "%s: failed to configure the testbus %d\n", __func__, err); - /* - * Power up the PHY using the minimum supported gear (UFS_HS_G2). - * Switching to max gear will be performed during reinit if supported. - */ - host->phy_gear = UFS_HS_G2; - return 0; out_variant_clear: From patchwork Wed Nov 22 07:10:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 168123 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1145773vqb; Tue, 21 Nov 2023 23:12:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IGZKB6ggAHZDnKUt47kZatD9Hw4u7riGYm9lYx+kItc73C0NDyXQD1JxRzTTnvMvhta6nqx X-Received: by 2002:a05:6830:13d5:b0:6d6:47e5:af6d with SMTP id e21-20020a05683013d500b006d647e5af6dmr1728269otq.13.1700637159988; Tue, 21 Nov 2023 23:12:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700637159; cv=none; d=google.com; s=arc-20160816; b=yYUf6hS9Z7uVesWqdFUtwit14B65EQB7MKLEOynh+t7ZsMGRIi9PH5X7Y4Qd4Ef2YP 93JMQoBp+arVxsOXQGON9dNY1MdHQJArCjshwmwnWVSJyjFouAPn6mt1i5soCbSvfTMj N8sNxvoZrF61Ve3Jg7G2xyaOQdxFArxKX0cmw+61fPsPPJhG7RLyv5GMiRdol4dcNIot 6bcd6gUulEyPYnIO7dOqnRhfxV6Aa86b299i2JINYS6r+jH/Ubcnk48nCDUYH2uNNbo9 iKxtwY4vTE08nF/boEP3zHZQmLtUhBcR0Di6zdm4qurUT8/v3+qWMPA9D3xLIj/Ai5JE q8vQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=rSe6hOxtLupIhXV+aZmWma0P/Ekfxk1FX64OlvhX6Mw=; fh=wymrgc1+SNcsimolyglcvb/r6HjG32KcHg7pLLGOpEo=; b=Y5+0WNCBTQb+/2CZL5eUtW0yQfbcy3FffHD9XxLB0qTwROFq2/vkv+GRF3uOcIK5zO 1b5O4REmYYtAJUMP68xYpSdUJBMcCjV21GNLZQIMYDIbzIo6uo8uahEXjP1fAVg4N635 myFoIEtLqusmLEnw9/XvTbUQK4yHVkmv5SN7aV1Wv6Ns6wLV+5psYZRemyT+We3Upkdb ikMkmS3RuZ+T7+ZHCYKbl/+E4mdmKzd9t0Pf9C1BT46yd64ovWqeMmmcoY3fCQgMqcTH QsrqhX922mx7n0pKEVBxrmcAnHzfBRtRSrjuGeWfHIBEZVxmJ79jWrIEIvVBcJQfFNMz qGtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=WgbRxRg6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id w10-20020a63d74a000000b005be03f0da78si11729368pgi.157.2023.11.21.23.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 23:12:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=WgbRxRg6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 42EFF80A4322; Tue, 21 Nov 2023 23:11:40 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234920AbjKVHLl (ORCPT + 99 others); Wed, 22 Nov 2023 02:11:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230166AbjKVHLg (ORCPT ); Wed, 22 Nov 2023 02:11:36 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36513D51; Tue, 21 Nov 2023 23:11:33 -0800 (PST) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AM5OcvI026033; Wed, 22 Nov 2023 07:11:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=rSe6hOxtLupIhXV+aZmWma0P/Ekfxk1FX64OlvhX6Mw=; b=WgbRxRg6IrznmY+WR4SpUkjSjamnojJioof4csZ599BiFuHIglXNh/aOKc9YG1RXr5sT bG7og68pJXBDG1/rAnmfarwmuXj9IY3eisRxbMOQg6LxZH4CjmdS/HGbqJ3V9kn5ZMVU NZoBpIy1sjLrWknLZHb8K8GhGUptOFddB8xDspKu9REA4o4FAOzYCtyW9d+3SZ42Jwjc KBprlFilOMIMz2SDP1cMnAW/F4w6Wu+/XCOaH2kI2yHac0ZnU92raVQ0UB7akf3wGNLO e07iWWlS+NJcNouyFECXl2kYVQCU+txbu0XSooygwLnvNGzPwov+GjI3Ngs68Xamj131 Pw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uh0b49kqs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 07:11:07 +0000 Received: from pps.filterd (NASANPPMTA03.qualcomm.com [127.0.0.1]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AM6uBWL027538; Wed, 22 Nov 2023 07:11:06 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA03.qualcomm.com (PPS) with ESMTP id 3uepbmpxrb-1; Wed, 22 Nov 2023 07:11:06 +0000 Received: from NASANPPMTA03.qualcomm.com (NASANPPMTA03.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AM78v8X013705; Wed, 22 Nov 2023 07:11:06 GMT Received: from stor-dylan.qualcomm.com (stor-dylan.qualcomm.com [192.168.140.207]) by NASANPPMTA03.qualcomm.com (PPS) with ESMTP id 3AM7B6jP019584; Wed, 22 Nov 2023 07:11:06 +0000 Received: by stor-dylan.qualcomm.com (Postfix, from userid 359480) id EC00320A65; Tue, 21 Nov 2023 23:11:05 -0800 (PST) From: Can Guo To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Johan Hovold , Abel Vesa , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT), linux-phy@lists.infradead.org (open list:GENERIC PHY FRAMEWORK), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 08/11] phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings Date: Tue, 21 Nov 2023 23:10:39 -0800 Message-Id: <1700637042-11104-9-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: f5vjPl-6tXN95lCdEg_Pbpjk9YmW8KJH X-Proofpoint-GUID: f5vjPl-6tXN95lCdEg_Pbpjk9YmW8KJH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_04,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=868 malwarescore=0 bulkscore=0 clxscore=1011 phishscore=0 spamscore=0 impostorscore=0 mlxscore=0 adultscore=0 priorityscore=1501 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220050 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:11:40 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247310780480377 X-GMAIL-MSGID: 1783247310780480377 The registers, which are being touched in current SM8550 UFS PHY settings, and the values being programmed are mainly the ones working for HS-G4 mode, meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings. However, even consider HS-G4 mode only, some of them are incorrect and some are missing. Rectify the HS-G4 PHY settings by strictly aligning with the SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings. Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support") Signed-off-by: Can Guo Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa --- .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 3 +++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 28 +++++++++++++++------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h index 15bcb4b..674f158 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h @@ -10,9 +10,12 @@ #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34 +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4 #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 3927eba..ad91f92 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -658,22 +658,26 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), }; static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c), }; static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), @@ -696,6 +700,8 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), }; struct qmp_ufs_offsets { @@ -1157,6 +1163,10 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { .pcs = sm8550_ufsphy_pcs, .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), }, + .tbls_hs_b = { + .serdes = sm8550_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, From patchwork Wed Nov 22 07:10:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 168125 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1145899vqb; Tue, 21 Nov 2023 23:13:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IHEAwWDFPzEAMt9jWC7rIslTSUOxjdJI9zx2VihjZ34FhLSL1SP4SY544gqJ3+MVOdHOlfr X-Received: by 2002:a05:6a00:15ca:b0:690:ce36:8b00 with SMTP id o10-20020a056a0015ca00b00690ce368b00mr1712743pfu.2.1700637180994; Tue, 21 Nov 2023 23:13:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700637180; cv=none; d=google.com; s=arc-20160816; b=oNzvtQ/kjGxysnIDyD4YJPr+sI+z3qTCfeWvi+yUSApK/wLSRoPN4jdR9xhj6mgcmz nj+kfZw1Di3MI/87QDcFmp+0eIFj74NuYcGqnJax53yGQeklixDa+I21Byfy5zdCL2zJ zi8CjBl+xm8TZTijrhwx/YGlT4qxW5D0wwsTYzkO5qD6Wogu7vpyFyXRXVk4y8cJd+99 IUwjsbtvs7WZnjs8lHqeLgp+HPy1hl+RCKqiG/4xsqJ7Vj93l8N/r/emK2VePB+/7WPJ 3uvzUPLLzkYxd7u+q3mZDkpAbKpo/yXN+4RXncOuka7pxH6D4TJHAYCHXXZoCHQHQtPs KGYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=8KIIwOOYOAIVazDSSyJZiSoqwV8HHBUfe3McSpMe1TE=; fh=Mmzz0bNh+f4WO6wVUF3DqgcPX/VhfXI1zeXnaWRCTIo=; b=kpEGdlh6aCqOiJtCejJ/BTmKTy6UmF3WFGO8wlMFxSUNiL5hu8WBQLTyLkzAORRlG9 dZ3so/sdsjK37HK8a5+3NXnxGWUgojTOuzTkutOk7eoebshk5a3fruXqcHbnhjSlPotH DWkMN8IZvOrGn3ndOiuIEOpT4XhmTgGTclvVa2Xk64xQmyRvnwbcY/FXDeXNyMa1G/R1 aFu6ZJJJ862bobtYQXuYTthS0aFGMWCBbPf24+AlVYUTk31GqKDKp/QbE/A6v45h+in4 Ay9oTXcvBqxRR5DI+jy1n3M5Z4Fd5rVi3+x53L6TEGkvb1EDYDSQ+U5WtgO54SfgIFc6 AD0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=kKY8t7vN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id e7-20020a056a001a8700b006cbaae6a079si5577591pfv.241.2023.11.21.23.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 23:13:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=kKY8t7vN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 2AA4D805A794; Tue, 21 Nov 2023 23:12:58 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234994AbjKVHLx (ORCPT + 99 others); Wed, 22 Nov 2023 02:11:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234904AbjKVHLi (ORCPT ); Wed, 22 Nov 2023 02:11:38 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AADE9D4F; Tue, 21 Nov 2023 23:11:34 -0800 (PST) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AM5pbxB026792; Wed, 22 Nov 2023 07:11:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=8KIIwOOYOAIVazDSSyJZiSoqwV8HHBUfe3McSpMe1TE=; b=kKY8t7vNAZgNm0ZH+/86F3Vg3hSmWTXw11nbPCUFoySbik2L44/W/2/9F9OpaVRtPrvA aIRRVUN5YvK8C34rTLRzUqh4kq/Y9ZKnb5Djwp5ItVQl4FGJ+6U/qAPMNJ6bTDq7KkIy hJk+wJapi7G4FjSgWvriL5mpWik/yINbgVuAJtIrigrx2GTtjil/uOLaW5xlpnEdaQr7 tS85mCVhj+eC76xWFTYFBVykljQ0vFtbxm1t+wMjj2c/l4ClO4d3R4U/v3VQvR6h7kQx HxL3UHRh7t/0z184gxYx58CkARhTzn17OuycSpZ0BCL8RyNh8w6algIyLMi0Xa8urVTn xA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ugu54avpp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 07:11:08 +0000 Received: from pps.filterd (NASANPPMTA05.qualcomm.com [127.0.0.1]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AM7079U009949; Wed, 22 Nov 2023 07:11:07 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA05.qualcomm.com (PPS) with ESMTP id 3uhcusg3yn-1; Wed, 22 Nov 2023 07:11:07 +0000 Received: from NASANPPMTA05.qualcomm.com (NASANPPMTA05.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AM73gRb016631; Wed, 22 Nov 2023 07:11:07 GMT Received: from stor-dylan.qualcomm.com (stor-dylan.qualcomm.com [192.168.140.207]) by NASANPPMTA05.qualcomm.com (PPS) with ESMTP id 3AM7B6Ck027691; Wed, 22 Nov 2023 07:11:07 +0000 Received: by stor-dylan.qualcomm.com (Postfix, from userid 359480) id A51AA20A65; Tue, 21 Nov 2023 23:11:06 -0800 (PST) From: Can Guo To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT), linux-phy@lists.infradead.org (open list:GENERIC PHY FRAMEWORK), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 09/11] phy: qualcomm: phy-qcom-qmp-ufs: Use tbls_hs_max instead of tbls_hs_g4 Date: Tue, 21 Nov 2023 23:10:40 -0800 Message-Id: <1700637042-11104-10-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Mjiel9YjSWy5SyAmriOj2vmlnC8hDKRD X-Proofpoint-ORIG-GUID: Mjiel9YjSWy5SyAmriOj2vmlnC8hDKRD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_04,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 bulkscore=0 phishscore=0 impostorscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 mlxlogscore=961 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220050 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:12:58 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247332848643202 X-GMAIL-MSGID: 1783247332848643202 Table tbls_hs_g4 is added to support HS Gear 4 and applied only if PHY submode is HS_G4. In future, we are adding support for Gear 5 and higher. To avoiding adding more tables, like tbls_hs_g5, let's use tbls_hs_max instead of tbls_hs_g4. In addition, max_hs_gear is added to indicate the maximum supported HS Gear of each configuration, so that we can check PHY submode against it to tell if tbls_hs_max needs to be applied. Signed-off-by: Can Guo --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 49 +++++++++++++++++---------------- 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index ad91f92..cae27a9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -735,8 +735,11 @@ struct qmp_phy_cfg { const struct qmp_phy_cfg_tbls tbls; /* Additional sequence for HS Series B */ const struct qmp_phy_cfg_tbls tbls_hs_b; - /* Additional sequence for HS G4 */ - const struct qmp_phy_cfg_tbls tbls_hs_g4; + /* Additional sequence for maximum supported HS Gear */ + const struct qmp_phy_cfg_tbls tbls_hs_max; + + /* Maximum supported HS Gear */ + u32 max_hs_gear; /* clock ids to be requested */ const char * const *clk_list; @@ -839,7 +842,7 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { .lanes = 1, .offsets = &qmp_ufs_offsets, - + .max_hs_gear = UFS_HS_G3, .tbls = { .serdes = msm8996_ufsphy_serdes, .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes), @@ -864,7 +867,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = { .lanes = 2, .offsets = &qmp_ufs_offsets, - + .max_hs_gear = UFS_HS_G4, .tbls = { .serdes = sm8350_ufsphy_serdes, .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), @@ -879,7 +882,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = { .serdes = sm8350_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, - .tbls_hs_g4 = { + .tbls_hs_max = { .tx = sm8350_ufsphy_g4_tx, .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), .rx = sm8350_ufsphy_g4_rx, @@ -898,7 +901,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { .lanes = 2, .offsets = &qmp_ufs_offsets, - + .max_hs_gear = UFS_HS_G4, .tbls = { .serdes = sm8350_ufsphy_serdes, .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), @@ -913,7 +916,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { .serdes = sm8350_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, - .tbls_hs_g4 = { + .tbls_hs_max = { .tx = sm8350_ufsphy_g4_tx, .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), .rx = sm8350_ufsphy_g4_rx, @@ -932,7 +935,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .lanes = 2, .offsets = &qmp_ufs_offsets, - + .max_hs_gear = UFS_HS_G3, .tbls = { .serdes = sdm845_ufsphy_serdes, .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), @@ -960,7 +963,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { .lanes = 1, .offsets = &qmp_ufs_offsets, - + .max_hs_gear = UFS_HS_G3, .tbls = { .serdes = sm6115_ufsphy_serdes, .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes), @@ -988,7 +991,7 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg = { .lanes = 1, .offsets = &qmp_ufs_offsets, - + .max_hs_gear = UFS_HS_G3, .tbls = { .serdes = sdm845_ufsphy_serdes, .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), @@ -1016,7 +1019,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .lanes = 2, .offsets = &qmp_ufs_offsets, - + .max_hs_gear = UFS_HS_G4, .tbls = { .serdes = sm8150_ufsphy_serdes, .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), @@ -1031,7 +1034,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .serdes = sm8150_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), }, - .tbls_hs_g4 = { + .tbls_hs_max = { .tx = sm8150_ufsphy_hs_g4_tx, .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), .rx = sm8150_ufsphy_hs_g4_rx, @@ -1050,7 +1053,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = { .lanes = 2, .offsets = &qmp_ufs_offsets, - + .max_hs_gear = UFS_HS_G4, .tbls = { .serdes = sm8150_ufsphy_serdes, .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), @@ -1065,7 +1068,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = { .serdes = sm8150_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), }, - .tbls_hs_g4 = { + .tbls_hs_max = { .tx = sm8250_ufsphy_hs_g4_tx, .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), .rx = sm8250_ufsphy_hs_g4_rx, @@ -1084,7 +1087,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .lanes = 2, .offsets = &qmp_ufs_offsets, - + .max_hs_gear = UFS_HS_G4, .tbls = { .serdes = sm8350_ufsphy_serdes, .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), @@ -1099,7 +1102,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .serdes = sm8350_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, - .tbls_hs_g4 = { + .tbls_hs_max = { .tx = sm8350_ufsphy_g4_tx, .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), .rx = sm8350_ufsphy_g4_rx, @@ -1118,7 +1121,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .lanes = 2, .offsets = &qmp_ufs_offsets, - + .max_hs_gear = UFS_HS_G4, .tbls = { .serdes = sm8350_ufsphy_serdes, .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), @@ -1133,7 +1136,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .serdes = sm8350_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, - .tbls_hs_g4 = { + .tbls_hs_max = { .tx = sm8350_ufsphy_g4_tx, .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), .rx = sm8350_ufsphy_g4_rx, @@ -1152,7 +1155,7 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { .lanes = 2, .offsets = &qmp_ufs_offsets_v6, - + .max_hs_gear = UFS_HS_G4, .tbls = { .serdes = sm8550_ufsphy_serdes, .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes), @@ -1235,11 +1238,11 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg if (qmp->mode == PHY_MODE_UFS_HS_B) qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); qmp_ufs_lanes_init(qmp, &cfg->tbls); - if (qmp->submode == UFS_HS_G4) - qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4); + if (qmp->submode == cfg->max_hs_gear) + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_max); qmp_ufs_pcs_init(qmp, &cfg->tbls); - if (qmp->submode == UFS_HS_G4) - qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4); + if (qmp->submode == cfg->max_hs_gear) + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_max); } static int qmp_ufs_com_init(struct qmp_ufs *qmp) From patchwork Wed Nov 22 07:10:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 168121 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1145466vqb; Tue, 21 Nov 2023 23:11:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IHenWeVcROgXZiK2pwPhzJXY7bqWLdGvOhqa1fLmQqFX2eZRCf/KUHURFgPuMhc5Z5evXMH X-Received: by 2002:a05:6871:53c5:b0:1c8:c27f:7d9b with SMTP id hz5-20020a05687153c500b001c8c27f7d9bmr1832572oac.27.1700637117519; Tue, 21 Nov 2023 23:11:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700637117; cv=none; d=google.com; s=arc-20160816; b=N1BEbQxIBAoYJJoNz0xDbjIc47ggIk4p/hRUqSzseSmn3aIPF2g5qMjHqTlpAwlzfo ztQ/fiaTYRSUaS+fwr8TixNBkAdKB6TeDqfyJsPkwUpJOu45tJSVUZ8gVf/wOfgl0zvq vCILdXu+e8LO9c3mMQmA/t/61MQFI+z0xGoOAFQT80ukj87mgUPP6D1UAPt6+az2wYFf Gf5hEcQxn+5KnxVXmqPDR1uDny7FS7FxxOwneV/YGneP8jtHE/gpJfMNnHS3HdZybgkX A8vwkVOuYKeVzsKXul0RDN88WMwG2Q0V+nDq4N92KmZ/yZhy9OIjnovRsX0LL8AviyXU 6YQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=a1qYfFLDdfwhm+jwjWAr0z37E0HqfVPYCzFxbAf8ENA=; fh=Mmzz0bNh+f4WO6wVUF3DqgcPX/VhfXI1zeXnaWRCTIo=; b=PamDGB9WIr5+8Vw+Z8Qrwkqy1a3aKn/tQKkztELYOHCmvnjMTtoatCpCAo7byua082 nbsYZYVGKlCwbvFrY/Kuplc+Sc1JpU7eGax7ggRFLr3D76xnnQDwjrjvOtZfJ4pC5MLE CG9l5g/x0fNDbS7rnmG6PKOfoK2m5+3qtlmQcM/l0i8vCA9jXmregPcp362k5Puhl6pB thEkT2zOqY229+SHMFsXgDkFwRNGAQWbceeWY8lYzL6tWTW+Fn1mSDfZc2Tv8qRU23i8 t2SITY5zjx/fLkvkaeMw0tMIT27vNk1qfnLUEaaN4EW1dufLJpfgi6gkTAoVTGdQgENu hcyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ai+BxE7T; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from lipwig.vger.email (lipwig.vger.email. [23.128.96.33]) by mx.google.com with ESMTPS id z12-20020a63e10c000000b005bdbcff21f5si12042804pgh.501.2023.11.21.23.11.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 23:11:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ai+BxE7T; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 60F7481C5276; Tue, 21 Nov 2023 23:11:47 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234884AbjKVHLn (ORCPT + 99 others); Wed, 22 Nov 2023 02:11:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234895AbjKVHLh (ORCPT ); Wed, 22 Nov 2023 02:11:37 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F50119D; Tue, 21 Nov 2023 23:11:33 -0800 (PST) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AM5Vdtn013067; Wed, 22 Nov 2023 07:11:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=a1qYfFLDdfwhm+jwjWAr0z37E0HqfVPYCzFxbAf8ENA=; b=ai+BxE7TYr2gHLDta9JHBzbvLbGhGt2ZObdeqFCIvFva8r2Yqx0PSCQ0NMpcaDXJEbva IUyySuthwZWzG7pmFsVq0xtnJTclq8zTOcpIaFtbYPeVHIHSs9c7a2BMP5xduGmxpBiC Qoo7F+3b0QiGDck8I2jnxOkkb6MhtqJJ827H9wLJXaAaiqgSZ0rekSOQFEwUPUAia+RJ j9n/nFYbR3aGbUXaJ0NFvVMOC6ubwFy8Tw6Z0U+nyiAcnT26fapJ+nSDFenKiAMSnZ1T WJff2IwJKWXWAz1b7+02poL+O8vAWcs/cOk9fXstk197wzAKrFef9ySBr28Rt3ODrfil Iw== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uhbjvg79d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 07:11:09 +0000 Received: from pps.filterd (NASANPPMTA01.qualcomm.com [127.0.0.1]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AM6mhQu003225; Wed, 22 Nov 2023 07:11:08 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA01.qualcomm.com (PPS) with ESMTP id 3ughrm95y1-1; Wed, 22 Nov 2023 07:11:08 +0000 Received: from NASANPPMTA01.qualcomm.com (NASANPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AM79BjZ002499; Wed, 22 Nov 2023 07:11:08 GMT Received: from stor-dylan.qualcomm.com (stor-dylan.qualcomm.com [192.168.140.207]) by NASANPPMTA01.qualcomm.com (PPS) with ESMTP id 3AM7B874007526; Wed, 22 Nov 2023 07:11:08 +0000 Received: by stor-dylan.qualcomm.com (Postfix, from userid 359480) id D41AB20A65; Tue, 21 Nov 2023 23:11:07 -0800 (PST) From: Can Guo To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT), linux-phy@lists.infradead.org (open list:GENERIC PHY FRAMEWORK), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 10/11] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550 Date: Tue, 21 Nov 2023 23:10:41 -0800 Message-Id: <1700637042-11104-11-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: zjsuQWM6NmLOYJ0ZfL1ESKQjTJwZkcje X-Proofpoint-ORIG-GUID: zjsuQWM6NmLOYJ0ZfL1ESKQjTJwZkcje X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_04,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 adultscore=0 mlxscore=0 phishscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220050 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:11:47 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247266564030834 X-GMAIL-MSGID: 1783247266564030834 On SM8550, two sets of UFS PHY settings are provided, one set is to support HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY settings are programming different values to different registers, mixing the two sets and/or overwriting one set with another set is definitely not blessed by UFS PHY designers. To add HS-G5 support for SM8550, split the two sets of PHY settings into their dedicated tables, G5 specific settings are put into .tbls_hs_max, no-G5 settings are put into .tbls_hs_not_max. Only the common parts of the two sets of PHY settings are left in the .tbls. In this case, .tbls alone is not a complete set of PHY settings, so either tbls_hs_max or tbls_hs_not_max should be applied on top of the .tbls to become a complete set of PHY settings. Signed-off-by: Can Guo --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 + drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 + .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 9 ++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 102 +++++++++++++++++++-- 4 files changed, 105 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h index c23d5e4..e563af5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h @@ -18,6 +18,7 @@ #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158 #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184 @@ -27,5 +28,6 @@ #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8 #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4 #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220 #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h index f420f8f..ef392ce 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h @@ -56,6 +56,8 @@ #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4 #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8 #define QSERDES_V6_COM_PLL_IVCO 0xf4 +#define QSERDES_V6_COM_CMN_IETRIM 0xfc +#define QSERDES_V6_COM_CMN_IPTRIM 0x100 #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110 #define QSERDES_V6_COM_RESETSM_CNTRL 0x118 #define QSERDES_V6_COM_LOCK_CMP_EN 0x120 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h index 674f158..48f31c8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h @@ -15,8 +15,15 @@ #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24 +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54 #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4 +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0 +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4 #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214 @@ -28,6 +35,8 @@ #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264 #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270 #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280 +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284 #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8 #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index cae27a9..7a382c4 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -649,15 +649,22 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), @@ -666,19 +673,24 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), }; -static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), }; static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = { QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c), }; static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), @@ -694,16 +706,45 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), }; +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff), + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), +}; + static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), +}; + +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), }; +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), +}; + struct qmp_ufs_offsets { u16 serdes; u16 pcs; @@ -735,6 +776,8 @@ struct qmp_phy_cfg { const struct qmp_phy_cfg_tbls tbls; /* Additional sequence for HS Series B */ const struct qmp_phy_cfg_tbls tbls_hs_b; + /* Additional sequence for HS Gears which are lower than the maximum supported HS Gear */ + const struct qmp_phy_cfg_tbls tbls_hs_not_max; /* Additional sequence for maximum supported HS Gear */ const struct qmp_phy_cfg_tbls tbls_hs_max; @@ -1155,7 +1198,7 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { .lanes = 2, .offsets = &qmp_ufs_offsets_v6, - .max_hs_gear = UFS_HS_G4, + .max_hs_gear = UFS_HS_G5, .tbls = { .serdes = sm8550_ufsphy_serdes, .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes), @@ -1170,6 +1213,24 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { .serdes = sm8550_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), }, + .tbls_hs_not_max = { + .serdes = sm8550_ufsphy_g4_serdes, + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes), + .tx = sm8550_ufsphy_g4_tx, + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx), + .rx = sm8550_ufsphy_g4_rx, + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx), + .pcs = sm8550_ufsphy_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs), + }, + .tbls_hs_max = { + .serdes = sm8550_ufsphy_g5_serdes, + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes), + .rx = sm8550_ufsphy_g5_rx, + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx), + .pcs = sm8550_ufsphy_g5_pcs, + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -1232,17 +1293,36 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num); } -static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) +static int qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) { + if (qmp->submode > cfg->max_hs_gear) { + dev_err(qmp->dev, "PHY submode %u exceeds maximum supported gear %u\n", + qmp->submode, cfg->max_hs_gear); + return -EINVAL; + } + qmp_ufs_serdes_init(qmp, &cfg->tbls); + if (qmp->submode == cfg->max_hs_gear) + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_max); + else + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_not_max); + if (qmp->mode == PHY_MODE_UFS_HS_B) qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); + qmp_ufs_lanes_init(qmp, &cfg->tbls); if (qmp->submode == cfg->max_hs_gear) qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_max); + else + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_not_max); + qmp_ufs_pcs_init(qmp, &cfg->tbls); if (qmp->submode == cfg->max_hs_gear) qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_max); + else + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_not_max); + + return 0; } static int qmp_ufs_com_init(struct qmp_ufs *qmp) @@ -1334,7 +1414,9 @@ static int qmp_ufs_power_on(struct phy *phy) unsigned int val; int ret; - qmp_ufs_init_registers(qmp, cfg); + ret = qmp_ufs_init_registers(qmp, cfg); + if (ret) + return ret; ret = reset_control_deassert(qmp->ufs_reset); if (ret) From patchwork Wed Nov 22 07:10:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Can Guo X-Patchwork-Id: 168124 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp1145827vqb; Tue, 21 Nov 2023 23:12:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IE4mAHs5cQ6vqe7hlulq3zu2LKbPNXwiBK7zrDgqDMJWtrsTi6bxdNPIDFyaf6/VQhz/rdb X-Received: by 2002:aca:2115:0:b0:3ad:f6ad:b9c5 with SMTP id 21-20020aca2115000000b003adf6adb9c5mr1753111oiz.59.1700637169899; Tue, 21 Nov 2023 23:12:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700637169; cv=none; d=google.com; s=arc-20160816; b=i4R9UhpAB8s5pA4Gl7E7s2PcUqzyNtcO73nfuJTHqYVcMaQG+CAo1+AY1dJegJNu+L VAo9simdf53/yEoBy9PrZcu4UL5loAlX8WYc1YZfTOmheVmW0jTj08JVGQySb2UNnbzn +X6/fxBhb9EssPzfu0Ej1klr6PBRD2JpaTnWp+DWx46KrrELRdIDy5yt3U+zn/8yY7dg VYWF3ey0mlBFgDpcwGhGCwOilJKrgzTM75mE4F8gvxQIH7werTqFkKpeJlAaxCswG8U6 9d9RxG3Zrfy4HZo/29ZW8mF/PRlGo/kHpwGKYEgvz4mESHgZqABKM4LMTL2hai5WcNWV SosA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=DFF6SBown3zJI3vv5koqMtjckFgbW+mpaijN5lmrUrY=; fh=lalENY90My7TZJF1CKddC9t+QyXXuf4U+2P3z4+1hVM=; b=0ubIPYSBlqv6TgdTVIhkeIneaUdKWeLY0AITYDuPz10/M+zke3AoKbJUoSgG/r+CcG 8SIsO45ep0NZdNwWsfwPW5g/fo8Dml5/lP8NDEUMh3D9Md0uQVJhWVxZdPNhGMbNVp08 kg4IitSKwgi4JvHR0x9+UqaIn1kC1huzYPpxhGNgrGrwiG6Q8BgNwlFhEYxHgM69VmH1 o+ATiUIAQb7/PTglOU1BCHxpdvYTdP82KTrlD2Lp7AG/JKqlF+RyLABlD4dE9/bi1NKk ZF3zQMBI6uJMVuVUz0nfWWbZs0vp9LTrd4Cx9RGYZeEOFkf/Ro4hGSDlYISEQkEob89R kviQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=hf8rmGXB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id t10-20020a056a0021ca00b006cb8abd39d3si6780223pfj.180.2023.11.21.23.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 23:12:49 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=hf8rmGXB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 167D0802893B; Tue, 21 Nov 2023 23:12:46 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235023AbjKVHMB (ORCPT + 99 others); Wed, 22 Nov 2023 02:12:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230166AbjKVHLm (ORCPT ); Wed, 22 Nov 2023 02:11:42 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92BC81A8; Tue, 21 Nov 2023 23:11:38 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AM4xb8F008924; Wed, 22 Nov 2023 07:11:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=DFF6SBown3zJI3vv5koqMtjckFgbW+mpaijN5lmrUrY=; b=hf8rmGXB2J/j0b8ugHJpdN7QTg5LkHyQBX4IO58EzgErCdO3TkqnwC/XJJm019urv50v Sb6FYowR93pb/R/qurIrEWhfisbjhRK+QgdQ1ueYKInvxtX89GxiryTe/yHeXTIBpQGk XXCYHJrN7fxzwWiWbShQJoEh3mzHDLsEwYwG3zsBwTnX6tvd9OboJvypcOJeVz6jd6+G sYk1wcBkv/IZUW7Nl1X3PBYcTgXxe6MpaYK/zNl7O4Opjr6JNL33IUD8bx36FLV8/1QP 9sZeoUZcQAayH4kG2GqNozIl2jorIEpKDZYgtwYpQJu1IOHWYCDfQnyUTa4ynV04BOsQ Lw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uh8mw8hdj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Nov 2023 07:11:11 +0000 Received: from pps.filterd (NASANPPMTA02.qualcomm.com [127.0.0.1]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3AM77Vp9004501; Wed, 22 Nov 2023 07:11:11 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NASANPPMTA02.qualcomm.com (PPS) with ESMTP id 3uepbmy82y-1; Wed, 22 Nov 2023 07:11:11 +0000 Received: from NASANPPMTA02.qualcomm.com (NASANPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AM7BAD0011287; Wed, 22 Nov 2023 07:11:10 GMT Received: from stor-dylan.qualcomm.com (stor-dylan.qualcomm.com [192.168.140.207]) by NASANPPMTA02.qualcomm.com (PPS) with ESMTP id 3AM7BAnR011286; Wed, 22 Nov 2023 07:11:10 +0000 Received: by stor-dylan.qualcomm.com (Postfix, from userid 359480) id 5852C20A65; Tue, 21 Nov 2023 23:11:10 -0800 (PST) From: Can Guo To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org, stanley.chu@mediatek.com, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com Cc: "Bao D. Nguyen" , Andy Gross , Bjorn Andersson , Konrad Dybcio , "James E.J. Bottomley" , linux-arm-msm@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-scsi@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 11/11] scsi: ufs: ufs-qcom: Add support for UFS device version detection Date: Tue, 21 Nov 2023 23:10:42 -0800 Message-Id: <1700637042-11104-12-git-send-email-quic_cang@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> References: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 2JxcIQFQgEb8s8n8GM-w4RcOHz2QZtsN X-Proofpoint-ORIG-GUID: 2JxcIQFQgEb8s8n8GM-w4RcOHz2QZtsN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-22_05,2023-11-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311220051 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 21 Nov 2023 23:12:46 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783247320934512073 X-GMAIL-MSGID: 1783247320934512073 From: "Bao D. Nguyen" A spare register in UFS host controller is used to indicate the UFS device version. The spare register is populated by bootloader for now, but in future it will be populated by HW automatically during link startup with its best efforts in any boot stages prior to Linux. During host driver init, read the spare register, if it is not populated with a UFS device version, go ahead with the dual init mechanism. If a UFS device version is in there, use the UFS device version together with host controller's HW version to decide the proper PHY gear which should be used to configure the UFS PHY without going through the second init. Signed-off-by: Bao D. Nguyen Signed-off-by: Can Guo --- drivers/ufs/host/ufs-qcom.c | 23 ++++++++++++++++++----- drivers/ufs/host/ufs-qcom.h | 2 ++ 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 7bbccf4..70bedd9 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1070,15 +1070,28 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host) { struct ufs_host_params *host_params = &host->host_params; + u32 val, dev_major = 0; host->phy_gear = host_params->hs_tx_gear; - /* - * Power up the PHY using the minimum supported gear (UFS_HS_G2). - * Switching to max gear will be performed during reinit if supported. - */ - if (host->hw_ver.major < 0x5) + if (host->hw_ver.major < 0x5) { + /* + * Power up the PHY using the minimum supported gear (UFS_HS_G2). + * Switching to max gear will be performed during reinit if supported. + */ host->phy_gear = UFS_HS_G2; + } else { + val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); + dev_major = FIELD_GET(GENMASK(7, 4), val); + + /* UFS device version populated, no need to do init twice */ + if (dev_major != 0) + host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; + + /* For UFS 3.1 and older, apply HS-G4 PHY gear to save power */ + if (dev_major < 0x4 && dev_major > 0) + host->phy_gear = UFS_HS_G4; + } } static void ufs_qcom_set_host_params(struct ufs_hba *hba) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 11419eb..d12fc5a 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -54,6 +54,8 @@ enum { UFS_AH8_CFG = 0xFC, REG_UFS_CFG3 = 0x271C, + + REG_UFS_DEBUG_SPARE_CFG = 0x284C, }; /* QCOM UFS host controller vendor specific debug registers */