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[8.43.85.97]) by mx.google.com with ESMTPS id l8-20020a0cd6c8000000b0066d1d01e982si10523158qvi.148.2023.11.21.22.12.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 22:12:34 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 13DD43858C3A for ; Wed, 22 Nov 2023 06:12:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id 720F23858D35 for ; Wed, 22 Nov 2023 06:12:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 720F23858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 720F23858D35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.92.39.34 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700633531; cv=none; b=aSBlngnSCcP65pqgNosDJ180wnmqRPLjsF5iN+0gmFs4fNF2yhX23rn+SqYHsxpOVpdT9YME4Z8Y6Nm0nq6ilbVS2Z0HkTs9jLbKEIHOEsGZPRtkvpSYYod83MIh2vPxpsv1j7xgxzqX8Nvvj2wcuAUztxTMJM25iXfavRjJ1rI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700633531; c=relaxed/simple; bh=eC8GlfbMiYEXgR4pgwlfeSkZjjcGNe1b3dDIM2786wA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=LvGsLKtGdTFRq+Tb/MlCKr6Ycl7GYnDPwCnYCTJdqiHF14p4Sz/g5VoxKqcUydGg7RCCbz9dB44K+yZFJSV+fYuuSVBEjtX/kAtUvNrNNZ6c1UuS7ujyI+Tcmy7JphtYccQeHc4HPbAn8lJ9Vsqhm1+IoWoYl/VAoR9+xqK0UAw= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp76t1700633523tvcq2ici Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Nov 2023 14:12:02 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: o+ZMjaAbu78aP3k/t871GKskG4Yjh+6+qGj4ALDFJFA0YDMPOekUss0shGCzl qhxTH+LnAYzJ66amuPcSfLOLEAPsJc+nA3Fpv+PniopGJdLGojt/WBlLAR0IyWE96nozjaK /goMfb1OFo6ZBhiDrF9AN+az2McQ/L8wFfBc43oSHojoUkqkkrPCWLb5N7e9Ii41ArtrbWc EZi9keQMKK/nuULA59t/qAu7NGhwX/UKe7Xq+Edu0znDCkZ+6KUdppZV56D4OU9IYDrBzxl gyNDJt0hQS3b15bQ5K6ZitOwcUPq+LfvbivD1tieW9Ri1djd/r/KyO4ncX2XZ3XfMwVTqCl ocWHR2SNDTRc9Yz5BIEhT83illoYSNCIlVUbPKxjCe6jn/15FGOtgJq//lG41dpF9bJBtrz f3U/bFXmMiC4jOesrdpLDQ== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 3360990997147053595 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix permutation indice mode bug Date: Wed, 22 Nov 2023 14:12:01 +0800 Message-Id: <20231122061201.3690516-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783243529624158269 X-GMAIL-MSGID: 1783243529624158269 This patch fixes following FAILs on zvl512b: FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-1.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-16.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-16.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-17.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-17.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-3.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-3.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-5.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-5.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-6.c execution test FAIL: gcc.target/riscv/rvv/autovec/partial/slp_run-6.c execution test The root cause is that we are using vrgather.vv on vector QI mode which is incorrect for zvl512b since it exceed 256. Instead, we should use vrgatherei16.vv PR target/112598 gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Adapt the priority. (shuffle_generic_patterns): Fix permutation indice bug. * config/riscv/vector-iterators.md: Fix VEI16 bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112598-2.c: New test. --- gcc/config/riscv/riscv-v.cc | 31 ++++++++++++++----- gcc/config/riscv/vector-iterators.md | 14 ++++----- .../gcc.target/riscv/rvv/autovec/pr112598-2.c | 24 ++++++++++++++ 3 files changed, 54 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 541dffba07b..7d6d0821d87 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -839,13 +839,13 @@ emit_vlmax_gather_insn (rtx target, rtx op, rtx sel) insn_code icode; machine_mode data_mode = GET_MODE (target); machine_mode sel_mode = GET_MODE (sel); - if (maybe_ne (GET_MODE_SIZE (data_mode), GET_MODE_SIZE (sel_mode))) - icode = code_for_pred_gatherei16 (data_mode); - else if (const_vec_duplicate_p (sel, &elt)) + if (const_vec_duplicate_p (sel, &elt)) { icode = code_for_pred_gather_scalar (data_mode); sel = elt; } + else if (maybe_ne (GET_MODE_SIZE (data_mode), GET_MODE_SIZE (sel_mode))) + icode = code_for_pred_gatherei16 (data_mode); else if (CONST_VECTOR_P (sel) && GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)) > 16 && riscv_get_v_regno_alignment (data_mode) > 1) @@ -3261,11 +3261,26 @@ shuffle_generic_patterns (struct expand_vec_perm_d *d) if (!pow2p_hwi (d->perm.encoding().npatterns ())) return false; - /* Permuting two SEW8 variable-length vectors need vrgatherei16.vv. - Otherwise, it could overflow the index range. */ - if (!nunits.is_constant () && GET_MODE_INNER (d->vmode) == QImode - && !get_vector_mode (HImode, nunits).exists (&sel_mode)) - return false; + if (GET_MODE_INNER (d->vmode) == QImode) + { + if (nunits.is_constant ()) + { + /* If indice is LMUL8 CONST_VECTOR and any element value + exceed the range of 0 ~ 255, Forbid such permutation + since we need vector HI mode to hold such indice and + we don't have it. */ + if (!d->perm.all_in_range_p (0, 255) + && !get_vector_mode (HImode, nunits).exists (&sel_mode)) + return false; + } + else + { + /* Permuting two SEW8 variable-length vectors need vrgatherei16.vv. + Otherwise, it could overflow the index range. */ + if (!get_vector_mode (HImode, nunits).exists (&sel_mode)) + return false; + } + } /* Success! */ if (d->testing_p) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 10187306de8..27dae102fff 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -376,13 +376,13 @@ (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)") (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)") (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)") - (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)") - (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64") - (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128") - (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256") - (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512") - (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024") - (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048") + (V32QI "riscv_vector::vls_mode_valid_p (V32QImode) && TARGET_MIN_VLEN >= 64") + (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 128") + (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 256") + (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 512") + (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 1024") + (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 2048") + (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 4096") (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)") (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)") (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c new file mode 100644 index 00000000000..d32e8bacb5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */ + +#include + +void +f (uint8_t *restrict a, uint8_t *restrict b, int n) +{ + for (int i = 0; i < n; ++i) + { + a[i * 8] = b[i * 8 + 3] + 1; + a[i * 8 + 1] = b[i * 8 + 2] + 2; + a[i * 8 + 2] = b[i * 8 + 1] + 3; + a[i * 8 + 3] = b[i * 8 + 0] + 4; + a[i * 8 + 4] = b[i * 8 + 7] + 5; + a[i * 8 + 5] = b[i * 8 + 6] + 6; + a[i * 8 + 6] = b[i * 8 + 5] + 7; + a[i * 8 + 7] = b[i * 8 + 4] + 8; + } +} + +/* We don't want EEW8 LMUL8 vrgather.vv. */ +/* { dg-final { scan-assembler-not {vrgather\.vv} } } */ +