From patchwork Tue Nov 21 12:50:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167722 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp594278vqb; Tue, 21 Nov 2023 04:51:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IF6DWGO1it245pQscgwFsuaH0OfOIml2vd3Rt6X/Wqd/aD204RBvYOgk0rGjDpluakKAVGp X-Received: by 2002:a05:6830:1508:b0:6c6:4a8d:da98 with SMTP id k8-20020a056830150800b006c64a8dda98mr12342673otp.24.1700571080526; Tue, 21 Nov 2023 04:51:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571080; cv=none; d=google.com; s=arc-20160816; b=dGdW2+SRmcCq7GqDRhv5UbbzbMkO56KtcZNKFjDAGDblJBPvOgYYAlJyD424OUnirN Lpg79kAWpWLLqGf5I+TR4WMvEZ9LxXi9ao3wOmcjp4mnjy39pVdPsz8dLNIvYRMd9oV0 Ld+Y17uI9m5PSqr1gJYKaE9wmeG5//X4Lb+z3rY5lT+aQUlMi+9CC0bwU3xH9hp/tt+2 y7puj2SdNXkhknaBRBL2onbCW64kmxIAQduUmZv/zZUgjKXePOfOsIVo5pwWeHgG+Hym dvMDi6MeIocZIEQtGnpJaExdlMHvXWA+Cb4HUh8YfLr12aqefpaT/aiSKC6ii4vtxGX+ YLwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7MZURram4+AEa4dg4UWiA48/8EOrUGOb9rBxviQ2z8M=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=JuSZRso5cgE7r80OWWESUNf8vyGvtr/pzwpso4Q+XfEh0VKp/xpjW3osjjjzLoECyW ZwATYWdqgAqt+zqtLRzmBLn1G+h7dGrV3URoNbk/gi6eHOpx3IBSjh3SCjG9rdNRwdQ+ SIeeiAMtbsJPSdVm0Wfu5azW6TMn8vW6mqq0jdvxMWnZvhL1qvyE/bU78MQZboKsGR77 6VE08LTYj8Bf53bYjs3LOSOIXqp8wmoYIhiDUjkEVYjisJXqS1jRY/lqLCSRJLEnDdBu HOupdClUpfNxNhypxgECGJdtVRnetPgiHyBnwQksXqymO8C+xpRafILXY9wm0RhfuGrR Xz9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=czu1IDXk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id m65-20020a632644000000b005859aec9406si10610659pgm.16.2023.11.21.04.51.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:51:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=czu1IDXk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 95A998026419; Tue, 21 Nov 2023 04:51:03 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233662AbjKUMu7 (ORCPT + 99 others); Tue, 21 Nov 2023 07:50:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232565AbjKUMu4 (ORCPT ); Tue, 21 Nov 2023 07:50:56 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 857B9D40; Tue, 21 Nov 2023 04:50:53 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 71F976607319; Tue, 21 Nov 2023 12:50:51 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571052; bh=sMWHddCvw/Ujx/UtO/I5fhryZnx4605LdfFnzpLxwHk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=czu1IDXkmfGQoXXAY2Ow6FUdSqnS8A6KSLHq2XIAtyYRq99vMp8hN4BBJQwJloPGU YRFADA3lT5OI/VXHS/TqZJDuGYzC3Gc44c2JupQkz/U8NIa+7aOs6Nb3fbPWFMjTIt uIxxdNLJXuIu+tScgpWR0XLVufgCxzg4n/IrAMBnfMDUkyP8tvdF8IFZp6cbMycZgp +PrXThhHX8MzgDTNasu3VM0HZtvCBl6owq9byofRwQKU3gC5P2eNPNTNSBOTVmfMIh XNONNivfhxcRDBTU5Kqs/4dvVLDnaXcnNQLeBp23U00xLzh8eBUCLUAJyT7HdXQgN8 VxpwdUmg8j37A== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 01/20] arm64: dts: mediatek: mt8183: Change iospaces for thermal and svs Date: Tue, 21 Nov 2023 13:50:25 +0100 Message-ID: <20231121125044.78642-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:51:03 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178021147000865 X-GMAIL-MSGID: 1783178021147000865 The SVS iospace starts at 0x1100bc00 and not at 0x1100b000 as the latter is the thermal sensor iospace instead. Change the iospaces for both as following: - Thermal: 0x1100b000, length 0xc00 - SVS: 0x1100bc00, length 0x400 Please note that while this would be a breaking change for SVS (but not for thermal sensors), it doesn't matter because the svs driver never worked anyway because of the missing trips in tzts2, causing that thermal zone to never actually register, hence the SVS driver to fail probing anyway. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 26 ++++++++++++------------ 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5169779d01df..13c3104bc67b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1183,22 +1183,10 @@ spi0: spi@1100a000 { status = "disabled"; }; - svs: svs@1100b000 { - compatible = "mediatek,mt8183-svs"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_THERM>; - clock-names = "main"; - nvmem-cells = <&svs_calibration>, - <&thermal_calibration>; - nvmem-cell-names = "svs-calibration-data", - "t-calibration-data"; - }; - thermal: thermal@1100b000 { #thermal-sensor-cells = <1>; compatible = "mediatek,mt8183-thermal"; - reg = <0 0x1100b000 0 0x1000>; + reg = <0 0x1100b000 0 0xc00>; clocks = <&infracfg CLK_INFRA_THERM>, <&infracfg CLK_INFRA_AUXADC>; clock-names = "therm", "auxadc"; @@ -1210,6 +1198,18 @@ thermal: thermal@1100b000 { nvmem-cell-names = "calibration-data"; }; + svs: svs@1100bc00 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100bc00 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, + <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", + "t-calibration-data"; + }; + thermal_zones: thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <100>; From patchwork Tue Nov 21 12:50:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167723 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp594351vqb; Tue, 21 Nov 2023 04:51:30 -0800 (PST) X-Google-Smtp-Source: AGHT+IEMDzbJr6NZwkjdv57oxKsEYGHlpw52WnPNlq1Z2IDbHw7Rhb6fqWfRzdKtAB7yv5GRqLVW X-Received: by 2002:a05:6808:1410:b0:3b5:a58c:cca6 with SMTP id w16-20020a056808141000b003b5a58ccca6mr14737460oiv.3.1700571090120; Tue, 21 Nov 2023 04:51:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571090; cv=none; d=google.com; s=arc-20160816; b=Krj0PMKfwiwrdZkbYGiQqKiq9Mhg2cr+zFnWyiAhnSFo+CTYwW9LTpxqxITtM5Wt11 S+S2adexIG3reu3nqYN4McxYKaLxLLJs5Y8limB+GMyLt0+X3dkAbNIZzqv/1Atkux+W fTbJU5WRlbTZrz32r1IppwPEDVhFD/Lo4HHJV8IiKYVSZ158OQtAdtS7urD+GLgMwEBi 8hM4CNJVzpYa8Vbd1iaoAwULYZBphq0GuBdHEPmqb3bwvNh7w1+OmK9oUl/88hJ9scDG 5WMoTfudGdanl+EEnfFiMPlFlpad3u4weMebrPxxD1PuKPVWKLhY0ujqEzQEN6NRKReH 0qNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XXs9aA28Fb/zI3HoK+Y5RpS9a5/sxHENqTOcKG51emk=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=S9GvAH2m9Xs+blZDtyeN203oLlphIDF7h82uXuO4FaRpgMtjn/bJCMeSNrYFeA7FhT FMwsWoYdwh5ndughsGDNE/f6SRo92TNZSEtIuc77Mu1S1emglho0wYF442Zre2FP2rxc mCzvTOZVmfp/QbCHDZl5vaoiYXP2TMQ+paqLetRaQ3wHk4LGtahUi+7xQ/Ef3NA413k7 5Ls8/BU8KjRu+TLAib87pjCNBXebQ96vHXv8PSFxa8pDTHohv51UnyolcmBa3fnlQMFu nOVLlHVECnyY716Jod5xC590vTYDl8A9qkWcZAevR9amyT5o9Bh8hMEbOPHqIEpOYZNK 13ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=h3yC6uUj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id j12-20020a63594c000000b005b98a7d2545si10287831pgm.527.2023.11.21.04.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:51:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=h3yC6uUj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id D97808027486; Tue, 21 Nov 2023 04:51:09 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233718AbjKUMvD (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233508AbjKUMu6 (ORCPT ); Tue, 21 Nov 2023 07:50:58 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 876D5D47; Tue, 21 Nov 2023 04:50:54 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7F86F660731B; Tue, 21 Nov 2023 12:50:52 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571053; bh=N42OlgtNsTN3hPgxRyKN1KLxCwyU6QyhLsWFXT5/rjk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h3yC6uUj28WfIhgoUfzT29/Zzy2yxGMeJyePbi04yGzRTSzNkWYwUVZM7bDwZLnmp b+kKOcIOqAUa4rqcuR+atOblgacwvANZY9VIUhZ7wFOsoO3SU3AEPU6mQFL9LzAVWy 3RO3PHwW39VUgrJXFa9bRXQVemjvm/s9SZC2rqYVAF3Mxp53ZH/yFZz1fbCoI7zBe2 P4kAbX8OEz6BjAPsGwYK69ByTcZryU6AUrYir7l4yTBD9v7rPsxBS6QcURNuwQ3v1A irGIVqSYKFNqycFoHlRjslL9v7Af1S8ZI0Pg6+x4DyDquM5bOB1X6DdHOY+Sj9mInn QXrFZv+ij4+6A== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 02/20] soc: mediatek: mtk-svs: Subtract offset from regs_v2 to avoid conflict Date: Tue, 21 Nov 2023 13:50:26 +0100 Message-ID: <20231121125044.78642-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:51:10 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178031225755784 X-GMAIL-MSGID: 1783178031225755784 The svs_regs_v2 array of registers was offsetted by 0xc00 because the SVS node was supposed to have the same iostart as the thermal sensors. That's wrong for two reasons: 1. Two different devices cannot have the same iostart in devicetree, as those would technically be the same device otherwise; and 2. SVS and Thermal Sensor (be it LVTS or AUXADC thermal) are not the same IP, and those two do obviously have a different iospace. Even though there already are users of this register array, the only one that declares a devicetree node for SVS is MT8183 - but it never actually worked because the "tzts1" thermal zone missed thermal trips, hence this driver's probe always failed on that SoC. Knowing this - it is safe to say that keeping compatibility with older device trees is pointless, hence simply subtract the 0xc00 offset from the register offset array. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 108 ++++++++++++++++----------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 0f7cfbe5630b..416e9b313c0a 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -256,60 +256,60 @@ enum svs_reg_index { }; static const u32 svs_regs_v2[] = { - [DESCHAR] = 0xc00, - [TEMPCHAR] = 0xc04, - [DETCHAR] = 0xc08, - [AGECHAR] = 0xc0c, - [DCCONFIG] = 0xc10, - [AGECONFIG] = 0xc14, - [FREQPCT30] = 0xc18, - [FREQPCT74] = 0xc1c, - [LIMITVALS] = 0xc20, - [VBOOT] = 0xc24, - [DETWINDOW] = 0xc28, - [CONFIG] = 0xc2c, - [TSCALCS] = 0xc30, - [RUNCONFIG] = 0xc34, - [SVSEN] = 0xc38, - [INIT2VALS] = 0xc3c, - [DCVALUES] = 0xc40, - [AGEVALUES] = 0xc44, - [VOP30] = 0xc48, - [VOP74] = 0xc4c, - [TEMP] = 0xc50, - [INTSTS] = 0xc54, - [INTSTSRAW] = 0xc58, - [INTEN] = 0xc5c, - [CHKINT] = 0xc60, - [CHKSHIFT] = 0xc64, - [STATUS] = 0xc68, - [VDESIGN30] = 0xc6c, - [VDESIGN74] = 0xc70, - [DVT30] = 0xc74, - [DVT74] = 0xc78, - [AGECOUNT] = 0xc7c, - [SMSTATE0] = 0xc80, - [SMSTATE1] = 0xc84, - [CTL0] = 0xc88, - [DESDETSEC] = 0xce0, - [TEMPAGESEC] = 0xce4, - [CTRLSPARE0] = 0xcf0, - [CTRLSPARE1] = 0xcf4, - [CTRLSPARE2] = 0xcf8, - [CTRLSPARE3] = 0xcfc, - [CORESEL] = 0xf00, - [THERMINTST] = 0xf04, - [INTST] = 0xf08, - [THSTAGE0ST] = 0xf0c, - [THSTAGE1ST] = 0xf10, - [THSTAGE2ST] = 0xf14, - [THAHBST0] = 0xf18, - [THAHBST1] = 0xf1c, - [SPARE0] = 0xf20, - [SPARE1] = 0xf24, - [SPARE2] = 0xf28, - [SPARE3] = 0xf2c, - [THSLPEVEB] = 0xf30, + [DESCHAR] = 0x00, + [TEMPCHAR] = 0x04, + [DETCHAR] = 0x08, + [AGECHAR] = 0x0c, + [DCCONFIG] = 0x10, + [AGECONFIG] = 0x14, + [FREQPCT30] = 0x18, + [FREQPCT74] = 0x1c, + [LIMITVALS] = 0x20, + [VBOOT] = 0x24, + [DETWINDOW] = 0x28, + [CONFIG] = 0x2c, + [TSCALCS] = 0x30, + [RUNCONFIG] = 0x34, + [SVSEN] = 0x38, + [INIT2VALS] = 0x3c, + [DCVALUES] = 0x40, + [AGEVALUES] = 0x44, + [VOP30] = 0x48, + [VOP74] = 0x4c, + [TEMP] = 0x50, + [INTSTS] = 0x54, + [INTSTSRAW] = 0x58, + [INTEN] = 0x5c, + [CHKINT] = 0x60, + [CHKSHIFT] = 0x64, + [STATUS] = 0x68, + [VDESIGN30] = 0x6c, + [VDESIGN74] = 0x70, + [DVT30] = 0x74, + [DVT74] = 0x78, + [AGECOUNT] = 0x7c, + [SMSTATE0] = 0x80, + [SMSTATE1] = 0x84, + [CTL0] = 0x88, + [DESDETSEC] = 0xe0, + [TEMPAGESEC] = 0xe4, + [CTRLSPARE0] = 0xf0, + [CTRLSPARE1] = 0xf4, + [CTRLSPARE2] = 0xf8, + [CTRLSPARE3] = 0xfc, + [CORESEL] = 0x300, + [THERMINTST] = 0x304, + [INTST] = 0x308, + [THSTAGE0ST] = 0x30c, + [THSTAGE1ST] = 0x310, + [THSTAGE2ST] = 0x314, + [THAHBST0] = 0x318, + [THAHBST1] = 0x31c, + [SPARE0] = 0x320, + [SPARE1] = 0x324, + [SPARE2] = 0x328, + [SPARE3] = 0x32c, + [THSLPEVEB] = 0x330, }; /** From patchwork Tue Nov 21 12:50:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167726 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp594778vqb; Tue, 21 Nov 2023 04:52:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IFLai+kYJm0sVCAGHlWs150QfvHhApf5x7j0TXhdtA8qGZ5zmzJfLvkuXPvT/8EqbxiUAIz X-Received: by 2002:a17:90a:3049:b0:27d:4b20:3604 with SMTP id q9-20020a17090a304900b0027d4b203604mr7861971pjl.27.1700571143582; Tue, 21 Nov 2023 04:52:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571143; cv=none; d=google.com; s=arc-20160816; b=ByFGsE71wCdZk0j4+Y1A80lwzpj/39rMVTGxB6Uza4cX6UGfhuYYkVu5EWQK0sSbR+ g2fYHLUgke/G0We55OzZ/IokCRzmho2R29m05c5EwPnepKws8JtwXVN+uKu4BxXQQeSu BOgG8pKf4UUAwMreyuofg3EBx/gG34vm3DPtTy9mQzec6q+phTGPccNtHd7tQnqw1W66 97zf8Utp2raMEgBM+9vj/rwREHcsTA12M9P8Ngyzr9PopQ4eHhlpQcJlZYaS30wnEfnV j02j9HUHaibsTGHJza0VvdYF0CUGW93MjYEmiAA4AZPFCmnPo2X1Q4OtMm+lpGwZzJ0M qZOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=W92mOS+7P+rMOkaT6iQmGddNhUN1MdLvuvbtrL+Q8VA=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=jdM0x6fASGYH7FONufWvMHc4ChlKsmtFSvNhsA9AiMKjnts1PPERkCyxpgwdgeXmdY trRUtEOl7lUhQArWhs4TFSpPao8tCLnFKY3XtZ1Lu0SgjOmIDZtkAC0c95jtlKBA8w7o BrG17yw92Yxk3PvTFUVBx1gFSGBLILEzT4wTy+RxXkN77jEQWEa2kTRG4e1R1Pa/0zSs ZS42XlU/I8EzQIBCHW4sY6q2nDaYGpg+YXRZ6XFtoZGu3zMvfWRh7c9ifq+39RK2lI+a G14fTN5xRHoq+y+qrM+mdEhS/OS/sLArceEmN0yReyQ4KgbD0CbBcpbbhBw2uGyrjQDL v1Kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=W1G5PHS5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id x20-20020a17090aca1400b0028534976bf4si2669228pjt.63.2023.11.21.04.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:52:23 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=W1G5PHS5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 6409F802F263; Tue, 21 Nov 2023 04:51:22 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233760AbjKUMvP (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233698AbjKUMvA (ORCPT ); Tue, 21 Nov 2023 07:51:00 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90074D49; Tue, 21 Nov 2023 04:50:55 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 896F06607324; Tue, 21 Nov 2023 12:50:53 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571054; bh=bxh5Gx+Fb0RV/Yt4vunB8wvLU6bWVnKSjAMj8DBawUs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W1G5PHS55UWSBxIpMg2wN7v/VDKnw26FRDP6qccyw8ydlv484574Z5i49D0swYLZy CzG116ZqowhHxMySIFa57KSls9jfXSnuXEmO7VicWA8+DhLe1ROL+4GSinNAyh2Dmd 3SSFw+8+wk6RfTrAduNu7t+jNSiOdGMOv161+Wr6EzZki14fJHpXU01TDAJozbLZtZ LldiWwg+KfqM7Clq5BcFQAPM1nIiFB9FBH861PUYXz1i8/AFfDeK3TAnFdrOT1Pab5 Mou1iEFrQnrSobBm7nK8Vd9o0eQscZCPM0RFA9Rfw+RY//zPtrELNPjudSdxh3nv+f W3GWYtrjQcWIA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 03/20] soc: mediatek: mtk-svs: Convert sw_id and type to enumerations Date: Tue, 21 Nov 2023 13:50:27 +0100 Message-ID: <20231121125044.78642-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:51:22 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178087309212723 X-GMAIL-MSGID: 1783178087309212723 The sw_id and type specifiers currently are defined as BIT(x) for unknown reasons: nothing in this code makes any AND/OR check for those, and that would never happen anyway because both sw_id and type are exclusive, as in: - There will never be a bank that is for both CPU and GPU, or for CPU and CCI together; - A bank cannot be contemporarily of one-line and two-line type, as much as it cannot contemporarily have both HIGH and LOW roles Change those definitions to enumerations and also add some kerneldoc to better describe what they are for and what they indicate. While at it, also change the names adding _SWID or _TYPE to increase human readability. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 192 ++++++++++++++++++--------------- 1 file changed, 106 insertions(+), 86 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 416e9b313c0a..ddbb9ba3e47d 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -32,16 +32,6 @@ #include #include -/* svs bank 1-line software id */ -#define SVSB_CPU_LITTLE BIT(0) -#define SVSB_CPU_BIG BIT(1) -#define SVSB_CCI BIT(2) -#define SVSB_GPU BIT(3) - -/* svs bank 2-line type */ -#define SVSB_LOW BIT(8) -#define SVSB_HIGH BIT(9) - /* svs bank mode support */ #define SVSB_MODE_ALL_DISABLE 0 #define SVSB_MODE_INIT01 BIT(1) @@ -174,6 +164,36 @@ static DEFINE_SPINLOCK(svs_lock); #define svs_dentry_data(name) {__stringify(name), &svs_##name##_debug_fops} #endif +/** + * enum svsb_sw_id - SVS Bank Software ID + * @SVSB_SWID_CPU_LITTLE: CPU little cluster Bank + * @SVSB_SWID_CPU_BIG: CPU big cluster Bank + * @SVSB_SWID_CCI: Cache Coherent Interconnect Bank + * @SVSB_SWID_GPU: GPU Bank + * @SVSB_SWID_MAX: Total number of Banks + */ +enum svsb_sw_id { + SVSB_SWID_CPU_LITTLE, + SVSB_SWID_CPU_BIG, + SVSB_SWID_CCI, + SVSB_SWID_GPU, + SVSB_SWID_MAX +}; + +/** + * enum svsb_type - SVS Bank 2-line: Type and Role + * @SVSB_TYPE_NONE: One-line type Bank - Global role + * @SVSB_TYPE_LOW: Two-line type Bank - Low bank role + * @SVSB_TYPE_HIGH: Two-line type Bank - High bank role + * @SVSB_TYPE_MAX: Total number of bank types + */ +enum svsb_type { + SVSB_TYPE_NONE, + SVSB_TYPE_LOW, + SVSB_TYPE_HIGH, + SVSB_TYPE_MAX +}; + /** * enum svsb_phase - svs bank phase enumeration * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition @@ -549,10 +569,10 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) * 2-line bank updates its corresponding opp volts. * 1-line bank updates all opp volts. */ - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { opp_start = 0; opp_stop = svsb->turn_pt; - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { opp_start = svsb->turn_pt; opp_stop = svsb->opp_count; } else { @@ -576,8 +596,8 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) temp_voffset += svsb->tzone_ltemp_voffset; /* 2-line bank update all opp volts when running mon mode */ - if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_HIGH || - svsb->type == SVSB_LOW)) { + if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_TYPE_HIGH || + svsb->type == SVSB_TYPE_LOW)) { opp_start = 0; opp_stop = svsb->opp_count; } @@ -881,7 +901,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) /* Target is to set svsb->volt[] by algorithm */ if (turn_pt < middle_index) { - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { /* volt[0] ~ volt[turn_pt - 1] */ for (i = 0; i < turn_pt; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); @@ -890,7 +910,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); shift_byte++; } - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ j = svsb->opp_count - 7; svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); @@ -912,7 +932,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) svsb->freq_pct[i]); } } else { - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ j = turn_pt - 7; svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); @@ -932,7 +952,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) svsb->volt[0], svsb->volt[j], svsb->freq_pct[i]); - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { /* volt[turn_pt] ~ volt[opp_count - 1] */ for (i = turn_pt; i < svsb->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); @@ -944,10 +964,10 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) } } - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { opp_start = 0; opp_stop = svsb->turn_pt; - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { opp_start = svsb->turn_pt; opp_stop = svsb->opp_count; } @@ -998,11 +1018,11 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) /* Target is to fill out freq_pct74 / freq_pct30 by algorithm */ if (turn_pt < middle_index) { - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { /* * If we don't handle this situation, - * SVSB_HIGH's FREQPCT74 / FREQPCT30 would keep "0" - * and this leads SVSB_LOW to work abnormally. + * SVSB_TYPE_HIGH's FREQPCT74 / FREQPCT30 would keep "0" + * and this leads SVSB_TYPE_LOW to work abnormally. */ if (turn_pt == 0) freq_pct30 = svsb->freq_pct[0]; @@ -1015,7 +1035,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) *freq_pct |= (svsb->freq_pct[i] << b_sft); shift_byte++; } - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { /* * freq_pct[turn_pt] + * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] @@ -1032,7 +1052,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) } } } else { - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { /* * freq_pct[0] + * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] @@ -1047,7 +1067,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) *freq_pct |= (svsb->freq_pct[i] << b_sft); shift_byte++; } - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ for (i = turn_pt; i < svsb->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); @@ -1550,7 +1570,7 @@ static int svs_init02(struct svs_platform *svsp) if (!(svsb->mode_support & SVSB_MODE_INIT02)) continue; - if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { + if (svsb->type == SVSB_TYPE_HIGH || svsb->type == SVSB_TYPE_LOW) { if (svs_sync_bank_volts_from_opp(svsb)) { dev_err(svsb->dev, "sync volt fail\n"); ret = -EPERM; @@ -1677,19 +1697,19 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) svsb = &svsp->banks[idx]; switch (svsb->sw_id) { - case SVSB_CPU_LITTLE: + case SVSB_SWID_CPU_LITTLE: svsb->name = "SVSB_CPU_LITTLE"; break; - case SVSB_CPU_BIG: + case SVSB_SWID_CPU_BIG: svsb->name = "SVSB_CPU_BIG"; break; - case SVSB_CCI: + case SVSB_SWID_CCI: svsb->name = "SVSB_CCI"; break; - case SVSB_GPU: - if (svsb->type == SVSB_HIGH) + case SVSB_SWID_GPU: + if (svsb->type == SVSB_TYPE_HIGH) svsb->name = "SVSB_GPU_HIGH"; - else if (svsb->type == SVSB_LOW) + else if (svsb->type == SVSB_TYPE_LOW) svsb->name = "SVSB_GPU_LOW"; else svsb->name = "SVSB_GPU"; @@ -1821,13 +1841,13 @@ static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) if (ft_pgm == 0) svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; - if (svsb->type == SVSB_LOW) { + if (svsb->type == SVSB_TYPE_LOW) { svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); - } else if (svsb->type == SVSB_HIGH) { + } else if (svsb->type == SVSB_TYPE_HIGH) { svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); @@ -1886,13 +1906,13 @@ static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) if (vmin == 0x1) svsb->vmin = 0x1e; - if (svsb->type == SVSB_LOW) { + if (svsb->type == SVSB_TYPE_LOW) { svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0); - } else if (svsb->type == SVSB_HIGH) { + } else if (svsb->type == SVSB_TYPE_HIGH) { svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); @@ -1946,13 +1966,13 @@ static bool svs_mt8188_efuse_parsing(struct svs_platform *svsp) for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; - if (svsb->type == SVSB_LOW) { + if (svsb->type == SVSB_TYPE_LOW) { svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); - } else if (svsb->type == SVSB_HIGH) { + } else if (svsb->type == SVSB_TYPE_HIGH) { svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); @@ -2007,14 +2027,14 @@ static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) svsb = &svsp->banks[idx]; switch (svsb->sw_id) { - case SVSB_CPU_BIG: - if (svsb->type == SVSB_HIGH) { + case SVSB_SWID_CPU_BIG: + if (svsb->type == SVSB_TYPE_HIGH) { svsb->mdes = (svsp->efuse[2] >> 24) & GENMASK(7, 0); svsb->bdes = (svsp->efuse[2] >> 16) & GENMASK(7, 0); svsb->mtdes = svsp->efuse[2] & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[13] >> 8) & GENMASK(7, 0); svsb->dcbdet = svsp->efuse[13] & GENMASK(7, 0); - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { svsb->mdes = (svsp->efuse[3] >> 24) & GENMASK(7, 0); svsb->bdes = (svsp->efuse[3] >> 16) & GENMASK(7, 0); svsb->mtdes = svsp->efuse[3] & GENMASK(7, 0); @@ -2022,21 +2042,21 @@ static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) svsb->dcbdet = (svsp->efuse[14] >> 16) & GENMASK(7, 0); } break; - case SVSB_CPU_LITTLE: + case SVSB_SWID_CPU_LITTLE: svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0); svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0); break; - case SVSB_CCI: + case SVSB_SWID_CCI: svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); break; - case SVSB_GPU: + case SVSB_SWID_GPU: svsb->mdes = (svsp->efuse[6] >> 24) & GENMASK(7, 0); svsb->bdes = (svsp->efuse[6] >> 16) & GENMASK(7, 0); svsb->mtdes = svsp->efuse[6] & GENMASK(7, 0); @@ -2098,7 +2118,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; switch (svsb->sw_id) { - case SVSB_CPU_LITTLE: + case SVSB_SWID_CPU_LITTLE: svsb->bdes = svsp->efuse[16] & GENMASK(7, 0); svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0); @@ -2110,7 +2130,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) else svsb->volt_od += 2; break; - case SVSB_CPU_BIG: + case SVSB_SWID_CPU_BIG: svsb->bdes = svsp->efuse[18] & GENMASK(7, 0); svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0); @@ -2122,7 +2142,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) else svsb->volt_od += 12; break; - case SVSB_CCI: + case SVSB_SWID_CCI: svsb->bdes = svsp->efuse[4] & GENMASK(7, 0); svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0); @@ -2134,7 +2154,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) else svsb->volt_od += 2; break; - case SVSB_GPU: + case SVSB_SWID_GPU: svsb->bdes = svsp->efuse[6] & GENMASK(7, 0); svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0); @@ -2219,16 +2239,16 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) svsb->mts = mts; switch (svsb->sw_id) { - case SVSB_CPU_LITTLE: + case SVSB_SWID_CPU_LITTLE: tb_roomt = x_roomt[3]; break; - case SVSB_CPU_BIG: + case SVSB_SWID_CPU_BIG: tb_roomt = x_roomt[4]; break; - case SVSB_CCI: + case SVSB_SWID_CCI: tb_roomt = x_roomt[3]; break; - case SVSB_GPU: + case SVSB_SWID_GPU: tb_roomt = x_roomt[1]; break; default: @@ -2321,9 +2341,9 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; - if (svsb->type == SVSB_HIGH) + if (svsb->type == SVSB_TYPE_HIGH) svsb->opp_dev = svs_add_device_link(svsp, "gpu"); - else if (svsb->type == SVSB_LOW) + else if (svsb->type == SVSB_TYPE_LOW) svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); if (IS_ERR(svsb->opp_dev)) @@ -2355,14 +2375,14 @@ static int svs_mt8186_platform_probe(struct svs_platform *svsp) svsb = &svsp->banks[idx]; switch (svsb->sw_id) { - case SVSB_CPU_LITTLE: - case SVSB_CPU_BIG: + case SVSB_SWID_CPU_LITTLE: + case SVSB_SWID_CPU_BIG: svsb->opp_dev = get_cpu_device(svsb->cpu_id); break; - case SVSB_CCI: + case SVSB_SWID_CCI: svsb->opp_dev = svs_add_device_link(svsp, "cci"); break; - case SVSB_GPU: + case SVSB_SWID_GPU: svsb->opp_dev = svs_add_device_link(svsp, "gpu"); break; default: @@ -2394,14 +2414,14 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) svsb = &svsp->banks[idx]; switch (svsb->sw_id) { - case SVSB_CPU_LITTLE: - case SVSB_CPU_BIG: + case SVSB_SWID_CPU_LITTLE: + case SVSB_SWID_CPU_BIG: svsb->opp_dev = get_cpu_device(svsb->cpu_id); break; - case SVSB_CCI: + case SVSB_SWID_CCI: svsb->opp_dev = svs_add_device_link(svsp, "cci"); break; - case SVSB_GPU: + case SVSB_SWID_GPU: svsb->opp_dev = svs_add_device_link(svsp, "gpu"); break; default: @@ -2420,8 +2440,8 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) static struct svs_bank svs_mt8195_banks[] = { { - .sw_id = SVSB_GPU, - .type = SVSB_LOW, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, @@ -2443,8 +2463,8 @@ static struct svs_bank svs_mt8195_banks[] = { .ctl0 = 0x00540003, }, { - .sw_id = SVSB_GPU, - .type = SVSB_HIGH, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .tzone_name = "gpu1", @@ -2475,8 +2495,8 @@ static struct svs_bank svs_mt8195_banks[] = { static struct svs_bank svs_mt8192_banks[] = { { - .sw_id = SVSB_GPU, - .type = SVSB_LOW, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .tzone_name = "gpu1", @@ -2503,8 +2523,8 @@ static struct svs_bank svs_mt8192_banks[] = { .tzone_ltemp_voffset = 7, }, { - .sw_id = SVSB_GPU, - .type = SVSB_HIGH, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .tzone_name = "gpu1", @@ -2535,8 +2555,8 @@ static struct svs_bank svs_mt8192_banks[] = { static struct svs_bank svs_mt8188_banks[] = { { - .sw_id = SVSB_GPU, - .type = SVSB_LOW, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, @@ -2558,8 +2578,8 @@ static struct svs_bank svs_mt8188_banks[] = { .ctl0 = 0x00100003, }, { - .sw_id = SVSB_GPU, - .type = SVSB_HIGH, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .tzone_name = "gpu1", @@ -2590,8 +2610,8 @@ static struct svs_bank svs_mt8188_banks[] = { static struct svs_bank svs_mt8186_banks[] = { { - .sw_id = SVSB_CPU_BIG, - .type = SVSB_LOW, + .sw_id = SVSB_SWID_CPU_BIG, + .type = SVSB_TYPE_LOW, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .cpu_id = 6, @@ -2615,8 +2635,8 @@ static struct svs_bank svs_mt8186_banks[] = { .ctl0 = 0x00540003, }, { - .sw_id = SVSB_CPU_BIG, - .type = SVSB_HIGH, + .sw_id = SVSB_SWID_CPU_BIG, + .type = SVSB_TYPE_HIGH, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .cpu_id = 6, @@ -2646,7 +2666,7 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_ltemp_voffset = 8, }, { - .sw_id = SVSB_CPU_LITTLE, + .sw_id = SVSB_SWID_CPU_LITTLE, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .cpu_id = 0, @@ -2675,7 +2695,7 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_ltemp_voffset = 8, }, { - .sw_id = SVSB_CCI, + .sw_id = SVSB_SWID_CCI, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .tzone_name = "cpu_zone0", @@ -2703,7 +2723,7 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_ltemp_voffset = 8, }, { - .sw_id = SVSB_GPU, + .sw_id = SVSB_SWID_GPU, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .tzone_name = "mfg", @@ -2733,7 +2753,7 @@ static struct svs_bank svs_mt8186_banks[] = { static struct svs_bank svs_mt8183_banks[] = { { - .sw_id = SVSB_CPU_LITTLE, + .sw_id = SVSB_SWID_CPU_LITTLE, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .cpu_id = 0, @@ -2757,7 +2777,7 @@ static struct svs_bank svs_mt8183_banks[] = { .ctl0 = 0x00010001, }, { - .sw_id = SVSB_CPU_BIG, + .sw_id = SVSB_SWID_CPU_BIG, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .cpu_id = 4, @@ -2781,7 +2801,7 @@ static struct svs_bank svs_mt8183_banks[] = { .ctl0 = 0x00000001, }, { - .sw_id = SVSB_CCI, + .sw_id = SVSB_SWID_CCI, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .buck_name = "proc", @@ -2804,7 +2824,7 @@ static struct svs_bank svs_mt8183_banks[] = { .ctl0 = 0x00100003, }, { - .sw_id = SVSB_GPU, + .sw_id = SVSB_SWID_GPU, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .buck_name = "mali", From patchwork Tue Nov 21 12:50:28 2023 Content-Type: text/plain; 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[2620:137:e000::3:5]) by mx.google.com with ESMTPS id f14-20020a170902ce8e00b001c88fc3c5a1si10455733plg.461.2023.11.21.04.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:51:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=Yv0OHqe3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id D99DF80BB235; Tue, 21 Nov 2023 04:51:11 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233692AbjKUMvG (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233677AbjKUMvA (ORCPT ); Tue, 21 Nov 2023 07:51:00 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93A9FD4C; Tue, 21 Nov 2023 04:50:56 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 94BD06607326; Tue, 21 Nov 2023 12:50:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571055; bh=lCOeXkBHj3GxnYKp57VPx13B7VONqu2PAmr9JmQp0B4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Yv0OHqe3h18r1zmGVQetpCWNuOGV4AbsKQgSqehbRcDSaquDriwv3fEBqyZMxPlpc tKk8CjyNL4W6tD0ICswVUKPY6TDAAeB9gtDOousKgRGy9QCcDNhhnG3cNZXkDQWRdG 6Py/cqnSbBGi3A2HrXzx1KK6BeFwT7kg/S0op2CCVY0MK5QB0aiut0UYlyUYnnW6OJ 4+YXLhCUP5W+ZZFzBZZdvcZEYgCdKsh+J+zLs0YhpI0KFb7eamAeo4djfypommMb2O bFqgbFic5h7MKU2XixuHq3ftmTFPuROcHGU/cpPn4Mbby03t71yiac1Zy6Xor0DV5n yhOPYNvrcqCEQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 04/20] soc: mediatek: mtk-svs: Build bank name string dynamically Date: Tue, 21 Nov 2023 13:50:28 +0100 Message-ID: <20231121125044.78642-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:51:12 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178031369710444 X-GMAIL-MSGID: 1783178031369710444 In svs_bank_resource_setup() there is a "big" switch assigning different names depending on sw_id and type and this will surely grow: for example MT8186 has got a two-line type (high/low) SVS bank for CPU_BIG, and this would require more switch nesting. Simplify all of this by changing that to a devm_kasprintf() call that will concatenate the SW_ID string (e.g. SVSB_CPU_LITTLE) with the Type string (e.g. _LOW), resulting in the expected full bank name (e.g. SVSB_CPU_LITTLE_LOW). This being a dynamic allocation can be slower, but this happens only once in the life of this driver and it's not a performance path, so it's totally acceptable. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 39 +++++++++++++++------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index ddbb9ba3e47d..1c7592fd6ae7 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -332,6 +332,14 @@ static const u32 svs_regs_v2[] = { [THSLPEVEB] = 0x330, }; +static const char * const svs_swid_names[SVSB_SWID_MAX] = { + "SVSB_CPU_LITTLE", "SVSB_CPU_BIG", "SVSB_CCI", "SVSB_GPU" +}; + +static const char * const svs_type_names[SVSB_TYPE_MAX] = { + "", "_LOW", "_HIGH" +}; + /** * struct svs_platform - svs platform control * @base: svs platform register base @@ -1696,34 +1704,21 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; - switch (svsb->sw_id) { - case SVSB_SWID_CPU_LITTLE: - svsb->name = "SVSB_CPU_LITTLE"; - break; - case SVSB_SWID_CPU_BIG: - svsb->name = "SVSB_CPU_BIG"; - break; - case SVSB_SWID_CCI: - svsb->name = "SVSB_CCI"; - break; - case SVSB_SWID_GPU: - if (svsb->type == SVSB_TYPE_HIGH) - svsb->name = "SVSB_GPU_HIGH"; - else if (svsb->type == SVSB_TYPE_LOW) - svsb->name = "SVSB_GPU_LOW"; - else - svsb->name = "SVSB_GPU"; - break; - default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + if (svsb->sw_id >= SVSB_SWID_MAX || svsb->type >= SVSB_TYPE_MAX) { + dev_err(svsb->dev, "unknown bank sw_id or type\n"); return -EINVAL; } - svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), - GFP_KERNEL); + svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), GFP_KERNEL); if (!svsb->dev) return -ENOMEM; + svsb->name = devm_kasprintf(svsp->dev, GFP_KERNEL, "%s%s", + svs_swid_names[svsb->sw_id], + svs_type_names[svsb->type]); + if (!svsb->name) + return -ENOMEM; + ret = dev_set_name(svsb->dev, "%s", svsb->name); if (ret) return ret; From patchwork Tue Nov 21 12:50:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167730 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp595917vqb; Tue, 21 Nov 2023 04:54:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IEUUYHMsrew2tuVjuibSEssu7q+eAtiXM+8ZKmaNGVChUiGvjy1sAVCafMQsmWzdYoGeB2L X-Received: by 2002:a05:6a21:78a2:b0:187:758e:9781 with SMTP id bf34-20020a056a2178a200b00187758e9781mr3625200pzc.17.1700571285407; Tue, 21 Nov 2023 04:54:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571285; cv=none; d=google.com; s=arc-20160816; b=g6C+KiCRaF7a4qt45evYwQ/VMrTfNvrJLKjaTLezFrSRBbUqZT8kF/V3Dv/NhRwpFX heQW72LPdneY6tM8jGRWlYWVtB8Ue52jU4W09gf+xknI7H0KdG+k4jMT9bOf9OktP984 2/QIVhwrsZ5Lp+t5v1HUpx/hcJtaHJ36VYX5SMyymySkeP7MQNs0zmN2iIv+JTuv5Y5o woi/iZUO3OityfMTDDCbUrLHrvN4jumpUeQ58dVtmzOwLxxmCCLhNbgQuhvSYruf5frG MQecJEkNTkKyfM53iqcg7Xd0PvuKdbIc0kXC+uepZSC7ZBqpLjvdzAVgyr9FjFHiTkVu YWzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sq9G32K6TtoLD+AvzTy4qXTHDqDo8A0lDQFf/DMBYSM=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=iAxU4/34RlUmG2kD3VucOH6VdiMMv3YyGL82r2I57OHkYHzdiBw/UQDS/PpRzXe+Fi eoV1pilw3nFQGG3O3rqTLZaVBIhZIQ0Aa4G6+bnJvTIF6pH/XQjkOxprdRbXvOH9wIkQ NIOHVGop3/PcfAeNENfwHO7Gzht7Vf2YvA0oA2jhcSa76jYoxaWX16WiqIxaB+iCnonu N7SwTdM9eozJT80bhVXqbjAQd5GBx3KkfkzDw/mucRF9SznXGkcjhYmfH7QMOywXkXy5 vHB7kRFT36MexDR9OjJDtxU0pxP0Lee0krT6OMPSbv6el6Fvl7VZnJWB21tEi/zLKNEs bvdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=asVihs0l; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id e36-20020a631e24000000b005b8ebaa2937si10494082pge.47.2023.11.21.04.54.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:54:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=asVihs0l; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 959A880A0557; Tue, 21 Nov 2023 04:51:28 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233822AbjKUMvJ (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233706AbjKUMvB (ORCPT ); Tue, 21 Nov 2023 07:51:01 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 986B0D40; Tue, 21 Nov 2023 04:50:57 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A17FD6607314; Tue, 21 Nov 2023 12:50:55 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571056; bh=HjqA+sAHeyELuvvhdsMlpINGaociXjYFjdm6q68a7V8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=asVihs0lKspnKojWxFlpYVRcUfG+duWidqbA5ziqx7fNXdoUpGLD1p71fUVyfL05f 5ySn/H+mo/46WeUGKUUcWGhoXN/JRFx7R9ic0F4ZKbYPneAkspQrY95jGjTaWHjxG6 2wYinIfHnmyLyq6WfYZqOy+GElxIx28jdM4rwBj+R6QEFck1tcEz3IKTQ8iFTZP2DS fS++It+Ta+hpLXJ5XYQ/L+HO9pxh9W1HQnHPPz2+mbCKrDV5kd58JwJINPLivS3yvK q/6+jYCq98uVkjOEfzsGsT5Pny+Q7zA3OF8xeTrc7B6Il4GgBM0yA27Mfeq9UEAeL8 eTWfIS7kLp6cA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 05/20] soc: mediatek: mtk-svs: Reduce memory footprint of struct svs_bank Date: Tue, 21 Nov 2023 13:50:29 +0100 Message-ID: <20231121125044.78642-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:51:28 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178236171773631 X-GMAIL-MSGID: 1783178236171773631 Many 32-bit members of this struct can be size reduced to either 16-bit or even 8-bit, for a total saving of ~61 bytes per bank. Keeping in mind that one SoC declares at least two banks, this brings a minimum of ~122 bytes saving (depending on compiler optimization). Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 51 +++++++++++++++++----------------- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 1c7592fd6ae7..6c27fb523bfa 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -456,13 +456,13 @@ struct svs_bank { char *buck_name; char *tzone_name; enum svsb_phase phase; - s32 volt_od; + short int volt_od; u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX]; u32 pm_runtime_enabled_count; - u32 mode_support; + u8 mode_support; u32 freq_base; u32 turn_freq_base; - u32 vboot; + u8 vboot; u32 opp_dfreq[MAX_OPP_ENTRIES]; u32 opp_dvolt[MAX_OPP_ENTRIES]; u32 freq_pct[MAX_OPP_ENTRIES]; @@ -470,36 +470,36 @@ struct svs_bank { u32 volt_step; u32 volt_base; u32 volt_flags; - u32 vmax; - u32 vmin; + u8 vmax; + u8 vmin; u32 age_config; - u32 age_voffset_in; + u16 age_voffset_in; u32 dc_config; - u32 dc_voffset_in; - u32 dvt_fixed; - u32 vco; - u32 chk_shift; + u16 dc_voffset_in; + u8 dvt_fixed; + u8 vco; + u8 chk_shift; u32 core_sel; - u32 opp_count; + u8 opp_count; u32 int_st; - u32 sw_id; - u32 cpu_id; + u8 sw_id; + u8 cpu_id; u32 ctl0; u32 temp; u32 tzone_htemp; - u32 tzone_htemp_voffset; + u16 tzone_htemp_voffset; u32 tzone_ltemp; - u32 tzone_ltemp_voffset; - u32 bts; - u32 mts; - u32 bdes; - u32 mdes; - u32 mtdes; - u32 dcbdet; - u32 dcmdet; + u16 tzone_ltemp_voffset; + u16 bts; + u16 mts; + u16 bdes; + u16 mdes; + u8 mtdes; + u8 dcbdet; + u8 dcmdet; u32 turn_pt; u32 vbin_turn_pt; - u32 type; + u8 type; }; static u32 percent(u32 numerator, u32 denominator) @@ -1267,6 +1267,7 @@ static inline void svs_error_isr_handler(struct svs_platform *svsp) static inline void svs_init01_isr_handler(struct svs_platform *svsp) { struct svs_bank *svsb = svsp->pbank; + u32 val; dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", __func__, svs_readl_relaxed(svsp, VDESIGN74), @@ -1276,8 +1277,8 @@ static inline void svs_init01_isr_handler(struct svs_platform *svsp) svs_save_bank_register_data(svsp, SVSB_PHASE_INIT01); svsb->phase = SVSB_PHASE_INIT01; - svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) & - GENMASK(15, 0)) + 1; + val = ~(svs_readl_relaxed(svsp, DCVALUES) & GENMASK(15, 0)) + 1; + svsb->dc_voffset_in = val & GENMASK(15, 0); if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE || (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT && svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY)) From patchwork Tue Nov 21 12:50:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167727 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp594799vqb; Tue, 21 Nov 2023 04:52:27 -0800 (PST) X-Google-Smtp-Source: AGHT+IGxlGYENqY4R/X8XGpCo+271ocX1ruHfwfw9/6W0HgS2agDiZVVAWKNNuA7MuqqU/oPDkto X-Received: by 2002:a05:6808:ecd:b0:3b2:e761:fadd with SMTP id q13-20020a0568080ecd00b003b2e761faddmr13085048oiv.16.1700571146770; Tue, 21 Nov 2023 04:52:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571146; cv=none; d=google.com; s=arc-20160816; b=ByAKv6arVlLF+wOlgZlgNCDXzarONEYvo/uZ3Cpp+dq76XMLj6/ai/A7G34Y/tD/+A dW31dIbJV4edqo+YTqA0kiEn6Z72vbAkuIqht0m0rDSCJu+qgdiGCpG+Wj8yDFM5bewv NrI1w2vnCByqPMFJ0RPBpGZ8MXGiZL2fDdTUpUqHQVg8D7p/ck7PM9SM8+T7ZSNvL8F6 tmqOAAWr73vjpnH1jL+K/oMKPGdLg4rkcafIc/XjB2bKEILeG3WnXeNu3g+vJUdkWsPt zzc9FIM2siCdx45w2aRBWBeTEwG949HwA/RYuI5TIUedOxWGgppgXTq3yjevqul1Jfsh hyOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=G4CiWflMa0UUyp9NbGyD/T0A000MhIAnhks0L2DnG2Q=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=vxYyPrTd4uzlo3+PtODzTczYryPveMYbkZUFWjCo+wnC5NZu+BGYxQmYTT0SLBs8RE iBkSfjiD0d0Mpn+qLiTwRiLBuLzgGSHNbWv6PIIbbpu6Io7hoeGXhxEFilrrWwiZpdhQ 7TF19MbNk7k4gBGEFjYuEOnukrRxKjlgZB94P/uyhZ/Ao2QhmRopfvOdfbbDN+cZXONb TNVODUPiVE/K8MVC4G9meUzD+dCj8Cslkv0aoOqJnsGmew3ZO8HIE0POF7elm4ctXDHk v/M/zDnOYreM2XYLyMHxD4MWCS+vbX+i4YrkfazfWjAUhc8vqf5uesm+6WlK/udYRoLC hRSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=DBpzUERp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id bv132-20020a632e8a000000b005bd68976351si10006232pgb.55.2023.11.21.04.52.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:52:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=DBpzUERp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 1307C8027B24; Tue, 21 Nov 2023 04:52:11 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233837AbjKUMvM (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233709AbjKUMvC (ORCPT ); Tue, 21 Nov 2023 07:51:02 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAF9BD52; Tue, 21 Nov 2023 04:50:58 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id AB37F660731B; Tue, 21 Nov 2023 12:50:56 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571057; bh=rbMxFG/9Z/MvXIMSXdH+Z5ELUWvpXJ2G/c2LivRCtOk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DBpzUERpnXVxQTq62hizv4R8fVPbIUHQHcCLwXPwO6zzL2zGsXcb12DLbdmJUVFq1 ICTMNG8y4zzELKcVCaY3i0hTea/M301YmHNuOUmnpQ2pz4pWxQcUguqsJNusCGUBd7 oaV26QCH0nOlmXt5watgiE+y+quzHg6fcxah8oQ0qXb/q+/z14H18mRpCbob4ZDg+I yW2hH7epRTbxUOALclfGyTF/iYDR3Qp+vKjonIYo7SbHxlrtpd1omapjnm4EHLXRvS nhrxLhBGCOgs+wOEn1BJra0d2PvEUPnBbkO7WDN4WGhwxHUG+GVb6jrGY3IQGWnpmy k7/7fvcF4cPYA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 06/20] soc: mediatek: mtk-svs: Change the thermal sensor device name Date: Tue, 21 Nov 2023 13:50:30 +0100 Message-ID: <20231121125044.78642-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:52:11 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178090441511294 X-GMAIL-MSGID: 1783178090441511294 This driver tries to create a device link to the thermal sensor device: change all instances of "lvts" and "thermal" to "thermal-sensor", as that's what the devicetree node name must be. Note for MT8183: As specified in a previous commit, this SoC never got SVS probing, so this is not a breaking change and it does not require fallback for older device trees. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 6c27fb523bfa..b5beb33c95ba 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2329,7 +2329,7 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), "cannot get svs reset control\n"); - dev = svs_add_device_link(svsp, "lvts"); + dev = svs_add_device_link(svsp, "thermal-sensor"); if (IS_ERR(dev)) return dev_err_probe(svsp->dev, PTR_ERR(dev), "failed to get lvts device\n"); @@ -2362,7 +2362,7 @@ static int svs_mt8186_platform_probe(struct svs_platform *svsp) return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), "cannot get svs reset control\n"); - dev = svs_add_device_link(svsp, "lvts"); + dev = svs_add_device_link(svsp, "thermal-sensor"); if (IS_ERR(dev)) return dev_err_probe(svsp->dev, PTR_ERR(dev), "failed to get lvts device\n"); @@ -2401,7 +2401,7 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) struct svs_bank *svsb; u32 idx; - dev = svs_add_device_link(svsp, "thermal"); + dev = svs_add_device_link(svsp, "thermal-sensor"); if (IS_ERR(dev)) return dev_err_probe(svsp->dev, PTR_ERR(dev), "failed to get thermal device\n"); From patchwork Tue Nov 21 12:50:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167725 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp594521vqb; Tue, 21 Nov 2023 04:51:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IFvTwgFkDvZuaX6NrReldxK6sLpDHA7YQHO86u93ZpPBr2h/Yp0++rMJEQUC0fWAO/y3SNc X-Received: by 2002:a9d:77d7:0:b0:6b8:9483:35ba with SMTP id w23-20020a9d77d7000000b006b8948335bamr11926952otl.24.1700571111213; Tue, 21 Nov 2023 04:51:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571111; cv=none; d=google.com; s=arc-20160816; b=t+Xsm6m0JYPzCo2U7qto2l2CHngo/9k5juan1VBsOxBni4Aro4F9EiP6pFo1/lrBCQ jRAnec+UUv/+t68WCfAPOt72MOdUGMyRf0HEe7nO3frkdpV8iPRoK6KW7V/UIyqeZfzr mP+/NvaS5/aI3SNqC6Ng5GhQB5IzT4eKN5JsaeUNFBcFK5QXLGpIcUDFVsFyYNBqB8Tk 60nUC186Wx/ofyH+D4ZmjmyYEO1Tnk6aGJX7y5kCqmlOyAoiifyY6IxggPUkamEi7IYz dyVjz3M2O8FEspHq9+8IqOMUD9+LcC/jNaqPIv71oW/w+3lPHdErWTRbJxCVu+9piOF5 3PRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dloUf1foTLvmfIU52Wp1Zyxe4yiIJTvKjylKM09rNkQ=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=sD4r2Nwy6eQaYXChqgmdbByF9P9JGfZHR6JHidiy+xB15w0g0gPrntJPrPaTTyc7Aq D2LLXiVXXR+wnfKxxC4waMHCIp/h72YUKBLXsjMhklENnggJ3os4KVXrlNxp+aqekxER 2kXzDCUCO5rj7sab1QzMf6eHxypoGar4uPvcN9tJ83np04vZMoT/DwEPt2bAHovlJzM+ vk5ZssJpmy7kIV6nrBz70fSBes5eO9/U6DnBesVPMkqD2JbwtG8LRj27wW6kuWi3OUj6 qq+irDzg7jFajtV2H91SbsdLZvtrsFmXaz1AK1MaXgO2FwMsH9J+h3Fo/IfQlK3Einv+ IlMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=HAbv1hzT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from lipwig.vger.email (lipwig.vger.email. [23.128.96.33]) by mx.google.com with ESMTPS id b14-20020a631b4e000000b005859c255ce9si10371943pgm.861.2023.11.21.04.51.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:51:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=HAbv1hzT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 4E3FA8027E1B; Tue, 21 Nov 2023 04:51:35 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233815AbjKUMvS (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233710AbjKUMvE (ORCPT ); Tue, 21 Nov 2023 07:51:04 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1BE2D61; Tue, 21 Nov 2023 04:50:59 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B36756607323; Tue, 21 Nov 2023 12:50:57 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571058; bh=y4hC7rjcvzTRTeQC8pyo7KQ1ZhxtsknG+ldiwzI/d40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HAbv1hzT4UIcXOf9Di1WuJ3VsuM8i8WJ5ME55E6HyPtW2VW1cnVrWeW9yrwzYihd6 BdjW5yziYPpACJA4ovJOkTeW78CqLD9efVV5qfvfgIjidYrdceq4CjRlcjKoT0AW2W roia3rjbWJWYFux7/cMAFcRbmsWdYJOdonJpffYROMrwfatdBLesMcTvosAPqUvDBH E4a5MmHBTp8asd/RolLVCpeu4ojlYtN2CmEs5TayLPNdpIzrW5WNRBeTb/ritTNyas WHkbzTbAMl5Fququ+eYeENCNve2C/UFYK15/gnPgMMXQ40rl/36uFrxntMiPZZsuUt xk6C3+H9R05Gg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 07/20] soc: mediatek: mtk-svs: Add a map to retrieve fused values Date: Tue, 21 Nov 2023 13:50:31 +0100 Message-ID: <20231121125044.78642-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:51:35 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178053430638296 X-GMAIL-MSGID: 1783178053430638296 In preparation for adding a common efuse parsing function which will greatly reduce code duplication, add a SoC-specific mapping that will be used to retrieve the right SVS calibration values from the fuses. The maps are two: one is a Global Map used for reading parameters that are SVS-global, and one is a Bank Map for reading calibrations for each SVS Bank. While at it, also populate the map in the platform data for each SoC. Being this a preparation commit, there are no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 87 ++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index b5beb33c95ba..6c6f133c327f 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -340,6 +340,26 @@ static const char * const svs_type_names[SVSB_TYPE_MAX] = { "", "_LOW", "_HIGH" }; +enum svs_fusemap_dev { + BDEV_BDES, + BDEV_MDES, + BDEV_MTDES, + BDEV_DCBDET, + BDEV_DCMDET, + BDEV_MAX +}; + +enum svs_fusemap_glb { + GLB_FT_PGM, + GLB_VMIN, + GLB_MAX +}; + +struct svs_fusemap { + s8 index; + u8 ofst; +}; + /** * struct svs_platform - svs platform control * @base: svs platform register base @@ -375,12 +395,14 @@ struct svs_platform_data { struct svs_bank *banks; bool (*efuse_parsing)(struct svs_platform *svsp); int (*probe)(struct svs_platform *svsp); + const struct svs_fusemap *glb_fuse_map; const u32 *regs; u32 bank_max; }; /** * struct svs_bank - svs bank representation + * @dev_fuse_map: Bank fuse map data * @dev: bank device * @opp_dev: device for opp table/buck control * @init_completion: the timeout completion for bank init @@ -444,6 +466,7 @@ struct svs_platform_data { * opp_volt[i] = (volt[i] * volt_step) + volt_base; */ struct svs_bank { + const struct svs_fusemap *dev_fuse_map; struct device *dev; struct device *opp_dev; struct completion init_completion; @@ -2457,6 +2480,9 @@ static struct svs_bank svs_mt8195_banks[] = { .core_sel = 0x0fff0100, .int_st = BIT(0), .ctl0 = 0x00540003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 10, 16 }, { 10, 24 }, { 10, 0 }, { 8, 0 }, { 8, 8 } + } }, { .sw_id = SVSB_SWID_GPU, @@ -2486,6 +2512,9 @@ static struct svs_bank svs_mt8195_banks[] = { .tzone_htemp_voffset = 0, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 9, 16 }, { 9, 24 }, { 9, 0 }, { 8, 0 }, { 8, 8 } + }, }, }; @@ -2517,6 +2546,9 @@ static struct svs_bank svs_mt8192_banks[] = { .tzone_htemp_voffset = 0, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 10, 16 }, { 10, 24 }, { 10, 0 }, { 17, 0 }, { 17, 8 } + } }, { .sw_id = SVSB_SWID_GPU, @@ -2546,6 +2578,9 @@ static struct svs_bank svs_mt8192_banks[] = { .tzone_htemp_voffset = 0, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 9, 16 }, { 9, 24 }, { 17, 0 }, { 17, 16 }, { 17, 24 } + } }, }; @@ -2572,6 +2607,9 @@ static struct svs_bank svs_mt8188_banks[] = { .core_sel = 0x0fff0000, .int_st = BIT(0), .ctl0 = 0x00100003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } + } }, { .sw_id = SVSB_SWID_GPU, @@ -2601,6 +2639,9 @@ static struct svs_bank svs_mt8188_banks[] = { .tzone_htemp_voffset = 0, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } + } }, }; @@ -2629,6 +2670,9 @@ static struct svs_bank svs_mt8186_banks[] = { .core_sel = 0x0fff0100, .int_st = BIT(0), .ctl0 = 0x00540003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 3, 16 }, { 3, 24 }, { 3, 0 }, { 14, 16 }, { 14, 24 } + } }, { .sw_id = SVSB_SWID_CPU_BIG, @@ -2660,6 +2704,9 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_htemp_voffset = 8, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 2, 16 }, { 2, 24 }, { 2, 0 }, { 13, 0 }, { 13, 8 } + } }, { .sw_id = SVSB_SWID_CPU_LITTLE, @@ -2689,6 +2736,9 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_htemp_voffset = 8, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } + } }, { .sw_id = SVSB_SWID_CCI, @@ -2717,6 +2767,9 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_htemp_voffset = 8, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } + } }, { .sw_id = SVSB_SWID_GPU, @@ -2744,6 +2797,9 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_htemp_voffset = 8, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 6, 16 }, { 6, 24 }, { 6, 0 }, { 15, 8 }, { 15, 0 } + } }, }; @@ -2771,6 +2827,9 @@ static struct svs_bank svs_mt8183_banks[] = { .core_sel = 0x8fff0000, .int_st = BIT(0), .ctl0 = 0x00010001, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 16, 0 }, { 16, 8 }, { 17, 16 }, { 16, 16 }, { 16, 24 } + } }, { .sw_id = SVSB_SWID_CPU_BIG, @@ -2795,6 +2854,9 @@ static struct svs_bank svs_mt8183_banks[] = { .core_sel = 0x8fff0001, .int_st = BIT(1), .ctl0 = 0x00000001, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 18, 0 }, { 18, 8 }, { 17, 0 }, { 18, 16 }, { 18, 24 } + } }, { .sw_id = SVSB_SWID_CCI, @@ -2818,6 +2880,9 @@ static struct svs_bank svs_mt8183_banks[] = { .core_sel = 0x8fff0002, .int_st = BIT(2), .ctl0 = 0x00100003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 0 }, { 4, 8 }, { 5, 16 }, { 4, 16 }, { 4, 24 } + } }, { .sw_id = SVSB_SWID_GPU, @@ -2848,6 +2913,9 @@ static struct svs_bank svs_mt8183_banks[] = { .tzone_htemp_voffset = 0, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 3, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 6, 0 }, { 6, 8 }, { 5, 0 }, { 6, 16 }, { 6, 24 } + } }, }; @@ -2858,6 +2926,9 @@ static const struct svs_platform_data svs_mt8195_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8195_banks), + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { + { 0, 0 }, { 19, 4 } + } }; static const struct svs_platform_data svs_mt8192_platform_data = { @@ -2867,6 +2938,10 @@ static const struct svs_platform_data svs_mt8192_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8192_banks), + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { + /* FT_PGM not present */ + { -1, 0 }, { 19, 4 } + } }; static const struct svs_platform_data svs_mt8188_platform_data = { @@ -2876,6 +2951,10 @@ static const struct svs_platform_data svs_mt8188_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8188_banks), + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { + /* FT_PGM and VMIN not present */ + { -1, 0 }, { -1, 0 } + } }; static const struct svs_platform_data svs_mt8186_platform_data = { @@ -2885,6 +2964,10 @@ static const struct svs_platform_data svs_mt8186_platform_data = { .probe = svs_mt8186_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8186_banks), + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { + /* FT_PGM and VMIN not present */ + { -1, 0 }, { -1, 0 } + } }; static const struct svs_platform_data svs_mt8183_platform_data = { @@ -2894,6 +2977,10 @@ static const struct svs_platform_data svs_mt8183_platform_data = { .probe = svs_mt8183_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8183_banks), + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { + /* VMIN not present */ + { 0, 4 }, { -1, 0 } + } }; static const struct of_device_id svs_of_match[] = { From patchwork Tue Nov 21 12:50:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167731 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp595940vqb; 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[23.128.96.37]) by mx.google.com with ESMTPS id s138-20020a632c90000000b005c1faa82c06si9742795pgs.470.2023.11.21.04.54.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:54:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=Dy8nGXWd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 9C58080775B1; Tue, 21 Nov 2023 04:51:38 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233859AbjKUMvW (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233752AbjKUMvE (ORCPT ); Tue, 21 Nov 2023 07:51:04 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27B53D69; Tue, 21 Nov 2023 04:51:00 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id BA65B6607319; Tue, 21 Nov 2023 12:50:58 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571059; bh=n+I9YOPDM99MnwpUCp/Jyp5QiCWQ9S9IzP9LXdnM4XE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dy8nGXWdvPSsM5zqAHNWXFtkPY/CD+8TDJ2WuIQR9lA0ZWOv00MoLYVOgZz0vsC9u VE10qlW9gQereyffjew/gDsiCsH8lmSZSA7aAdVWf0PbEPr+C8Bwjeo0cRNIhWAJr7 r0JsNv9fC1IBlvvR+Fm9jW8/p2yRO9GnNMuAP4xI+ROp68uKwjvzR+XL358m7Sbfxz bJg9u7ozDj7Nyeli27vVe74BouUZmuKGK672lWp8sUSCNkGehPMDoFtPRETcm3jHL0 pcuEuerVqQCbLbwVP3EDPn5Cb5nDTOjRgF5z7GmGQwNWa2yqvqtM1tXav4pcbZd4/h qiY11JeHYz2HQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 08/20] soc: mediatek: mtk-svs: Add SVS-Thermal coefficient to SoC platform data Date: Tue, 21 Nov 2023 13:50:32 +0100 Message-ID: <20231121125044.78642-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:51:38 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178239401640561 X-GMAIL-MSGID: 1783178239401640561 In preparation for commonizing the efuse parsing function, add the SVS-Thermal coefficients for all SoCs for which said function can be commonized (MT8186, MT8188, MT8192, MT8195) and assign those to their platform data structure. That will be used to calculate the MTS parameter with the equation MTS = (ts_coeff * 2) / 1000 This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 6c6f133c327f..ab564d48092b 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -118,6 +118,10 @@ #define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16) #define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24) +/* SVS Thermal Coefficients */ +#define SVSB_TS_COEFF_MT8195 250460 +#define SVSB_TS_COEFF_MT8186 204650 + /* svs bank related setting */ #define BITS8 8 #define MAX_OPP_ENTRIES 16 @@ -374,6 +378,7 @@ struct svs_fusemap { * @bank_max: total number of svs banks * @efuse: svs efuse data received from NVMEM framework * @tefuse: thermal efuse data received from NVMEM framework + * @ts_coeff: thermal sensors coefficient */ struct svs_platform { void __iomem *base; @@ -388,6 +393,7 @@ struct svs_platform { u32 bank_max; u32 *efuse; u32 *tefuse; + u32 ts_coeff; }; struct svs_platform_data { @@ -398,6 +404,7 @@ struct svs_platform_data { const struct svs_fusemap *glb_fuse_map; const u32 *regs; u32 bank_max; + u32 ts_coeff; }; /** @@ -2926,6 +2933,7 @@ static const struct svs_platform_data svs_mt8195_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8195_banks), + .ts_coeff = SVSB_TS_COEFF_MT8195, .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { { 0, 0 }, { 19, 4 } } @@ -2938,6 +2946,7 @@ static const struct svs_platform_data svs_mt8192_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8192_banks), + .ts_coeff = SVSB_TS_COEFF_MT8195, .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { /* FT_PGM not present */ { -1, 0 }, { 19, 4 } @@ -2951,6 +2960,7 @@ static const struct svs_platform_data svs_mt8188_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8188_banks), + .ts_coeff = SVSB_TS_COEFF_MT8195, .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { /* FT_PGM and VMIN not present */ { -1, 0 }, { -1, 0 } @@ -2964,6 +2974,7 @@ static const struct svs_platform_data svs_mt8186_platform_data = { .probe = svs_mt8186_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8186_banks), + .ts_coeff = SVSB_TS_COEFF_MT8186, .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { /* FT_PGM and VMIN not present */ { -1, 0 }, { -1, 0 } @@ -3021,6 +3032,7 @@ static int svs_probe(struct platform_device *pdev) svsp->banks = svsp_data->banks; svsp->regs = svsp_data->regs; svsp->bank_max = svsp_data->bank_max; + svsp->ts_coeff = svsp_data->ts_coeff; ret = svsp_data->probe(svsp); if (ret) From patchwork Tue Nov 21 12:50:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167735 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp595945vqb; Tue, 21 Nov 2023 04:54:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IFpcqcaCxt9sJZt7e0vSaIqnQ9ZkATy7utagFKHOB+3Jl+J7cOjGwqWx8wenraXzVZz/xMP X-Received: by 2002:a17:90b:4f4e:b0:27c:f8bd:9a98 with SMTP id pj14-20020a17090b4f4e00b0027cf8bd9a98mr7063718pjb.40.1700571289015; Tue, 21 Nov 2023 04:54:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571289; cv=none; d=google.com; s=arc-20160816; b=rxMqRI1JSkfsWYFMBOaB7RoMJgWRizvNkbNXGQFM7wDP0yqV7RgHN1B9ddV38bB51W +t1sE7ForX4s+SRC4nwOTeYfXRcxddWQMYtN0m9RtSsLWo/k8sORRS12w2otHDqGRiNV Z6e+nKWwg4BNKc9c4Ss/7GbVwRKymtpAN5tf8ywDxtFRB1C4iiVuDmeVF3bmy5EmpVid n0zx9oYjsr2bOKpKkvDWRL5IHqVGx97woLJgjXIJmmal8ZAdxEV+t830Nos+Un/waDMc DknCcqNRLI1zLIvzxTKgsWuJ51atSR43tgKM/HspyXCDi45pmaNHIWhA/umhgD7wbZs0 Flzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/sTmpSUpUoBKaV3NeAFIU7m6PHTjrLFL8tG3Y3lCQEU=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=UDvny7uDrHMqMxxSQQ5mgAvmX8JjPg6y6XuxcGchX1HKz1DSVQEYe2LxVczWnSUzk+ xEPXd331pg86iS65Q09WdvlKLwooQFTOZEcCI0AANmq0QGIUF+V855IR5ZZSjFl03tak X/krSlxtJzYzhJ1F+gRKFdEbVI9cuP/JZUYajfbr0TUB1FUengCDPiY8O5UQyRFkcoge GRjF1naOFLAQnZzvXNZRjfgUtHIMmVb1C3lK3KEYdf55gbH3iIrkGUq/4D4hiWfBm3U5 OiiTQD4FJnF7xjaI/U744QZJ2DmEGG2bHuG+KlasAg+nIbwEJnpWZsivJ1xzksEmtmSQ SGQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=QXtid+iv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id v12-20020a17090a898c00b00280386ec042si12608208pjn.149.2023.11.21.04.54.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:54:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=QXtid+iv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 6B48E80A1875; Tue, 21 Nov 2023 04:51:39 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233878AbjKUMv0 (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233758AbjKUMvF (ORCPT ); Tue, 21 Nov 2023 07:51:05 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0AAA1AA; Tue, 21 Nov 2023 04:51:01 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id C8E4F6607314; Tue, 21 Nov 2023 12:50:59 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571060; bh=YAm2XwYefU2Wi2EmslwaPruVfwk8nKNQAa35BFgYSvI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QXtid+ivp1dSih09MgnuxB4/ZRA4pjGsxDuGrhSKwwYcVK0UMLDH0eWsBzpUYBULB XkPzk17UGPJj9qII/QGy1AKPOVKl+k72O6cbbYaYsz6/S4b9lpuCJ632A6PYH659ZU LT5Lz5/KwXwbw326hHl0PO4uNsgCwNdxwoI1IiBmqgYAjyWUWN9VmMuYrW7Qv1kaRA hX2aEmUc5WgzHTf59V/Q8Ydty51DJ1ig8+cPlNb20L2uS21/kHxClGt+Hi+EreKmin OyvnPwbiaOb2uQs6pYcvDtn+X7oaV5EEn8v8GvJwv+i18NYdLuvx+H8PxOeNlkLqei xBuD6EZCNjuog== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 09/20] soc: mediatek: mtk-svs: Move t-calibration-data retrieval to svs_probe() Date: Tue, 21 Nov 2023 13:50:33 +0100 Message-ID: <20231121125044.78642-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:51:39 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178239588244420 X-GMAIL-MSGID: 1783178239588244420 The t-calibration-data (SVS-Thermal calibration data) shall exist for all SoCs or SVS won't work anyway: move it to the common svs_probe() function and remove it from all of the per-SoC efuse_parsing() probe callbacks. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 32 ++++++-------------------------- 1 file changed, 6 insertions(+), 26 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index ab564d48092b..1042af2aee3f 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1884,11 +1884,6 @@ static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) svsb->vmax += svsb->dvt_fixed; } - ret = svs_get_efuse_data(svsp, "t-calibration-data", - &svsp->tefuse, &svsp->tefuse_max); - if (ret) - return false; - for (i = 0; i < svsp->tefuse_max; i++) if (svsp->tefuse[i] != 0) break; @@ -1949,11 +1944,6 @@ static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) svsb->vmax += svsb->dvt_fixed; } - ret = svs_get_efuse_data(svsp, "t-calibration-data", - &svsp->tefuse, &svsp->tefuse_max); - if (ret) - return false; - for (i = 0; i < svsp->tefuse_max; i++) if (svsp->tefuse[i] != 0) break; @@ -2009,11 +1999,6 @@ static bool svs_mt8188_efuse_parsing(struct svs_platform *svsp) svsb->vmax += svsb->dvt_fixed; } - ret = svs_get_efuse_data(svsp, "t-calibration-data", - &svsp->tefuse, &svsp->tefuse_max); - if (ret) - return false; - for (i = 0; i < svsp->tefuse_max; i++) if (svsp->tefuse[i] != 0) break; @@ -2097,11 +2082,6 @@ static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) svsb->vmax += svsb->dvt_fixed; } - ret = svs_get_efuse_data(svsp, "t-calibration-data", - &svsp->tefuse, &svsp->tefuse_max); - if (ret) - return false; - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); if (!golden_temp) golden_temp = 50; @@ -2198,11 +2178,6 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) } } - ret = svs_get_efuse_data(svsp, "t-calibration-data", - &svsp->tefuse, &svsp->tefuse_max); - if (ret) - return false; - /* Thermal efuse parsing */ adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0); adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0); @@ -3040,8 +3015,13 @@ static int svs_probe(struct platform_device *pdev) ret = svs_get_efuse_data(svsp, "svs-calibration-data", &svsp->efuse, &svsp->efuse_max); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Cannot read SVS calibration\n"); + + ret = svs_get_efuse_data(svsp, "t-calibration-data", + &svsp->tefuse, &svsp->tefuse_max); if (ret) { - ret = -EPERM; + dev_err_probe(&pdev->dev, ret, "Cannot read SVS-Thermal calibration\n"); goto svs_probe_free_efuse; } From patchwork Tue Nov 21 12:50:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167733 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp595984vqb; Tue, 21 Nov 2023 04:54:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IFzQ+oPpRn22OGL0Oauvy6rqzxhbFjFxcEL8UMopQls01Y+D6O5J2cwyZLSEs1DBj3SzPL6 X-Received: by 2002:a05:6a20:5d8f:b0:187:995c:1d74 with SMTP id km15-20020a056a205d8f00b00187995c1d74mr6700566pzb.55.1700571293332; Tue, 21 Nov 2023 04:54:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571293; cv=none; d=google.com; s=arc-20160816; b=ovt6q8KJjqPogxB++UCl1BA88eQe66f84JvIaa/6BQA1qaXwXtiTx0zMlJ+IE/+AXf NXpG7P3HQ6M1YfkwIyqkRWvODZqsSut7vPGsl3JUuVGfzplR6bQ4bqak0Ab9yDASmwin Go9i/qp5AaCo+RSfR4WHIQ7fvDiKMcMankB7LvnQJneGMFRNHDGHJIzA2yCkxHstcHYf j3Q8IfufhfMub/fZNpnT56elxmmM5JzSiQhol70ms5d5B8VktLqmwQnOTXpALNEeHQb7 Wsu1x6o1YDu8Y5IixBHrE0F/GSmJrdbsZrlveveov32CyhEAq9xpBPqsK05vn0h+TjQ7 yi6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2jxZKtVyXB2tzqqlGVSJEMZeZf6/8BJWPByJAAdW+g4=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=LiTanFzYE9jrYEtlS4NPdoFaoA1VRePwHHx1L5UJZBjztpO8BHur+V4a/Q5rUqnZSm h7QvxKVCeMT4Uyy+2t3/HwssC84qB5rtjiBCeQL+ysvvo+Mo+Rl13Y18yEkd4dfP8MGI YGd70c4RMtf6S4ot1BsSJwvBN0CJM+UroyIkWLU31PLyEcQY79rgeONZ7XRlGhGjo/0a PW84/9rLC7LGLxy8ZRwBuNMFSQYeNHXBfkTIZjHfd6kuaJyaoKOq81Fn2N58RglSupMo jHhU00RzN79UA2Nm1qOykZZfGimpyv+UL1Qu2EE0wYkNXL3QFePkJf+tEAG9nzgAi12T YrjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=SthxPow9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id lb3-20020a17090b4a4300b002805aa7b138si12920550pjb.59.2023.11.21.04.54.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:54:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=SthxPow9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 12BA9804E807; Tue, 21 Nov 2023 04:51:49 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233813AbjKUMvd (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233709AbjKUMvO (ORCPT ); Tue, 21 Nov 2023 07:51:14 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AF07D6F; Tue, 21 Nov 2023 04:51:02 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id D19F1660731B; Tue, 21 Nov 2023 12:51:00 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571061; bh=hkZjJ7q8rV2xyxskAur6iNWuCHUO3iI4tzSStjxhlcA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SthxPow9/ahxFz0vHixuSB05ua6d4W5wCR6J0gY3Y9QvjktSEMkOeSpDKOnkTZ/uJ VFxM4sRCZgCzDf+icOWp8HwnK/GFqMVGoogbelMg2UWILwqUQXe/v0OqEUAcfwJzlz m8Fmy4hIVqihYhkD79g5wcnwOQKm8yJTmJHtupxKXjdokoGKGtcUqsR0jqN7i3UK7g 7tzQYdkqRsMKCTNY/aPQQrVsRe9ymm3uShywDTFzwScdt+txT8R9aOuO6PkZLuAfTj EpBjJrvpZbpe6pwaX7wRLutu6a+3oaN+x2Idn3W76YonttY/rOFd8pN6tjbKVBTHtx QS6ROFu8BvAOg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 10/20] soc: mediatek: mtk-svs: Commonize efuse parse function for most SoCs Date: Tue, 21 Nov 2023 13:50:34 +0100 Message-ID: <20231121125044.78642-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:51:49 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178244620432610 X-GMAIL-MSGID: 1783178244620432610 Remove almost all of the per-SoC .efuse_parsing() callbacks and replace them with one common callback svs_common_parse_efuse(): to do that, also change the function signature of the callback to add the newly required pointer to struct svs_platform_data, containing the SVS-global fuse map. This is done for MT8186, MT8188, MT8192, MT8195. As for MT8183, the efuse parse function was simplified by using the new fuse maps. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 332 +++++++-------------------------- 1 file changed, 66 insertions(+), 266 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 1042af2aee3f..517a27c58888 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -122,6 +122,9 @@ #define SVSB_TS_COEFF_MT8195 250460 #define SVSB_TS_COEFF_MT8186 204650 +/* Algo helpers */ +#define FUSE_DATA_NOT_VALID U32_MAX + /* svs bank related setting */ #define BITS8 8 #define MAX_OPP_ENTRIES 16 @@ -399,7 +402,7 @@ struct svs_platform { struct svs_platform_data { char *name; struct svs_bank *banks; - bool (*efuse_parsing)(struct svs_platform *svsp); + bool (*efuse_parsing)(struct svs_platform *svsp, const struct svs_platform_data *pdata); int (*probe)(struct svs_platform *svsp); const struct svs_fusemap *glb_fuse_map; const u32 *regs; @@ -1838,264 +1841,83 @@ static int svs_get_efuse_data(struct svs_platform *svsp, return 0; } -static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) +static u32 svs_get_fuse_val(u32 *fuse_array, const struct svs_fusemap *fmap, u8 nbits) { - struct svs_bank *svsb; - u32 idx, i, ft_pgm, vmin, golden_temp; - int ret; - - for (i = 0; i < svsp->efuse_max; i++) - if (svsp->efuse[i]) - dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", - i, svsp->efuse[i]); - - if (!svsp->efuse[10]) { - dev_notice(svsp->dev, "svs_efuse[10] = 0x0?\n"); - return false; - } - - /* Svs efuse parsing */ - ft_pgm = svsp->efuse[0] & GENMASK(7, 0); - vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); - - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - - if (vmin == 0x1) - svsb->vmin = 0x1e; - - if (ft_pgm == 0) - svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; - - if (svsb->type == SVSB_TYPE_LOW) { - svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); - } else if (svsb->type == SVSB_TYPE_HIGH) { - svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); - } - - svsb->vmax += svsb->dvt_fixed; - } - - for (i = 0; i < svsp->tefuse_max; i++) - if (svsp->tefuse[i] != 0) - break; + u32 val; - if (i == svsp->tefuse_max) - golden_temp = 50; /* All thermal efuse data are 0 */ - else - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + if (fmap->index < 0) + return FUSE_DATA_NOT_VALID; - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - svsb->mts = 500; - svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; - } + val = fuse_array[fmap->index] >> fmap->ofst; + val &= GENMASK(nbits - 1, 0); - return true; + return val; } -static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) +static bool svs_is_available(struct svs_platform *svsp) { - struct svs_bank *svsb; - u32 idx, i, vmin, golden_temp; - int ret; + int i, num_populated = 0; - for (i = 0; i < svsp->efuse_max; i++) + /* If at least two fuse arrays are populated, SVS is calibrated */ + for (i = 0; i < svsp->efuse_max; i++) { if (svsp->efuse[i]) - dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", - i, svsp->efuse[i]); - - if (!svsp->efuse[9]) { - dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n"); - return false; - } - - /* Svs efuse parsing */ - vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); - - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - - if (vmin == 0x1) - svsb->vmin = 0x1e; - - if (svsb->type == SVSB_TYPE_LOW) { - svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0); - } else if (svsb->type == SVSB_TYPE_HIGH) { - svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0); - } + num_populated++; - svsb->vmax += svsb->dvt_fixed; + if (num_populated > 1) + return true; } - for (i = 0; i < svsp->tefuse_max; i++) - if (svsp->tefuse[i] != 0) - break; - - if (i == svsp->tefuse_max) - golden_temp = 50; /* All thermal efuse data are 0 */ - else - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); - - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - svsb->mts = 500; - svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; - } - - return true; + return false; } -static bool svs_mt8188_efuse_parsing(struct svs_platform *svsp) +static bool svs_common_parse_efuse(struct svs_platform *svsp, + const struct svs_platform_data *pdata) { - struct svs_bank *svsb; - u32 idx, i, golden_temp; - int ret; + const struct svs_fusemap *gfmap = pdata->glb_fuse_map; + struct svs_fusemap tfm = { 0, 24 }; + u32 golden_temp, val; + u8 ft_pgm, vmin; + int i; - for (i = 0; i < svsp->efuse_max; i++) - if (svsp->efuse[i]) - dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", - i, svsp->efuse[i]); - - if (!svsp->efuse[5]) { - dev_notice(svsp->dev, "svs_efuse[5] = 0x0?\n"); + if (!svs_is_available(svsp)) return false; - } - - /* Svs efuse parsing */ - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - - if (svsb->type == SVSB_TYPE_LOW) { - svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); - } else if (svsb->type == SVSB_TYPE_HIGH) { - svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); - svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0); - } - - svsb->vmax += svsb->dvt_fixed; - } - - for (i = 0; i < svsp->tefuse_max; i++) - if (svsp->tefuse[i] != 0) - break; - - if (i == svsp->tefuse_max) - golden_temp = 50; /* All thermal efuse data are 0 */ - else - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); - - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - svsb->mts = 500; - svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; - } - return true; -} + /* Get golden temperature from SVS-Thermal calibration */ + val = svs_get_fuse_val(svsp->tefuse, &tfm, 8); -static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) -{ - struct svs_bank *svsb; - u32 idx, i, golden_temp; - int ret; + /* If golden temp is not programmed, use the default of 50 */ + golden_temp = val ? val : 50; - for (i = 0; i < svsp->efuse_max; i++) - if (svsp->efuse[i]) - dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", - i, svsp->efuse[i]); + /* Parse fused SVS calibration */ + ft_pgm = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_FT_PGM], 8); + vmin = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_VMIN], 2); - if (!svsp->efuse[0]) { - dev_notice(svsp->dev, "svs_efuse[0] = 0x0?\n"); - return false; - } + for (i = 0; i < svsp->bank_max; i++) { + struct svs_bank *svsb = &svsp->banks[i]; + const struct svs_fusemap *dfmap = svsb->dev_fuse_map; - /* Svs efuse parsing */ - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; + if (vmin == 1) + svsb->vmin = 0x1e; - switch (svsb->sw_id) { - case SVSB_SWID_CPU_BIG: - if (svsb->type == SVSB_TYPE_HIGH) { - svsb->mdes = (svsp->efuse[2] >> 24) & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[2] >> 16) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[2] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[13] >> 8) & GENMASK(7, 0); - svsb->dcbdet = svsp->efuse[13] & GENMASK(7, 0); - } else if (svsb->type == SVSB_TYPE_LOW) { - svsb->mdes = (svsp->efuse[3] >> 24) & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[3] >> 16) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[3] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[14] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[14] >> 16) & GENMASK(7, 0); - } - break; - case SVSB_SWID_CPU_LITTLE: - svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0); - svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0); - break; - case SVSB_SWID_CCI: - svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); - break; - case SVSB_SWID_GPU: - svsb->mdes = (svsp->efuse[6] >> 24) & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[6] >> 16) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[6] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[15] >> 8) & GENMASK(7, 0); - svsb->dcbdet = svsp->efuse[15] & GENMASK(7, 0); - break; - default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); - return false; - } + if (ft_pgm == 0) + svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; + svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8); + svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8); + svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8); + svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8); + svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8); svsb->vmax += svsb->dvt_fixed; - } - - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); - if (!golden_temp) - golden_temp = 50; - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - svsb->mts = 409; - svsb->bts = (((500 * golden_temp + 204650) / 1000) - 25) * 4; + svsb->mts = (svsp->ts_coeff * 2) / 1000; + svsb->bts = (((500 * golden_temp + svsp->ts_coeff) / 1000) - 25) * 4; } return true; } -static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) +static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, + const struct svs_platform_data *pdata) { struct svs_bank *svsb; int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0; @@ -2115,65 +1937,43 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) } /* Svs efuse parsing */ - ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0); + ft_pgm = svs_get_fuse_val(svsp->efuse, &pdata->glb_fuse_map[GLB_FT_PGM], 4); for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + const struct svs_fusemap *dfmap = svsb->dev_fuse_map; if (ft_pgm <= 1) svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; + svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8); + svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8); + svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8); + svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8); + svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8); + switch (svsb->sw_id) { case SVSB_SWID_CPU_LITTLE: - svsb->bdes = svsp->efuse[16] & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0); - svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0); - + case SVSB_SWID_CCI: if (ft_pgm <= 3) svsb->volt_od += 10; else svsb->volt_od += 2; break; case SVSB_SWID_CPU_BIG: - svsb->bdes = svsp->efuse[18] & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0); - if (ft_pgm <= 3) svsb->volt_od += 15; else svsb->volt_od += 12; break; - case SVSB_SWID_CCI: - svsb->bdes = svsp->efuse[4] & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0); - svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); - - if (ft_pgm <= 3) - svsb->volt_od += 10; - else - svsb->volt_od += 2; - break; case SVSB_SWID_GPU: - svsb->bdes = svsp->efuse[6] & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); - - if (ft_pgm >= 2) { + if (ft_pgm != FUSE_DATA_NOT_VALID && ft_pgm >= 2) { svsb->freq_base = 800000000; /* 800MHz */ svsb->dvt_fixed = 2; } break; default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); return false; } } @@ -2904,7 +2704,7 @@ static struct svs_bank svs_mt8183_banks[] = { static const struct svs_platform_data svs_mt8195_platform_data = { .name = "mt8195-svs", .banks = svs_mt8195_banks, - .efuse_parsing = svs_mt8195_efuse_parsing, + .efuse_parsing = svs_common_parse_efuse, .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8195_banks), @@ -2917,7 +2717,7 @@ static const struct svs_platform_data svs_mt8195_platform_data = { static const struct svs_platform_data svs_mt8192_platform_data = { .name = "mt8192-svs", .banks = svs_mt8192_banks, - .efuse_parsing = svs_mt8192_efuse_parsing, + .efuse_parsing = svs_common_parse_efuse, .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8192_banks), @@ -2931,7 +2731,7 @@ static const struct svs_platform_data svs_mt8192_platform_data = { static const struct svs_platform_data svs_mt8188_platform_data = { .name = "mt8188-svs", .banks = svs_mt8188_banks, - .efuse_parsing = svs_mt8188_efuse_parsing, + .efuse_parsing = svs_common_parse_efuse, .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8188_banks), @@ -2945,7 +2745,7 @@ static const struct svs_platform_data svs_mt8188_platform_data = { static const struct svs_platform_data svs_mt8186_platform_data = { .name = "mt8186-svs", .banks = svs_mt8186_banks, - .efuse_parsing = svs_mt8186_efuse_parsing, + .efuse_parsing = svs_common_parse_efuse, .probe = svs_mt8186_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8186_banks), @@ -3025,7 +2825,7 @@ static int svs_probe(struct platform_device *pdev) goto svs_probe_free_efuse; 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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id j9-20020a170903024900b001b973681493si10591621plh.16.2023.11.21.04.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:54:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=fQS7q6n0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 9CFE6804C553; Tue, 21 Nov 2023 04:51:53 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234059AbjKUMvg (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233754AbjKUMvO (ORCPT ); Tue, 21 Nov 2023 07:51:14 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DED40D4C; Tue, 21 Nov 2023 04:51:03 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id DD4BF6607324; Tue, 21 Nov 2023 12:51:01 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571062; bh=Ugc04MbnUnt7uzZ2TQCUP0pKACMxidFV1p9AUF2t0WA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fQS7q6n01f7NFD/WR90kOGIjofEUXiDULQkINnbAdxfBjYOmqhYupMpay6gLUT8oK Xg1oc4y9nYZgOjNNmdo/ehlnSwRmRL+iHfLNFy379spt4Edi0h1fgb8aVrC8VYT0GE jkj8Mm7l/p3a9TDVhYumybgPwMeuSe3DB6G6eAG9ql7xHeqvu5CGC24FcCmqJi9TN4 5yPQs/WNnTHQOsAmJkz4DNYA9jBbefwy3tDBazK/9eGY3aMYdbrG7zZyfpSLy+G+fK slZej5DsmRyLIBSnaq4vbNrOUQaOwwljJjEfpYtV7JcE/h0g8yYKjhAcTzRI8NUtvR oC50u1xv/WzeA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 11/20] soc: mediatek: mtk-svs: Drop supplementary svs per-bank pointer Date: Tue, 21 Nov 2023 13:50:35 +0100 Message-ID: <20231121125044.78642-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:51:53 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178246851021291 X-GMAIL-MSGID: 1783178246851021291 Drop the "pbank" pointer from struct svs_bank: this was used to simply pass a pointer to the SVS bank that the flow was working on. That for instance needs more locking, and it's avoidable by adding one more parameter to functions working on specific banks, either a bank index number, or passing the svs_bank pointer directly from the caller. Even if the locking can now be reduced, for now, it was still left in place for the sake of making sure to not introduce any stability and/or reliability regression. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 87 ++++++++++++++++------------------ 1 file changed, 40 insertions(+), 47 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 517a27c58888..e7df3a577b4c 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -372,7 +372,6 @@ struct svs_fusemap { * @base: svs platform register base * @dev: svs platform device * @main_clk: main clock for svs bank - * @pbank: svs bank pointer needing to be protected by spin_lock section * @banks: svs banks that svs platform supports * @rst: svs platform reset control * @efuse_max: total number of svs efuse @@ -387,7 +386,6 @@ struct svs_platform { void __iomem *base; struct device *dev; struct clk *main_clk; - struct svs_bank *pbank; struct svs_bank *banks; struct reset_control *rst; size_t efuse_max; @@ -483,8 +481,8 @@ struct svs_bank { struct regulator *buck; struct thermal_zone_device *tzd; struct mutex lock; /* lock to protect voltage update process */ - void (*set_freq_pct)(struct svs_platform *svsp); - void (*get_volts)(struct svs_platform *svsp); + void (*set_freq_pct)(struct svs_platform *svsp, struct svs_bank *svsb); + void (*get_volts)(struct svs_platform *svsp, struct svs_bank *svsb); char *name; char *buck_name; char *tzone_name; @@ -555,10 +553,8 @@ static void svs_writel_relaxed(struct svs_platform *svsp, u32 val, writel_relaxed(val, svsp->base + svsp->regs[rg_i]); } -static void svs_switch_bank(struct svs_platform *svsp) +static void svs_switch_bank(struct svs_platform *svsp, struct svs_bank *svsb) { - struct svs_bank *svsb = svsp->pbank; - svs_writel_relaxed(svsp, svsb->core_sel, CORESEL); } @@ -693,8 +689,7 @@ static void svs_bank_disable_and_restore_default_volts(struct svs_platform *svsp return; spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; - svs_switch_bank(svsp); + svs_switch_bank(svsp, svsb); svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); spin_unlock_irqrestore(&svs_lock, flags); @@ -926,9 +921,8 @@ static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx) return DIV_ROUND_UP(vx, 100); } -static void svs_get_bank_volts_v3(struct svs_platform *svsp) +static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *svsb) { - struct svs_bank *svsb = svsp->pbank; u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0; u32 middle_index = (svsb->opp_count / 2); @@ -1041,9 +1035,8 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) } } -static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) +static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *svsb) { - struct svs_bank *svsb = svsp->pbank; u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0; u32 b_sft, shift_byte = 0, turn_pt; u32 middle_index = (svsb->opp_count / 2); @@ -1124,9 +1117,8 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) svs_writel_relaxed(svsp, freq_pct30, FREQPCT30); } -static void svs_get_bank_volts_v2(struct svs_platform *svsp) +static void svs_get_bank_volts_v2(struct svs_platform *svsp, struct svs_bank *svsb) { - struct svs_bank *svsb = svsp->pbank; u32 temp, i; temp = svs_readl_relaxed(svsp, VOP74); @@ -1181,9 +1173,8 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp) } } -static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) +static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp, struct svs_bank *svsb) { - struct svs_bank *svsb = svsp->pbank; u32 freqpct74_val, freqpct30_val; freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) | @@ -1201,12 +1192,13 @@ static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) } static void svs_set_bank_phase(struct svs_platform *svsp, + unsigned int bank_idx, enum svsb_phase target_phase) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs; - svs_switch_bank(svsp); + svs_switch_bank(svsp, svsb); des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) | FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes); @@ -1225,7 +1217,7 @@ static void svs_set_bank_phase(struct svs_platform *svsp, svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG); svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG); - svsb->set_freq_pct(svsp); + svsb->set_freq_pct(svsp, svsb); limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) | FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) | @@ -1267,18 +1259,20 @@ static void svs_set_bank_phase(struct svs_platform *svsp, } static inline void svs_save_bank_register_data(struct svs_platform *svsp, + unsigned short bank_idx, enum svsb_phase phase) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; enum svs_reg_index rg_i; for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++) svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i); } -static inline void svs_error_isr_handler(struct svs_platform *svsp) +static inline void svs_error_isr_handler(struct svs_platform *svsp, + unsigned short bank_idx) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n", __func__, svs_readl_relaxed(svsp, CORESEL)); @@ -1290,16 +1284,17 @@ static inline void svs_error_isr_handler(struct svs_platform *svsp) svs_readl_relaxed(svsp, SMSTATE1)); dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP)); - svs_save_bank_register_data(svsp, SVSB_PHASE_ERROR); + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_ERROR); svsb->phase = SVSB_PHASE_ERROR; svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); } -static inline void svs_init01_isr_handler(struct svs_platform *svsp) +static inline void svs_init01_isr_handler(struct svs_platform *svsp, + unsigned short bank_idx) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; u32 val; dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", @@ -1307,7 +1302,7 @@ static inline void svs_init01_isr_handler(struct svs_platform *svsp) svs_readl_relaxed(svsp, VDESIGN30), svs_readl_relaxed(svsp, DCVALUES)); - svs_save_bank_register_data(svsp, SVSB_PHASE_INIT01); + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT01); svsb->phase = SVSB_PHASE_INIT01; val = ~(svs_readl_relaxed(svsp, DCVALUES) & GENMASK(15, 0)) + 1; @@ -1325,32 +1320,34 @@ static inline void svs_init01_isr_handler(struct svs_platform *svsp) svsb->core_sel &= ~SVSB_DET_CLK_EN; } -static inline void svs_init02_isr_handler(struct svs_platform *svsp) +static inline void svs_init02_isr_handler(struct svs_platform *svsp, + unsigned short bank_idx) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", __func__, svs_readl_relaxed(svsp, VOP74), svs_readl_relaxed(svsp, VOP30), svs_readl_relaxed(svsp, DCVALUES)); - svs_save_bank_register_data(svsp, SVSB_PHASE_INIT02); + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT02); svsb->phase = SVSB_PHASE_INIT02; - svsb->get_volts(svsp); + svsb->get_volts(svsp, svsb); svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS); } -static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp) +static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp, + unsigned short bank_idx) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; - svs_save_bank_register_data(svsp, SVSB_PHASE_MON); + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_MON); svsb->phase = SVSB_PHASE_MON; - svsb->get_volts(svsp); + svsb->get_volts(svsp, svsb); svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS); @@ -1368,7 +1365,6 @@ static irqreturn_t svs_isr(int irq, void *data) WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; /* Find out which svs bank fires interrupt */ if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) { @@ -1376,20 +1372,20 @@ static irqreturn_t svs_isr(int irq, void *data) continue; } - svs_switch_bank(svsp); + svs_switch_bank(svsp, svsb); int_sts = svs_readl_relaxed(svsp, INTSTS); svs_en = svs_readl_relaxed(svsp, SVSEN); if (int_sts == SVSB_INTSTS_F0_COMPLETE && svs_en == SVSB_PTPEN_INIT01) - svs_init01_isr_handler(svsp); + svs_init01_isr_handler(svsp, idx); else if (int_sts == SVSB_INTSTS_F0_COMPLETE && svs_en == SVSB_PTPEN_INIT02) - svs_init02_isr_handler(svsp); + svs_init02_isr_handler(svsp, idx); else if (int_sts & SVSB_INTSTS_FLD_MONVOP) - svs_mon_mode_isr_handler(svsp); + svs_mon_mode_isr_handler(svsp, idx); else - svs_error_isr_handler(svsp); + svs_error_isr_handler(svsp, idx); spin_unlock_irqrestore(&svs_lock, flags); break; @@ -1518,8 +1514,7 @@ static int svs_init01(struct svs_platform *svsp) } spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; - svs_set_bank_phase(svsp, SVSB_PHASE_INIT01); + svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT01); spin_unlock_irqrestore(&svs_lock, flags); time_left = wait_for_completion_timeout(&svsb->init_completion, @@ -1588,8 +1583,7 @@ static int svs_init02(struct svs_platform *svsp) reinit_completion(&svsb->init_completion); spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; - svs_set_bank_phase(svsp, SVSB_PHASE_INIT02); + svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT02); spin_unlock_irqrestore(&svs_lock, flags); time_left = wait_for_completion_timeout(&svsb->init_completion, @@ -1645,8 +1639,7 @@ static void svs_mon_mode(struct svs_platform *svsp) continue; spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; - svs_set_bank_phase(svsp, SVSB_PHASE_MON); + svs_set_bank_phase(svsp, idx, SVSB_PHASE_MON); spin_unlock_irqrestore(&svs_lock, flags); } } From patchwork Tue Nov 21 12:50:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167732 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp595971vqb; Tue, 21 Nov 2023 04:54:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IG7LH+WYgDYxnR/fnAEWTpH3T9TXS4hZ++xp68pr72QXvBt4H+lRBmJkpZlbE/kd/9cMWzS X-Received: by 2002:a05:6a20:2585:b0:18a:fbd1:8e6d with SMTP id k5-20020a056a20258500b0018afbd18e6dmr1011419pzd.27.1700571291968; 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[23.128.96.37]) by mx.google.com with ESMTPS id fb27-20020a056a002d9b00b006cb901a87c4si4806278pfb.376.2023.11.21.04.54.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:54:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=JME8J0fO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 46497804DDBA; Tue, 21 Nov 2023 04:51:46 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234018AbjKUMv3 (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233865AbjKUMvO (ORCPT ); Tue, 21 Nov 2023 07:51:14 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 073D7D7B; Tue, 21 Nov 2023 04:51:04 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E7F0D6607325; Tue, 21 Nov 2023 12:51:02 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571063; bh=zNfya3IwOleE3gv7u+f222r6Eh2oBHfy4LgRig9Wjl4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JME8J0fOzBllttmy6YP2f3UBamsismPO7cYy+ESjToe7kho7iYAUsR25Z+1uEKcm7 KE8sn6k9kq99YUINIwIybXl4NCC8KPJHC1sMS1SgspPRyMUqjWCJ4JsCEMdxEvazGl 3E0+17hF4SP9Pgo6WuYdMQj3W8NnNC7qddBmZphikoPsjgwZ6bla6gouBP3ZdMnoom 4r8/B0JZYS2FIupPHmwhvf/xfvYJfuAcesxMzeMUfAavkcocd0qAzDfUNOBw0ILJx5 5/SIUjAmJoP3xrsz4CW9iYKYMqcFM3j7Kg6DElPz6z1WpYHwpsTuvMlNLcTiDAxzsH P7ZPHcrhlUg+Q== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 12/20] soc: mediatek: mtk-svs: Commonize MT8192 probe function for MT8186 Date: Tue, 21 Nov 2023 13:50:36 +0100 Message-ID: <20231121125044.78642-13-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:51:46 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178243000752061 X-GMAIL-MSGID: 1783178243000752061 Include the additions of svs_mt8186_platform_probe() in the common svs_mt8192_platform_probe() function, remove the former, and use the latter as .probe() callback for MT8186. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 44 ++++++---------------------------- 1 file changed, 7 insertions(+), 37 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index e7df3a577b4c..cd5064683506 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2119,7 +2119,6 @@ static struct device *svs_add_device_link(struct svs_platform *svsp, static int svs_mt8192_platform_probe(struct svs_platform *svsp) { struct device *dev; - struct svs_bank *svsb; u32 idx; svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); @@ -2133,40 +2132,7 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) "failed to get lvts device\n"); for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - - if (svsb->type == SVSB_TYPE_HIGH) - svsb->opp_dev = svs_add_device_link(svsp, "gpu"); - else if (svsb->type == SVSB_TYPE_LOW) - svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); - - if (IS_ERR(svsb->opp_dev)) - return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), - "failed to get OPP device for bank %d\n", - idx); - } - - return 0; -} - -static int svs_mt8186_platform_probe(struct svs_platform *svsp) -{ - struct device *dev; - struct svs_bank *svsb; - u32 idx; - - svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); - if (IS_ERR(svsp->rst)) - return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), - "cannot get svs reset control\n"); - - dev = svs_add_device_link(svsp, "thermal-sensor"); - if (IS_ERR(dev)) - return dev_err_probe(svsp->dev, PTR_ERR(dev), - "failed to get lvts device\n"); - - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; + struct svs_bank *svsb = &svsp->banks[idx]; switch (svsb->sw_id) { case SVSB_SWID_CPU_LITTLE: @@ -2177,7 +2143,11 @@ static int svs_mt8186_platform_probe(struct svs_platform *svsp) svsb->opp_dev = svs_add_device_link(svsp, "cci"); break; case SVSB_SWID_GPU: - svsb->opp_dev = svs_add_device_link(svsp, "gpu"); + if (svsb->type == SVSB_TYPE_LOW) + svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); + else + svsb->opp_dev = svs_add_device_link(svsp, "gpu"); + break; break; default: dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); @@ -2739,7 +2709,7 @@ static const struct svs_platform_data svs_mt8186_platform_data = { .name = "mt8186-svs", .banks = svs_mt8186_banks, .efuse_parsing = svs_common_parse_efuse, - .probe = svs_mt8186_platform_probe, + .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8186_banks), .ts_coeff = SVSB_TS_COEFF_MT8186, From patchwork Tue Nov 21 12:50:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167736 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp596038vqb; Tue, 21 Nov 2023 04:55:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IH+vqDZWkU9wijir5A5SSNLXxJ2fhcmxBfB698JO3UXA+YiF+wBv0YncWnTZVcHd+g/X5PH X-Received: by 2002:a17:902:650a:b0:1cf:7439:690c with SMTP id b10-20020a170902650a00b001cf7439690cmr587809plk.11.1700571301306; Tue, 21 Nov 2023 04:55:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571301; cv=none; d=google.com; s=arc-20160816; b=GWMDy9YO0zexlzpB5VF22BqiTTMF2VYJOc//9oVX1eTHtHcVQzkj5194VhFp5ABpvg oardLQ7/IReNEGiiaA7+Ctpz7yzVIml2qfffzBHj/cVFjWzWzuj4aVPwEl2R3vHj9yxz 5NQIoJ7BHe1L4IEhgllgc1l/sJd3AEmiGDkKjS9zDLuz89qM/OIKpuZV9Nt6QG+Sz1oK DJ+VrajYmC8jegPd1f34jawrR4AVJeTANznquK5N8BpWfnaQUxVvBFHUBG6Y/aHRwHaS qA87+M6ELIECXXRqxkWrVX3DaoOrfb+ouLD55Jx96/o1l+SJBZ6p8ZcenqdfDLkWvOQq oScQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IAsuYrChTQ+mBfJ8/Sih8DwoRlV6uZI64nyaA9Bhlv4=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=yawxDrgkO/lgHe/kht8hlKAF4ifzj0W9zRlP3G5znwnW/QamOO7yjl2e1x9CbkMEEC btUbbiJvsKmenbV/mT8zbH/rVQ18BivSs9YaeySBA7KAGdp9r9jhjxVk16ZupBEw0kse xhSmajDMU3ix4GPVNAUiBqdO2KSgWR3VzSA3qlF8FTMYOzomSneihBpe/yxSK1/JPGDg jwzlTBZ3Qw493ksIanuK3fmhmu5bVs/bD6EQIvBwrn80PlL1TgN7rkZW/+2CeSE+JKBE mSSOAGX4SXiXBJrAyFshy4JnKtFuyKNG917D061ZUqkrRyenCrwIMZ+8MBTTcJV6Svpu GWRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=nmoGRWIy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id j187-20020a638bc4000000b00578db6172fdsi10258937pge.325.2023.11.21.04.55.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:55:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=nmoGRWIy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 2A57280B01ED; Tue, 21 Nov 2023 04:52:09 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234128AbjKUMvj (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233887AbjKUMvP (ORCPT ); Tue, 21 Nov 2023 07:51:15 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AE2F10CA; Tue, 21 Nov 2023 04:51:05 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id F2D156607314; Tue, 21 Nov 2023 12:51:03 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571064; bh=8hsTcNhO6pxrVZKfxLeF/xkr1pZ2hVQ5uEBZ0ICc55k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nmoGRWIypByB7QtqvoL5JTa8TqDXOQZ4A0ih7PRveZ8JVpqM0wu53jXz0Z2a6cv74 QWqflMRgdduut4HJGceb4XwQDT2cd7B1yIeQsX7QI8OVmS/N5q6thiWkkvL/22AJNM 2BGzq60E1HV6MURl6nWU+613mgZSj30mNzso7kF1HkYerkfLTb2zVCc6GT10/50yeD X3pfrswRsgGcC+UEOOn39riImoTl9+g4YjySg+aSLLq616R4WkQzLv+xj+j7UxbPxj O3O2c6nOiG0sBSfvLuhptlin8XJznOxILTR5u8RW86F1Nyq+qNSrL8Sh1XsRYIE/GR +608jeQ/2nZ0A== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 13/20] soc: mediatek: mtk-svs: Remove redundant print in svs_get_efuse_data Date: Tue, 21 Nov 2023 13:50:37 +0100 Message-ID: <20231121125044.78642-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:52:09 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178252694921557 X-GMAIL-MSGID: 1783178252694921557 Callers of svs_get_efuse_data() are already printing an error in case anything goes wrong, and the error print for nvmem_cell_read() failure is redundant: remove it. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index cd5064683506..5fd9884dd20f 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1822,8 +1822,6 @@ static int svs_get_efuse_data(struct svs_platform *svsp, *svsp_efuse = nvmem_cell_read(cell, svsp_efuse_max); if (IS_ERR(*svsp_efuse)) { - dev_err(svsp->dev, "cannot read \"%s\" efuse: %ld\n", - nvmem_cell_name, PTR_ERR(*svsp_efuse)); nvmem_cell_put(cell); return PTR_ERR(*svsp_efuse); } From patchwork Tue Nov 21 12:50:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167728 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp594861vqb; Tue, 21 Nov 2023 04:52:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IFcxjo4zwTQCq/G+QUQtURJO6F3DbPjAJDxEBUpTp9H4f3vICAJoJWbliiFkdWmbxn2pILJ X-Received: by 2002:a9d:7554:0:b0:6b7:4a52:a33a with SMTP id b20-20020a9d7554000000b006b74a52a33amr11538000otl.14.1700571154402; Tue, 21 Nov 2023 04:52:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571154; cv=none; d=google.com; s=arc-20160816; b=SUZcu1YKkLcKA4tMbD7pnlud98y5xCfGbAnxOLD973eySVVLLdCVKp/u1ySDyEw3Tr DjHSAH7PZ8MlyfgxjO5Twn+LMzZjB1ljZ5PfsjNYa4ijpp/d4yjX2LEirdVc2nZWE++j a5yS93vGxL7yq+gGtHBb4xd44kFrOWyAthFOVvuLd1fzRaonRuaYxp/0sH7xFm/QqPno clUphcy9k3eUV2uQ5U5X/fjj6Vuo1T16gFeC0STQD9hqjR2uRxkjcX8fm1VCP/m6B8ob aaSw3sZ4FJex7lEbKEyG3/Hx0CDvi/v+tFofe5n4BM1e8DbpPuaHk++eTHDYulY6sx2C YJ0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BEImrCI/kXGGUJLIMX0kD855YKMvbpgOQwIUEihf9gQ=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=Q/kmPSOZTfKGiglKa5AnKUG10t8+vYi6ZtRr7Z8T53shNvg7LIherKd8qyYMOvrsfG 4OS8uRcivqH2Re/HmCylQ3CE8oT14pz4nOYklTyzuYFxj5CLsLlXZy2fjkskHZzzu7kN VeaplvFvliNVqUnp9bq1cBs39nV2pKLYT7Y6Kms5zwNFgCgeqhlJhgAANObbBRSwOCCt D7RpAMPx6JIMBDa5tsLn0pSY2fMKs6VTssq/wPNkPxQUBFRPa+XH4nYDiaJJoOOUq6Lf asc1TmALTieLzxjz2As2YBmrXfxBCncOUOFmDbubD9Km4Z8ITEwsowjkUqluOl3J60UA 9mFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b="S8cSzG/X"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from fry.vger.email (fry.vger.email. [23.128.96.38]) by mx.google.com with ESMTPS id b17-20020a630c11000000b005be10ed80d9si10274793pgl.177.2023.11.21.04.52.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:52:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b="S8cSzG/X"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 5AFCC802641B; Tue, 21 Nov 2023 04:52:02 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233866AbjKUMvm (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233792AbjKUMvR (ORCPT ); Tue, 21 Nov 2023 07:51:17 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED6F810CE; Tue, 21 Nov 2023 04:51:06 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0706D6607319; Tue, 21 Nov 2023 12:51:04 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571065; bh=EEiAga7/PEKFwq5/KS3naIy5UuB1z5wjPE5byYQKsG4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S8cSzG/X6sVcxBU+LFBQPQo4ord4Kb0pxgC80dEAGKNPFNKt7rDi9gUVx3j6Phz4B tdvXfuvXkR79/mWGKI8OyldNZh0km9cKaTiQmwZaSO4/JHR8m9eRNguFw9DPQIYe4Q metDVDPU0oOF3/3npZcWvjlnbVJT1epWsIvi96+ODzyxFEDiKQkbkTKLiWlbPPNoSg quIxJh5r/dKeQk7uBaYISnLiRqrbkDTt3wipYLOFQmtqFZKyeYlwiyqPCfDRj6tZlJ hpjfy583jyRDUwYMHMocfhmth+i9KfKn7ByZzGU3+BGUZkjh6jtzMzfBNKyScL7EL8 pnVYeS28bsWLA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 14/20] soc: mediatek: mtk-svs: Compress of_device_id entries Date: Tue, 21 Nov 2023 13:50:38 +0100 Message-ID: <20231121125044.78642-15-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:52:03 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178098446370256 X-GMAIL-MSGID: 1783178098446370256 Compress each entry to one line, as they fit in 84 columns, which is acceptable. While at it, also change the capital 'S' to 's' in 'sentinel'. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 5fd9884dd20f..ac36c2efcafa 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2731,24 +2731,12 @@ static const struct svs_platform_data svs_mt8183_platform_data = { }; static const struct of_device_id svs_of_match[] = { - { - .compatible = "mediatek,mt8195-svs", - .data = &svs_mt8195_platform_data, - }, { - .compatible = "mediatek,mt8192-svs", - .data = &svs_mt8192_platform_data, - }, { - .compatible = "mediatek,mt8188-svs", - .data = &svs_mt8188_platform_data, - }, { - .compatible = "mediatek,mt8186-svs", - .data = &svs_mt8186_platform_data, - }, { - .compatible = "mediatek,mt8183-svs", - .data = &svs_mt8183_platform_data, - }, { - /* Sentinel */ - }, + { .compatible = "mediatek,mt8195-svs", .data = &svs_mt8195_platform_data }, + { .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data }, + { .compatible = "mediatek,mt8188-svs", .data = &svs_mt8188_platform_data }, + { .compatible = "mediatek,mt8186-svs", .data = &svs_mt8186_platform_data }, + { .compatible = "mediatek,mt8183-svs", .data = &svs_mt8183_platform_data }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, svs_of_match); From patchwork Tue Nov 21 12:50:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167737 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp596046vqb; Tue, 21 Nov 2023 04:55:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IGTz4OjdaKDF3WsQUgbt3OYRVb1nsZGBhI4K+iTp3Tt80lBbLgSiHG/B4kB2boJhoSt3c20 X-Received: by 2002:a17:90a:6048:b0:27d:6dd:fb7d with SMTP id h8-20020a17090a604800b0027d06ddfb7dmr11006227pjm.17.1700571303338; Tue, 21 Nov 2023 04:55:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571303; cv=none; d=google.com; s=arc-20160816; b=ZFJDpi2Luhqq4CugZgczZ8rJv80Wgp18oPBzZNOFDM1P8b8K+Ia4wA5sbFJ2rhJWmr n3glBx5VptLQVXoEhpT/AQNzywjRkvm5lf20lE5zize2lVT1Ah3D6Uup3SHt/nBMdYRM WkE14DCxK58ZrXRMMrrQURLkVjhvRFZJW1+nnHJ4FH+HIKeqq6SK8JgrThwhInUc+e9I lKEpo/+iuyzeDs0GdG35NTDXNDQ2mttpGA/HcMOAUCjotPwo4UJz3AbfMcYC6Y5qgQGt Yt4j/aRycEubVp3EWZqVcJtxTRdv8zAuqsMaW5RSsS7y4ctmByffPc95thCSGdqJDRxN 96eQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=a5feH2/jkDCbwJZEcvQP2UexdyAXhgSRCA68qIaap+0=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=T1q3r9LPByO4RzF/perps2+G+7L/3Tdf327qnUQiTWuXo/Dc5Ti5odSCWoaY6amIPj v3zuq/CN9t9H6Eh4l359CYFAcB3wBr++DDPudNx51MZPqBCPqwmlxt/hBGhO6PZWif7C CLOzXjA2ASWqVYZjkHwzQ7RcU74By6JvftxZwXdMvH7v0iJS9uH28rnghNFN4Iu5I+Tn aCaur96ol9TO0ZI1XxeQFS59+xgeHo587JrGBfpzkCpRfuttSQ0IqnQMleC8FmQFG7d3 FVot6rURbjsCLt+nVCl57+KacInQfO3lc8uns92FBYhO8+EZsug6tDL4JcSY1T1xVVfl V4RQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=Tn4Icet1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id a12-20020a17090abe0c00b0027383ac5ebcsi10202188pjs.130.2023.11.21.04.55.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:55:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=Tn4Icet1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 866CC8049228; Tue, 21 Nov 2023 04:52:12 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234141AbjKUMvo (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233916AbjKUMvR (ORCPT ); Tue, 21 Nov 2023 07:51:17 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1133F10D4; Tue, 21 Nov 2023 04:51:08 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0D8436607326; Tue, 21 Nov 2023 12:51:05 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571066; bh=mvDbP9LsG0x+WjQA4KRWvixfVCE355+sCyiuJX+FpKc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tn4Icet19uVB5GgfkjB4A6lrS8zxXD51rMrmLc0MVNJWKcFYpgIIKvtFqDGzt/0nz VL4CEsm4Y5nl8tuAM8uk4PEq3PZatsGGPWKv5aIMPf/HbZCFrPaDLaSrvLFGmpLJ5q juOqcwuOp9CPdj6Qk2Y19FPA8uc58emAAPWyRoUEu/yQbiMlEfqeSwaGVRXftl2jDO 0IaFa8JhRlE68KfqwnWCX23/UYQTmJSYM09DtqSV+XQGUdJI5t6LcYgYRRa/AD+5W/ QvGhNrsuLRH/owcPn4lTN6lhY4nmN/uab8E/IOz8pwDojB3zuREERC7YuxUL/GyH45 cW9LBq8sEen4g== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 15/20] soc: mediatek: mtk-svs: Cleanup of svs_probe() function Date: Tue, 21 Nov 2023 13:50:39 +0100 Message-ID: <20231121125044.78642-16-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:52:12 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178254837221004 X-GMAIL-MSGID: 1783178254837221004 Cleanup the svs_probe() function: use dev_err_probe() where possible, change some efuse read failure gotos and then remove now impossible IS_ERR_OR_NULL() checks (as they will never return true) for nvmem (efuse read) failures. Also remove some unnecessary blank lines. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 32 +++++++++++--------------------- 1 file changed, 11 insertions(+), 21 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index ac36c2efcafa..ae0cc22a2941 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2775,14 +2775,13 @@ static int svs_probe(struct platform_device *pdev) } if (!svsp_data->efuse_parsing(svsp, svsp_data)) { - dev_err(svsp->dev, "efuse data parsing failed\n"); - ret = -EPERM; + ret = dev_err_probe(svsp->dev, -EINVAL, "efuse data parsing failed\n"); goto svs_probe_free_tefuse; } ret = svs_bank_resource_setup(svsp); if (ret) { - dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret); + dev_err_probe(svsp->dev, ret, "svs bank resource setup fail\n"); goto svs_probe_free_tefuse; } @@ -2794,43 +2793,40 @@ static int svs_probe(struct platform_device *pdev) svsp->main_clk = devm_clk_get(svsp->dev, "main"); if (IS_ERR(svsp->main_clk)) { - dev_err(svsp->dev, "failed to get clock: %ld\n", - PTR_ERR(svsp->main_clk)); - ret = PTR_ERR(svsp->main_clk); + ret = dev_err_probe(svsp->dev, PTR_ERR(svsp->main_clk), + "failed to get clock\n"); goto svs_probe_free_tefuse; } ret = clk_prepare_enable(svsp->main_clk); if (ret) { - dev_err(svsp->dev, "cannot enable main clk: %d\n", ret); + dev_err_probe(svsp->dev, ret, "cannot enable main clk\n"); goto svs_probe_free_tefuse; } svsp->base = of_iomap(svsp->dev->of_node, 0); if (IS_ERR_OR_NULL(svsp->base)) { - dev_err(svsp->dev, "cannot find svs register base\n"); - ret = -EINVAL; + ret = dev_err_probe(svsp->dev, -EINVAL, "cannot find svs register base\n"); goto svs_probe_clk_disable; } ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, IRQF_ONESHOT, svsp_data->name, svsp); if (ret) { - dev_err(svsp->dev, "register irq(%d) failed: %d\n", - svsp_irq, ret); + dev_err_probe(svsp->dev, ret, "register irq(%d) failed\n", svsp_irq); goto svs_probe_iounmap; } ret = svs_start(svsp); if (ret) { - dev_err(svsp->dev, "svs start fail: %d\n", ret); + dev_err_probe(svsp->dev, ret, "svs start fail\n"); goto svs_probe_iounmap; } #ifdef CONFIG_DEBUG_FS ret = svs_create_debug_cmds(svsp); if (ret) { - dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret); + dev_err_probe(svsp->dev, ret, "svs create debug cmds fail\n"); goto svs_probe_iounmap; } #endif @@ -2839,18 +2835,12 @@ static int svs_probe(struct platform_device *pdev) svs_probe_iounmap: iounmap(svsp->base); - svs_probe_clk_disable: clk_disable_unprepare(svsp->main_clk); - svs_probe_free_tefuse: - if (!IS_ERR_OR_NULL(svsp->tefuse)) - kfree(svsp->tefuse); - + kfree(svsp->tefuse); svs_probe_free_efuse: - if (!IS_ERR_OR_NULL(svsp->efuse)) - kfree(svsp->efuse); - + kfree(svsp->efuse); return ret; } From patchwork Tue Nov 21 12:50:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167738 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp596050vqb; Tue, 21 Nov 2023 04:55:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IEH8yKkLL3gdOFDHLPBxDYnFDaQqrY0sFs8Gc6KUZEFEEWp12lRTAFTyCwxyow/O+CFpqvf X-Received: by 2002:a05:6a00:d5a:b0:6c9:79e1:63a1 with SMTP id n26-20020a056a000d5a00b006c979e163a1mr3297202pfv.15.1700571303822; Tue, 21 Nov 2023 04:55:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571303; cv=none; d=google.com; s=arc-20160816; b=clJGBKsqkp3cCGIvLUqpqTv1+zOPYaBmjFt4oonrKfXChHMUXfoml3kyXtf9CazAuY /7A2/pyqug37Kq9KJd4r57ESgRte4TToD/NxKPVE7I7yYyfw3RARS/QDT56QcCSjwPKS wY0HbCtKTChfl0ZBXAEeEuCUKISrUY4xmlT0QAjps7QfYE2E4grt0GyIu2HQjfpWlySd Mh131T7xlmz6ZlukFHop62BaCUmbX7OUEhI6NS4rrkk3eLv0vN60gy7pi124S48uYVoR gJHT9+k5DphxvRezmPFoBB15ykh0FQQqUHR13Z5mNnD8OgQ4Wy7NBhBd1rrsE6TrpneR vlDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KpBUxqYvBKX4tX03KjbJxbiKYB0CW1q5AbspkuYc90k=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=JMRBcpBiB1eXNuxhsoVTF77irNg93E/09gWK+2eZAH8klkpMaarP/tzzjB+DyC7V/u r6O0/coV3PXtMKQCFR2CMhnz+c00YSJ9q6hyPNShP8OBLPXkWApf0dd7wsoruQhRoVk1 gBYCVOo7l2TrVNoV+xHY9WG/6Gon/+YgZizjgboMSLYGqs7SjmpZxY9UK91fSCWrt+K0 D8scNT/lKBfrrrmlt8nEAPRL/S/hhlVMHc7sHZV3KUvkTWs5xIRyi4BixAzH98O42bUS jLeQ5rbfEQPGpMGUsy4YAcktui89HLIyP3ybcbCN3uPanxHaYlXuN5SjvREXWMgvFqkW SFcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=MZro2lpE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id k14-20020a056a00134e00b006cb8c11d641si5195199pfu.53.2023.11.21.04.55.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:55:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=MZro2lpE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id B418680B8E56; Tue, 21 Nov 2023 04:52:12 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234176AbjKUMvr (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233946AbjKUMvR (ORCPT ); Tue, 21 Nov 2023 07:51:17 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90A8010EB; Tue, 21 Nov 2023 04:51:09 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 16530660731B; Tue, 21 Nov 2023 12:51:07 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571067; bh=XEVVBoXHkUpKz+mYu2BhuD+v7qTvXaba6bcEiQ5SYSg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MZro2lpEW2iayt+uvYR2PTq9KhFa++lNx+CbzXMb7cp3Ubs0sFYy4r78aUbs/fvpg UH8SHKdesT/NlI//U1jqxnS1toFZ5MWz1lNuyZKDGrEa/rzp4P/ZTsqHQBIsbzRlp2 YVJjVdpWaVxlz9MHvFHIPIylXH54DLlstNsxIpSMEqEAt3+wxN5syNY2WpYRMG5MOq JTa3vp1ecqa2ak+7zz1hJXTYAu+ukJJDGN/NRUKyiPQC5gj+nEMxUa9ijkRcAcUsXb qvs2VoU7LgveWfsgQzDB6at+oArRypvPS8vZDUi8P3kXxtV3l+SNXkZ3CxeWO2NCEF gPs80gfSkhxkQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 16/20] soc: mediatek: mtk-svs: Check if SVS mode is available in the beginning Date: Tue, 21 Nov 2023 13:50:40 +0100 Message-ID: <20231121125044.78642-17-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:52:13 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178255510364743 X-GMAIL-MSGID: 1783178255510364743 The svs_init01() and svs_init02() functions are already checking if the INIT01 and INIT02 modes are available - but that's done in for loops and for each SVS bank. Give those a shortcut to get out early if no SVS bank features the desired init mode: this is especially done to avoid some locking in the svs_init01(), but also to avoid multiple for loops to check the same, when no bank supports a specific mode. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index ae0cc22a2941..16a16c5a3f24 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1400,6 +1400,16 @@ static irqreturn_t svs_isr(int irq, void *data) return IRQ_HANDLED; } +static bool svs_mode_available(struct svs_platform *svsp, u8 mode) +{ + int i; + + for (i = 0; i < svsp->bank_max; i++) + if (svsp->banks[i].mode_support & mode) + return true; + return false; +} + static int svs_init01(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -1408,6 +1418,9 @@ static int svs_init01(struct svs_platform *svsp) int ret = 0, r; u32 opp_freq, opp_vboot, buck_volt, idx, i; + if (!svs_mode_available(svsp, SVSB_MODE_INIT01)) + return 0; + /* Keep CPUs' core power on for svs_init01 initialization */ cpuidle_pause_and_lock(); @@ -1575,6 +1588,9 @@ static int svs_init02(struct svs_platform *svsp) int ret; u32 idx; + if (!svs_mode_available(svsp, SVSB_MODE_INIT02)) + return 0; + for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; From patchwork Tue Nov 21 12:50:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167739 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp596048vqb; Tue, 21 Nov 2023 04:55:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IFal6qWNyJGS2OtOhD/TVf38Jpmf8/IL754P+XHLvTRnhnCd67d6250JoytxxEBxf5qpCJV X-Received: by 2002:a17:902:d712:b0:1cf:5362:7e7b with SMTP id w18-20020a170902d71200b001cf53627e7bmr11437197ply.19.1700571303658; Tue, 21 Nov 2023 04:55:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571303; cv=none; d=google.com; s=arc-20160816; b=fvDQV4jSr/ZvPcT9AlNdVZ8b67gz7Q8R1cowjQdGKoYr4SsWdGanMSc6/22A+GE9o4 K4l4W9XPnhGWtrsRJKfd1hCwjQeiHz6v1xYaQGw0vZj//kN+z2EkGOXiIyGdLL+vjRxz mcaCXwg+FPC+MDyIUA562+8iKtb7JuleQ0s92DPXSAzwLee8cm0z4wEbzx5jJF3Fktwu kQYEWn3Ju1w4C93Haga7ljB1y6cjAcaTEVZdskvQxfa4LZZUyKSu/eu1ouNVBwHy087K 0Cr2f/fxc9/W8v6srVLKFaM0cU9X0Z/NsLoFVnFhzjYBmT9IzLrfrCFOCN11Y7wq6a4S AkJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bshaVLl7I5VmG/9PhcP3nuXBjaqS8pv5wJ1Ry067DEY=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=sGH1N0SOdNJiGGJKu0ajy7T5cSee4NhWP/d+gFoxhum+VsEBTo/Ncupz0M4Dqe+/FT 5kSvlG3nVc0u4K6hIF1lTXCsRR3IifWBQDtH0rZLDJbRTsorU7sYhXHnzfRrNVIRb8lh XYNGUF+YDN+WZ3lPWTMmAt57b+scjFqUueQVKLRaQ6P/vICst9xzt26U2ibOLSSLot+c JNn9C+f0l09Df2knw+C1hXZbR7xfOj8a6lCyrq9BnjamWsHCi9C4WHK0qJ1XxAY2j4ik bGemno4ddOLxRJqxlAOfzhNSm/hfYPf3o6YludQ4LGuvb+f9vkSRXToDPGzrbx/sbGok pYvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=ViAFubID; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id u15-20020a170902e5cf00b001ce6693d6edsi8744811plf.370.2023.11.21.04.55.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:55:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=ViAFubID; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 8B59C80B01E9; Tue, 21 Nov 2023 04:52:12 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234229AbjKUMvu (ORCPT + 99 others); Tue, 21 Nov 2023 07:51:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233952AbjKUMvS (ORCPT ); Tue, 21 Nov 2023 07:51:18 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 731B910F8; Tue, 21 Nov 2023 04:51:10 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1F8F06607314; Tue, 21 Nov 2023 12:51:08 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571068; bh=P8X/98SRN6b58tyqRku7rqXinlOozOu5V7sRiK56qy0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ViAFubIDMIpRtDAs9VWbbuSobDzYbrb4oaI/Ozqt8FOV9mv26AuDFXqM2mK76IOUU Fu3pX8d5NKnDZkEN4nznxEyaVdLsReuQb5nL3EMQK6ua+KTLTx8ogveZSrurl2ZfRH 3AUh77aff/E/s4EV+w+LctagcInvhCO1tXtoi/kDJZmz/nzOFtDC4HuFX5wifFQ1DL O5OjPmGgpW8CIRjWkypSvvG7iNrxMFPk/N8PHbGIFZlgTrUpY1PVoX2sjnyFopseer dzDCi/84ynhKL4KUxeXk/P79MorKHZVOPieQexYcwlXL2h2ps59R3JDcPi11imLHKI +wbaCV2Kn2Wig== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 17/20] soc: mediatek: mtk-svs: Use ULONG_MAX to compare floor frequency Date: Tue, 21 Nov 2023 13:50:41 +0100 Message-ID: <20231121125044.78642-18-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:52:12 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178255216494736 X-GMAIL-MSGID: 1783178255216494736 The `freq` variable is of type unsigned long and, even though it does currently work with u32 because no frequency is higher than U32_MAX, it is not guaranteed that in the future we will see one. Initialize the freq variable with ULONG_MAX instead of U32_MAX. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 16a16c5a3f24..df39e7430ba9 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1804,7 +1804,7 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) return count; } - for (i = 0, freq = U32_MAX; i < svsb->opp_count; i++, freq--) { + for (i = 0, freq = ULONG_MAX; i < svsb->opp_count; i++, freq--) { opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); if (IS_ERR(opp)) { dev_err(svsb->dev, "cannot find freq = %ld\n", From patchwork Tue Nov 21 12:50:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167741 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp596098vqb; Tue, 21 Nov 2023 04:55:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IHI6xm2yya8gbQmMabBEty+xWxpu2ouX6TduNzITJmP1MtbSjxorllEDJPjvPN5vHNZ/EiS X-Received: by 2002:a05:6a00:451a:b0:6cb:6684:8d47 with SMTP id cw26-20020a056a00451a00b006cb66848d47mr7372183pfb.22.1700571310076; Tue, 21 Nov 2023 04:55:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571310; cv=none; d=google.com; s=arc-20160816; b=Hn8OuGrsvKfuGs+aLNKUIIYaKSYfMSMoAI8i/BaAdF0VGveF1wJ5DrJxEO97SCz4f6 XEab2YM8bLFiVNNXNpq2IXlgqrGBW/4pdce+1aYmmuOCiEZ8/11j9jEWQfRdcldD1oWR PmHvkU1pYecD/fwwvCtXUtiZFzc9q4IXmHJPSw5U6Z5aDNW6WK0vISRsTFAQ7iqvJH53 1h+4Z4bUZsZZJrIDYEhjdf9kqgM0xiE0NKbZJiK4ea8HdUdslQKfog1e8A8gD60yLff1 GBxzRWBTX1NzDJ/cqlmENdRxpYIZUNkdUHtRKAlb+xgdZ5/7j7gHksPhkeaCLxkv6FQh kHSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sIDX01elY0VncKtqRFRgMCTS5qeYDH3HPPgKV/efi9Q=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=uA9Fts88beCEnu/+1Bv3DCwm9j88J1Qg33sj/Q/SSI7ExPcIjNM/f/NzKwupW7Ulzu tcBS1yULRNW4WSD/7iS8AsTSgZj7mrzBQApPQTwM3kdFKkH3Mh+vK3gVIWgxiVS3UnMk 5xbyQsqy7t/A2VpY0A8gHM9BZZvyQwkIaHdZnZCVFjzm6tZ8VPIo9fmWKF45YjNDzEoT kixVl29tHfptsC07384hKA3Ql/MOxQa8bFiLd/Z7T1oWiof0jySaHq02lsZmkGcjnkfY ukG7OjNbreVN/9LqiRn9WGKcGuFD+3ZeaKCj7BxgwnsbURSgpmnLZk+9eIvtBF5tk28a zuag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b="QYJEk/aH"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id d2-20020a056a0024c200b006c0fe926fc9si10389343pfv.173.2023.11.21.04.55.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:55:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b="QYJEk/aH"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 88E0980C5929; Tue, 21 Nov 2023 04:52:29 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233923AbjKUMwE (ORCPT + 99 others); Tue, 21 Nov 2023 07:52:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234039AbjKUMva (ORCPT ); Tue, 21 Nov 2023 07:51:30 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 630821700; Tue, 21 Nov 2023 04:51:11 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 28B1C6607325; Tue, 21 Nov 2023 12:51:09 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571070; bh=mN7DiepfyFZ8SxB4d5o3jTkS/BkSU7UTWeZI7JlwaCQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QYJEk/aHzdsnoHVn9x5mLVjc29AZa8zodPrlK6E9GSSxGdMM6LOzyR9nN9Juz4rgA VyCeWmHqhE8+5C/3cdYxJ38m483BY33vXrbPLdGoIxyeDLjoGzHdrGwekgVU8vhyVq UI0QDW9CjXFopK2CeqE7Bkv0+u/fUKCfRloEDS+NG1F4r0V64hYXpalOhj1nW25Arb ly7CRhws46MI+dZ9/UMHRPhr/iL6puQLOoDgAkSYj2aMAL0rZDuVQC/fMJX9GPiJ9H NLqmvWbn+bEhZcieunLIsWeQ1W4747xp618Tvgy4ZIfbo6kQhg+zHI2hxlFXxTjLAM eHvLnFYJGU2TQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 18/20] soc: mediatek: mtk-svs: Constify runtime-immutable members of svs_bank Date: Tue, 21 Nov 2023 13:50:42 +0100 Message-ID: <20231121125044.78642-19-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:52:29 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178261966672323 X-GMAIL-MSGID: 1783178261966672323 Some members of struct svs_bank are not changed during runtime, so those are not variables but constants: move all of those to a new structure called svs_bank_pdata and refactor the code to make use of that and reorder members by size where possible. This effectively moves at least 50 bytes to the text segment. While at it, also uniform the thermal zone names across the banks. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 1204 +++++++++++++++++--------------- 1 file changed, 631 insertions(+), 573 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index df39e7430ba9..c832f5c670bc 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2022 MediaTek Inc. + * Copyright (C) 2022 Collabora Ltd. + * AngeloGioacchino Del Regno */ #include @@ -377,10 +379,10 @@ struct svs_fusemap { * @efuse_max: total number of svs efuse * @tefuse_max: total number of thermal efuse * @regs: svs platform registers map - * @bank_max: total number of svs banks * @efuse: svs efuse data received from NVMEM framework * @tefuse: thermal efuse data received from NVMEM framework * @ts_coeff: thermal sensors coefficient + * @bank_max: total number of svs banks */ struct svs_platform { void __iomem *base; @@ -391,10 +393,10 @@ struct svs_platform { size_t efuse_max; size_t tefuse_max; const u32 *regs; - u32 bank_max; u32 *efuse; u32 *tefuse; u32 ts_coeff; + u16 bank_max; }; struct svs_platform_data { @@ -404,59 +406,92 @@ struct svs_platform_data { int (*probe)(struct svs_platform *svsp); const struct svs_fusemap *glb_fuse_map; const u32 *regs; - u32 bank_max; u32 ts_coeff; + u16 bank_max; }; /** - * struct svs_bank - svs bank representation + * struct svs_bank_pdata - SVS Bank immutable config parameters * @dev_fuse_map: Bank fuse map data + * @buck_name: Regulator name + * @tzone_name: Thermal zone name + * @age_config: Bank age configuration + * @ctl0: TS-x selection + * @dc_config: Bank dc configuration + * @int_st: Bank interrupt identification + * @turn_freq_base: Reference frequency for 2-line turn point + * @tzone_htemp: Thermal zone high temperature threshold + * @tzone_ltemp: Thermal zone low temperature threshold + * @volt_step: Bank voltage step + * @volt_base: Bank voltage base + * @tzone_htemp_voffset: Thermal zone high temperature voltage offset + * @tzone_ltemp_voffset: Thermal zone low temperature voltage offset + * @chk_shift: Bank chicken shift + * @cpu_id: CPU core ID for SVS CPU bank use only + * @opp_count: Bank opp count + * @vboot: Voltage request for bank init01 only + * @vco: Bank VCO value + * @sw_id: Bank software identification + * @type: SVS Bank Type (1 or 2-line) and Role (high/low) + * @set_freq_pct: function pointer to set bank frequency percent table + * @get_volts: function pointer to get bank voltages + */ +struct svs_bank_pdata { + const struct svs_fusemap *dev_fuse_map; + char *buck_name; + char *tzone_name; + u32 age_config; + u32 ctl0; + u32 dc_config; + u32 int_st; + u32 turn_freq_base; + u32 tzone_htemp; + u32 tzone_ltemp; + u32 volt_step; + u32 volt_base; + u16 tzone_htemp_voffset; + u16 tzone_ltemp_voffset; + u8 chk_shift; + u8 cpu_id; + u8 opp_count; + u8 vboot; + u8 vco; + u8 sw_id; + u8 type; + + /* Callbacks */ + void (*set_freq_pct)(struct svs_platform *svsp, struct svs_bank *svsb); + void (*get_volts)(struct svs_platform *svsp, struct svs_bank *svsb); +}; + +/** + * struct svs_bank - svs bank representation + * @pdata: SVS Bank immutable config parameters * @dev: bank device * @opp_dev: device for opp table/buck control * @init_completion: the timeout completion for bank init * @buck: regulator used by opp_dev * @tzd: thermal zone device for getting temperature * @lock: mutex lock to protect voltage update process - * @set_freq_pct: function pointer to set bank frequency percent table - * @get_volts: function pointer to get bank voltages * @name: bank name - * @buck_name: regulator name - * @tzone_name: thermal zone name * @phase: bank current phase * @volt_od: bank voltage overdrive * @reg_data: bank register data in different phase for debug purpose * @pm_runtime_enabled_count: bank pm runtime enabled count - * @mode_support: bank mode support. + * @mode_support: bank mode support * @freq_base: reference frequency for bank init - * @turn_freq_base: refenrece frequency for 2-line turn point - * @vboot: voltage request for bank init01 only * @opp_dfreq: default opp frequency table * @opp_dvolt: default opp voltage table * @freq_pct: frequency percent table for bank init * @volt: bank voltage table - * @volt_step: bank voltage step - * @volt_base: bank voltage base * @volt_flags: bank voltage flags * @vmax: bank voltage maximum * @vmin: bank voltage minimum - * @age_config: bank age configuration * @age_voffset_in: bank age voltage offset - * @dc_config: bank dc configuration * @dc_voffset_in: bank dc voltage offset * @dvt_fixed: bank dvt fixed value - * @vco: bank VCO value - * @chk_shift: bank chicken shift * @core_sel: bank selection - * @opp_count: bank opp count - * @int_st: bank interrupt identification - * @sw_id: bank software identification - * @cpu_id: cpu core id for SVS CPU bank use only - * @ctl0: TS-x selection * @temp: bank temperature - * @tzone_htemp: thermal zone high temperature threshold - * @tzone_htemp_voffset: thermal zone high temperature voltage offset - * @tzone_ltemp: thermal zone low temperature threshold - * @tzone_ltemp_voffset: thermal zone low temperature voltage offset * @bts: svs efuse data * @mts: svs efuse data * @bdes: svs efuse data @@ -466,61 +501,41 @@ struct svs_platform_data { * @dcmdet: svs efuse data * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank * @vbin_turn_pt: voltage bin turn point helps know which svsb_volt should be overridden - * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank * - * Svs bank will generate suitalbe voltages by below general math equation + * Svs bank will generate suitable voltages by below general math equation * and provide these voltages to opp voltage table. * * opp_volt[i] = (volt[i] * volt_step) + volt_base; */ struct svs_bank { - const struct svs_fusemap *dev_fuse_map; + const struct svs_bank_pdata pdata; struct device *dev; struct device *opp_dev; struct completion init_completion; struct regulator *buck; struct thermal_zone_device *tzd; - struct mutex lock; /* lock to protect voltage update process */ - void (*set_freq_pct)(struct svs_platform *svsp, struct svs_bank *svsb); - void (*get_volts)(struct svs_platform *svsp, struct svs_bank *svsb); + struct mutex lock; + int pm_runtime_enabled_count; + short int volt_od; char *name; - char *buck_name; - char *tzone_name; enum svsb_phase phase; - short int volt_od; u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX]; - u32 pm_runtime_enabled_count; u8 mode_support; - u32 freq_base; - u32 turn_freq_base; - u8 vboot; u32 opp_dfreq[MAX_OPP_ENTRIES]; u32 opp_dvolt[MAX_OPP_ENTRIES]; u32 freq_pct[MAX_OPP_ENTRIES]; u32 volt[MAX_OPP_ENTRIES]; - u32 volt_step; - u32 volt_base; u32 volt_flags; - u8 vmax; - u8 vmin; - u32 age_config; + u32 freq_base; + u32 turn_pt; + u32 vbin_turn_pt; + u32 core_sel; + u32 temp; u16 age_voffset_in; - u32 dc_config; u16 dc_voffset_in; u8 dvt_fixed; - u8 vco; - u8 chk_shift; - u32 core_sel; - u8 opp_count; - u32 int_st; - u8 sw_id; - u8 cpu_id; - u32 ctl0; - u32 temp; - u32 tzone_htemp; - u16 tzone_htemp_voffset; - u32 tzone_ltemp; - u16 tzone_ltemp_voffset; + u8 vmax; + u8 vmin; u16 bts; u16 mts; u16 bdes; @@ -528,9 +543,6 @@ struct svs_bank { u8 mtdes; u8 dcbdet; u8 dcmdet; - u32 turn_pt; - u32 vbin_turn_pt; - u8 type; }; static u32 percent(u32 numerator, u32 denominator) @@ -572,10 +584,11 @@ static u32 svs_opp_volt_to_bank_volt(u32 opp_u_volt, u32 svsb_volt_step, static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb) { + const struct svs_bank_pdata *bdata = &svsb->pdata; struct dev_pm_opp *opp; u32 i, opp_u_volt; - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < bdata->opp_count; i++) { opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, svsb->opp_dfreq[i], true); @@ -587,8 +600,8 @@ static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb) opp_u_volt = dev_pm_opp_get_voltage(opp); svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt, - svsb->volt_step, - svsb->volt_base); + bdata->volt_step, + bdata->volt_base); dev_pm_opp_put(opp); } @@ -598,6 +611,7 @@ static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb) static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) { int ret = -EPERM, tzone_temp = 0; + const struct svs_bank_pdata *bdata = &svsb->pdata; u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop; mutex_lock(&svsb->lock); @@ -606,15 +620,15 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) * 2-line bank updates its corresponding opp volts. * 1-line bank updates all opp volts. */ - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { opp_start = 0; opp_stop = svsb->turn_pt; - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { opp_start = svsb->turn_pt; - opp_stop = svsb->opp_count; + opp_stop = bdata->opp_count; } else { opp_start = 0; - opp_stop = svsb->opp_count; + opp_stop = bdata->opp_count; } /* Get thermal effect */ @@ -623,20 +637,20 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && svsb->temp < SVSB_TEMP_LOWER_BOUND)) { dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n", - svsb->tzone_name, ret, svsb->temp); + bdata->tzone_name, ret, svsb->temp); svsb->phase = SVSB_PHASE_ERROR; } - if (tzone_temp >= svsb->tzone_htemp) - temp_voffset += svsb->tzone_htemp_voffset; - else if (tzone_temp <= svsb->tzone_ltemp) - temp_voffset += svsb->tzone_ltemp_voffset; + if (tzone_temp >= bdata->tzone_htemp) + temp_voffset += bdata->tzone_htemp_voffset; + else if (tzone_temp <= bdata->tzone_ltemp) + temp_voffset += bdata->tzone_ltemp_voffset; /* 2-line bank update all opp volts when running mon mode */ - if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_TYPE_HIGH || - svsb->type == SVSB_TYPE_LOW)) { + if (svsb->phase == SVSB_PHASE_MON && (bdata->type == SVSB_TYPE_HIGH || + bdata->type == SVSB_TYPE_LOW)) { opp_start = 0; - opp_stop = svsb->opp_count; + opp_stop = bdata->opp_count; } } @@ -653,8 +667,8 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) case SVSB_PHASE_MON: svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin); opp_volt = svs_bank_volt_to_opp_volt(svsb_volt, - svsb->volt_step, - svsb->volt_base); + bdata->volt_step, + bdata->volt_base); break; default: dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase); @@ -816,7 +830,7 @@ static int svs_status_debug_show(struct seq_file *m, void *v) svsb->name, tzone_temp, svsb->vbin_turn_pt, svsb->turn_pt); - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < svsb->pdata.opp_count; i++) { opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, svsb->opp_dfreq[i], true); if (IS_ERR(opp)) { @@ -923,9 +937,10 @@ static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx) static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *svsb) { + const struct svs_bank_pdata *bdata = &svsb->pdata; u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0; - u32 middle_index = (svsb->opp_count / 2); + u32 middle_index = (bdata->opp_count / 2); if (svsb->phase == SVSB_PHASE_MON && svsb->volt_flags & SVSB_MON_VOLT_IGNORE) @@ -936,7 +951,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv /* Target is to set svsb->volt[] by algorithm */ if (turn_pt < middle_index) { - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { /* volt[0] ~ volt[turn_pt - 1] */ for (i = 0; i < turn_pt; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); @@ -945,12 +960,12 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); shift_byte++; } - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ - j = svsb->opp_count - 7; + j = bdata->opp_count - 7; svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); shift_byte++; - for (i = j; i < svsb->opp_count; i++) { + for (i = j; i < bdata->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); vop = (shift_byte < REG_BYTES) ? &vop30 : &vop74; @@ -967,7 +982,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv svsb->freq_pct[i]); } } else { - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ j = turn_pt - 7; svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); @@ -987,9 +1002,9 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv svsb->volt[0], svsb->volt[j], svsb->freq_pct[i]); - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { /* volt[turn_pt] ~ volt[opp_count - 1] */ - for (i = turn_pt; i < svsb->opp_count; i++) { + for (i = turn_pt; i < bdata->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); vop = (shift_byte < REG_BYTES) ? &vop30 : &vop74; @@ -999,12 +1014,12 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv } } - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { opp_start = 0; opp_stop = svsb->turn_pt; - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { opp_start = svsb->turn_pt; - opp_stop = svsb->opp_count; + opp_stop = bdata->opp_count; } for (i = opp_start; i < opp_stop; i++) @@ -1014,11 +1029,11 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv /* For voltage bin support */ if (svsb->opp_dfreq[0] > svsb->freq_base) { svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], - svsb->volt_step, - svsb->volt_base); + bdata->volt_step, + bdata->volt_base); /* Find voltage bin turn point */ - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < bdata->opp_count; i++) { if (svsb->opp_dfreq[i] <= svsb->freq_base) { svsb->vbin_turn_pt = i; break; @@ -1037,12 +1052,13 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *svsb) { + const struct svs_bank_pdata *bdata = &svsb->pdata; u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0; u32 b_sft, shift_byte = 0, turn_pt; - u32 middle_index = (svsb->opp_count / 2); + u32 middle_index = (bdata->opp_count / 2); - for (i = 0; i < svsb->opp_count; i++) { - if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) { + for (i = 0; i < bdata->opp_count; i++) { + if (svsb->opp_dfreq[i] <= bdata->turn_freq_base) { svsb->turn_pt = i; break; } @@ -1052,7 +1068,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank /* Target is to fill out freq_pct74 / freq_pct30 by algorithm */ if (turn_pt < middle_index) { - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { /* * If we don't handle this situation, * SVSB_TYPE_HIGH's FREQPCT74 / FREQPCT30 would keep "0" @@ -1069,15 +1085,15 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *freq_pct |= (svsb->freq_pct[i] << b_sft); shift_byte++; } - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { /* * freq_pct[turn_pt] + * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] */ freq_pct30 = svsb->freq_pct[turn_pt]; shift_byte++; - j = svsb->opp_count - 7; - for (i = j; i < svsb->opp_count; i++) { + j = bdata->opp_count - 7; + for (i = j; i < bdata->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); freq_pct = (shift_byte < REG_BYTES) ? &freq_pct30 : &freq_pct74; @@ -1086,7 +1102,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank } } } else { - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { /* * freq_pct[0] + * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] @@ -1101,9 +1117,9 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *freq_pct |= (svsb->freq_pct[i] << b_sft); shift_byte++; } - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ - for (i = turn_pt; i < svsb->opp_count; i++) { + for (i = turn_pt; i < bdata->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); freq_pct = (shift_byte < REG_BYTES) ? &freq_pct30 : &freq_pct74; @@ -1119,6 +1135,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank static void svs_get_bank_volts_v2(struct svs_platform *svsp, struct svs_bank *svsb) { + const struct svs_bank_pdata *bdata = &svsb->pdata; u32 temp, i; temp = svs_readl_relaxed(svsp, VOP74); @@ -1146,17 +1163,17 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp, struct svs_bank *sv svsb->volt[14], svsb->freq_pct[15]); - for (i = 0; i < svsb->opp_count; i++) + for (i = 0; i < bdata->opp_count; i++) svsb->volt[i] += svsb->volt_od; /* For voltage bin support */ if (svsb->opp_dfreq[0] > svsb->freq_base) { svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], - svsb->volt_step, - svsb->volt_base); + bdata->volt_step, + bdata->volt_base); /* Find voltage bin turn point */ - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < bdata->opp_count; i++) { if (svsb->opp_dfreq[i] <= svsb->freq_base) { svsb->vbin_turn_pt = i; break; @@ -1196,6 +1213,7 @@ static void svs_set_bank_phase(struct svs_platform *svsp, enum svsb_phase target_phase) { struct svs_bank *svsb = &svsp->banks[bank_idx]; + const struct svs_bank_pdata *bdata = &svsb->pdata; u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs; svs_switch_bank(svsp, svsb); @@ -1204,7 +1222,7 @@ static void svs_set_bank_phase(struct svs_platform *svsp, FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes); svs_writel_relaxed(svsp, des_char, DESCHAR); - temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, svsb->vco) | + temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, bdata->vco) | FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) | FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed); svs_writel_relaxed(svsp, temp_char, TEMPCHAR); @@ -1213,11 +1231,11 @@ static void svs_set_bank_phase(struct svs_platform *svsp, FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet); svs_writel_relaxed(svsp, det_char, DETCHAR); - svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG); - svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG); + svs_writel_relaxed(svsp, bdata->dc_config, DCCONFIG); + svs_writel_relaxed(svsp, bdata->age_config, AGECONFIG); svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG); - svsb->set_freq_pct(svsp, svsb); + bdata->set_freq_pct(svsp, svsb); limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) | FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) | @@ -1227,13 +1245,13 @@ static void svs_set_bank_phase(struct svs_platform *svsp, svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW); svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG); - svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT); - svs_writel_relaxed(svsp, svsb->ctl0, CTL0); + svs_writel_relaxed(svsp, bdata->chk_shift, CHKSHIFT); + svs_writel_relaxed(svsp, bdata->ctl0, CTL0); svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); switch (target_phase) { case SVSB_PHASE_INIT01: - svs_writel_relaxed(svsp, svsb->vboot, VBOOT); + svs_writel_relaxed(svsp, bdata->vboot, VBOOT); svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN); svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN); break; @@ -1324,6 +1342,7 @@ static inline void svs_init02_isr_handler(struct svs_platform *svsp, unsigned short bank_idx) { struct svs_bank *svsb = &svsp->banks[bank_idx]; + const struct svs_bank_pdata *bdata = &svsb->pdata; dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", __func__, svs_readl_relaxed(svsp, VOP74), @@ -1333,7 +1352,7 @@ static inline void svs_init02_isr_handler(struct svs_platform *svsp, svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT02); svsb->phase = SVSB_PHASE_INIT02; - svsb->get_volts(svsp, svsb); + bdata->get_volts(svsp, svsb); svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS); @@ -1343,11 +1362,12 @@ static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp, unsigned short bank_idx) { struct svs_bank *svsb = &svsp->banks[bank_idx]; + const struct svs_bank_pdata *bdata = &svsb->pdata; svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_MON); svsb->phase = SVSB_PHASE_MON; - svsb->get_volts(svsp, svsb); + bdata->get_volts(svsp, svsb); svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS); @@ -1356,18 +1376,20 @@ static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp, static irqreturn_t svs_isr(int irq, void *data) { struct svs_platform *svsp = data; + const struct svs_bank_pdata *bdata; struct svs_bank *svsb = NULL; unsigned long flags; u32 idx, int_sts, svs_en; for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); spin_lock_irqsave(&svs_lock, flags); /* Find out which svs bank fires interrupt */ - if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) { + if (bdata->int_st & svs_readl_relaxed(svsp, INTST)) { spin_unlock_irqrestore(&svs_lock, flags); continue; } @@ -1412,6 +1434,7 @@ static bool svs_mode_available(struct svs_platform *svsp, u8 mode) static int svs_init01(struct svs_platform *svsp) { + const struct svs_bank_pdata *bdata; struct svs_bank *svsb; unsigned long flags, time_left; bool search_done; @@ -1427,6 +1450,7 @@ static int svs_init01(struct svs_platform *svsp) /* Svs bank init01 preparation - power enable */ for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; if (!(svsb->mode_support & SVSB_MODE_INIT01)) continue; @@ -1434,7 +1458,7 @@ static int svs_init01(struct svs_platform *svsp) ret = regulator_enable(svsb->buck); if (ret) { dev_err(svsb->dev, "%s enable fail: %d\n", - svsb->buck_name, ret); + bdata->buck_name, ret); goto svs_init01_resume_cpuidle; } @@ -1464,6 +1488,7 @@ static int svs_init01(struct svs_platform *svsp) */ for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; if (!(svsb->mode_support & SVSB_MODE_INIT01)) continue; @@ -1473,11 +1498,11 @@ static int svs_init01(struct svs_platform *svsp) * fix to that freq until svs_init01 is done. */ search_done = false; - opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, - svsb->volt_step, - svsb->volt_base); + opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot, + bdata->volt_step, + bdata->volt_base); - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < bdata->opp_count; i++) { opp_freq = svsb->opp_dfreq[i]; if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) { ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, @@ -1509,13 +1534,14 @@ static int svs_init01(struct svs_platform *svsp) /* Svs bank init01 begins */ for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; if (!(svsb->mode_support & SVSB_MODE_INIT01)) continue; - opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, - svsb->volt_step, - svsb->volt_base); + opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot, + bdata->volt_step, + bdata->volt_base); buck_volt = regulator_get_voltage(svsb->buck); if (buck_volt != opp_vboot) { @@ -1542,11 +1568,12 @@ static int svs_init01(struct svs_platform *svsp) svs_init01_finish: for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; if (!(svsb->mode_support & SVSB_MODE_INIT01)) continue; - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < bdata->opp_count; i++) { r = dev_pm_opp_enable(svsb->opp_dev, svsb->opp_dfreq[i]); if (r) @@ -1572,7 +1599,7 @@ static int svs_init01(struct svs_platform *svsp) r = regulator_disable(svsb->buck); if (r) dev_err(svsb->dev, "%s disable fail: %d\n", - svsb->buck_name, r); + bdata->buck_name, r); } svs_init01_resume_cpuidle: @@ -1583,6 +1610,7 @@ static int svs_init01(struct svs_platform *svsp) static int svs_init02(struct svs_platform *svsp) { + const struct svs_bank_pdata *bdata; struct svs_bank *svsb; unsigned long flags, time_left; int ret; @@ -1618,11 +1646,12 @@ static int svs_init02(struct svs_platform *svsp) */ for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; if (!(svsb->mode_support & SVSB_MODE_INIT02)) continue; - if (svsb->type == SVSB_TYPE_HIGH || svsb->type == SVSB_TYPE_LOW) { + if (bdata->type == SVSB_TYPE_HIGH || bdata->type == SVSB_TYPE_LOW) { if (svs_sync_bank_volts_from_opp(svsb)) { dev_err(svsb->dev, "sync volt fail\n"); ret = -EPERM; @@ -1680,12 +1709,12 @@ static int svs_start(struct svs_platform *svsp) static int svs_suspend(struct device *dev) { struct svs_platform *svsp = dev_get_drvdata(dev); - struct svs_bank *svsb; int ret; u32 idx; for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; + struct svs_bank *svsb = &svsp->banks[idx]; + svs_bank_disable_and_restore_default_volts(svsp, svsb); } @@ -1736,6 +1765,7 @@ static int svs_resume(struct device *dev) static int svs_bank_resource_setup(struct svs_platform *svsp) { + const struct svs_bank_pdata *bdata; struct svs_bank *svsb; struct dev_pm_opp *opp; unsigned long freq; @@ -1746,8 +1776,9 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; - if (svsb->sw_id >= SVSB_SWID_MAX || svsb->type >= SVSB_TYPE_MAX) { + if (bdata->sw_id >= SVSB_SWID_MAX || bdata->type >= SVSB_TYPE_MAX) { dev_err(svsb->dev, "unknown bank sw_id or type\n"); return -EINVAL; } @@ -1757,8 +1788,8 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) return -ENOMEM; svsb->name = devm_kasprintf(svsp->dev, GFP_KERNEL, "%s%s", - svs_swid_names[svsb->sw_id], - svs_type_names[svsb->type]); + svs_swid_names[bdata->sw_id], + svs_type_names[bdata->type]); if (!svsb->name) return -ENOMEM; @@ -1779,32 +1810,32 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) if (svsb->mode_support & SVSB_MODE_INIT01) { svsb->buck = devm_regulator_get_optional(svsb->opp_dev, - svsb->buck_name); + bdata->buck_name); if (IS_ERR(svsb->buck)) { dev_err(svsb->dev, "cannot get \"%s-supply\"\n", - svsb->buck_name); + bdata->buck_name); return PTR_ERR(svsb->buck); } } - if (!IS_ERR_OR_NULL(svsb->tzone_name)) { - svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name); + if (!IS_ERR_OR_NULL(bdata->tzone_name)) { + svsb->tzd = thermal_zone_get_zone_by_name(bdata->tzone_name); if (IS_ERR(svsb->tzd)) { dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", - svsb->tzone_name); + bdata->tzone_name); return PTR_ERR(svsb->tzd); } } count = dev_pm_opp_get_opp_count(svsb->opp_dev); - if (svsb->opp_count != count) { + if (bdata->opp_count != count) { dev_err(svsb->dev, "opp_count not \"%u\" but get \"%d\"?\n", - svsb->opp_count, count); + bdata->opp_count, count); return count; } - for (i = 0, freq = ULONG_MAX; i < svsb->opp_count; i++, freq--) { + for (i = 0, freq = ULONG_MAX; i < bdata->opp_count; i++, freq--) { opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); if (IS_ERR(opp)) { dev_err(svsb->dev, "cannot find freq = %ld\n", @@ -1901,7 +1932,8 @@ static bool svs_common_parse_efuse(struct svs_platform *svsp, for (i = 0; i < svsp->bank_max; i++) { struct svs_bank *svsb = &svsp->banks[i]; - const struct svs_fusemap *dfmap = svsb->dev_fuse_map; + const struct svs_bank_pdata *bdata = &svsb->pdata; + const struct svs_fusemap *dfmap = bdata->dev_fuse_map; if (vmin == 1) svsb->vmin = 0x1e; @@ -1927,11 +1959,11 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, const struct svs_platform_data *pdata) { struct svs_bank *svsb; + const struct svs_bank_pdata *bdata; int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0; int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t; int o_slope, o_slope_sign, ts_id; u32 idx, i, ft_pgm, mts, temp0, temp1, temp2; - int ret; for (i = 0; i < svsp->efuse_max; i++) if (svsp->efuse[i]) @@ -1948,7 +1980,8 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; - const struct svs_fusemap *dfmap = svsb->dev_fuse_map; + bdata = &svsb->pdata; + const struct svs_fusemap *dfmap = bdata->dev_fuse_map; if (ft_pgm <= 1) svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; @@ -1959,7 +1992,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8); svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8); - switch (svsb->sw_id) { + switch (bdata->sw_id) { case SVSB_SWID_CPU_LITTLE: case SVSB_SWID_CCI: if (ft_pgm <= 3) @@ -2044,9 +2077,10 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; svsb->mts = mts; - switch (svsb->sw_id) { + switch (bdata->sw_id) { case SVSB_SWID_CPU_LITTLE: tb_roomt = x_roomt[3]; break; @@ -2060,7 +2094,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, tb_roomt = x_roomt[1]; break; default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); goto remove_mt8183_svsb_mon_mode; } @@ -2147,24 +2181,24 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) for (idx = 0; idx < svsp->bank_max; idx++) { struct svs_bank *svsb = &svsp->banks[idx]; + const struct svs_bank_pdata *bdata = &svsb->pdata; - switch (svsb->sw_id) { + switch (bdata->sw_id) { case SVSB_SWID_CPU_LITTLE: case SVSB_SWID_CPU_BIG: - svsb->opp_dev = get_cpu_device(svsb->cpu_id); + svsb->opp_dev = get_cpu_device(bdata->cpu_id); break; case SVSB_SWID_CCI: svsb->opp_dev = svs_add_device_link(svsp, "cci"); break; case SVSB_SWID_GPU: - if (svsb->type == SVSB_TYPE_LOW) + if (bdata->type == SVSB_TYPE_LOW) svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); else svsb->opp_dev = svs_add_device_link(svsp, "gpu"); break; - break; default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); return -EINVAL; } @@ -2180,7 +2214,6 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) static int svs_mt8183_platform_probe(struct svs_platform *svsp) { struct device *dev; - struct svs_bank *svsb; u32 idx; dev = svs_add_device_link(svsp, "thermal-sensor"); @@ -2189,12 +2222,13 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) "failed to get thermal device\n"); for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; + struct svs_bank *svsb = &svsp->banks[idx]; + const struct svs_bank_pdata *bdata = &svsb->pdata; - switch (svsb->sw_id) { + switch (bdata->sw_id) { case SVSB_SWID_CPU_LITTLE: case SVSB_SWID_CPU_BIG: - svsb->opp_dev = get_cpu_device(svsb->cpu_id); + svsb->opp_dev = get_cpu_device(bdata->cpu_id); break; case SVSB_SWID_CCI: svsb->opp_dev = svs_add_device_link(svsp, "cci"); @@ -2203,7 +2237,7 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) svsb->opp_dev = svs_add_device_link(svsp, "gpu"); break; default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); return -EINVAL; } @@ -2218,463 +2252,486 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) static struct svs_bank svs_mt8195_banks[] = { { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_LOW, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, - .mode_support = SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 640000000, - .turn_freq_base = 640000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x38, - .vmin = 0x14, - .age_config = 0x555555, - .dc_config = 0x1, - .dvt_fixed = 0x1, - .vco = 0x18, - .chk_shift = 0x87, - .core_sel = 0x0fff0100, - .int_st = BIT(0), - .ctl0 = 0x00540003, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 10, 16 }, { 10, 24 }, { 10, 0 }, { 8, 0 }, { 8, 8 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .int_st = BIT(0), + .ctl0 = 0x00540003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 10, 16 }, { 10, 24 }, { 10, 0 }, { 8, 0 }, { 8, 8 } + } + }, + .mode_support = SVSB_MODE_INIT02, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .freq_base = 640000000, + .core_sel = 0x0fff0100, + .dvt_fixed = 0x1, + .vmax = 0x38, + .vmin = 0x14, }, { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_HIGH, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .tzone_name = "gpu1", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 880000000, - .turn_freq_base = 640000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x38, - .vmin = 0x14, - .age_config = 0x555555, - .dc_config = 0x1, - .dvt_fixed = 0x6, - .vco = 0x18, - .chk_shift = 0x87, - .core_sel = 0x0fff0101, - .int_st = BIT(1), - .ctl0 = 0x00540003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 0, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 7, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 9, 16 }, { 9, 24 }, { 9, 0 }, { 8, 0 }, { 8, 8 } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 9, 16 }, { 9, 24 }, { 9, 0 }, { 8, 0 }, { 8, 8 } + }, }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 880000000, + .core_sel = 0x0fff0101, + .dvt_fixed = 0x6, + .vmax = 0x38, + .vmin = 0x14, }, }; static struct svs_bank svs_mt8192_banks[] = { { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_LOW, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .tzone_name = "gpu1", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, - .mode_support = SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 688000000, - .turn_freq_base = 688000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x60, - .vmin = 0x1a, - .age_config = 0x555555, - .dc_config = 0x1, - .dvt_fixed = 0x1, - .vco = 0x18, - .chk_shift = 0x87, - .core_sel = 0x0fff0100, - .int_st = BIT(0), - .ctl0 = 0x00540003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 0, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 7, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 10, 16 }, { 10, 24 }, { 10, 0 }, { 17, 0 }, { 17, 8 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 688000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .int_st = BIT(0), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 10, 16 }, { 10, 24 }, { 10, 0 }, { 17, 0 }, { 17, 8 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support = SVSB_MODE_INIT02, + .freq_base = 688000000, + .core_sel = 0x0fff0100, + .dvt_fixed = 0x1, + .vmax = 0x60, + .vmin = 0x1a, }, { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_HIGH, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .tzone_name = "gpu1", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 902000000, - .turn_freq_base = 688000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x60, - .vmin = 0x1a, - .age_config = 0x555555, - .dc_config = 0x1, - .dvt_fixed = 0x6, - .vco = 0x18, - .chk_shift = 0x87, - .core_sel = 0x0fff0101, - .int_st = BIT(1), - .ctl0 = 0x00540003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 0, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 7, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 9, 16 }, { 9, 24 }, { 17, 0 }, { 17, 16 }, { 17, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 688000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 9, 16 }, { 9, 24 }, { 17, 0 }, { 17, 16 }, { 17, 24 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 902000000, + .core_sel = 0x0fff0101, + .dvt_fixed = 0x6, + .vmax = 0x60, + .vmin = 0x1a, }, }; static struct svs_bank svs_mt8188_banks[] = { { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_LOW, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, - .mode_support = SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 640000000, - .turn_freq_base = 640000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x38, - .vmin = 0x1c, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x1, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0000, - .int_st = BIT(0), - .ctl0 = 0x00100003, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(0), + .ctl0 = 0x00100003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support = SVSB_MODE_INIT02, + .freq_base = 640000000, + .core_sel = 0x0fff0000, + .dvt_fixed = 0x1, + .vmax = 0x38, + .vmin = 0x1c, }, { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_HIGH, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .tzone_name = "gpu1", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 880000000, - .turn_freq_base = 640000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x38, - .vmin = 0x1c, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x4, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0001, - .int_st = BIT(1), - .ctl0 = 0x00100003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 0, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 7, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(1), + .ctl0 = 0x00100003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 880000000, + .core_sel = 0x0fff0001, + .dvt_fixed = 0x4, + .vmax = 0x38, + .vmin = 0x1c, }, }; static struct svs_bank svs_mt8186_banks[] = { { - .sw_id = SVSB_SWID_CPU_BIG, - .type = SVSB_TYPE_LOW, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .cpu_id = 6, - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, - .mode_support = SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 1670000000, - .turn_freq_base = 1670000000, - .volt_step = 6250, - .volt_base = 400000, - .volt_od = 4, - .vmax = 0x59, - .vmin = 0x20, - .age_config = 0x1, - .dc_config = 0x1, - .dvt_fixed = 0x3, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0100, - .int_st = BIT(0), - .ctl0 = 0x00540003, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 3, 16 }, { 3, 24 }, { 3, 0 }, { 14, 16 }, { 14, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CPU_BIG, + .type = SVSB_TYPE_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .cpu_id = 6, + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 1670000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x1, + .dc_config = 0x1, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(0), + .ctl0 = 0x00540003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 3, 16 }, { 3, 24 }, { 3, 0 }, { 14, 16 }, { 14, 24 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .volt_od = 4, + .mode_support = SVSB_MODE_INIT02, + .freq_base = 1670000000, + .core_sel = 0x0fff0100, + .dvt_fixed = 0x3, + .vmax = 0x59, + .vmin = 0x20, }, { - .sw_id = SVSB_SWID_CPU_BIG, - .type = SVSB_TYPE_HIGH, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .cpu_id = 6, - .tzone_name = "cpu_big0", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 2050000000, - .turn_freq_base = 1670000000, - .volt_step = 6250, - .volt_base = 400000, - .volt_od = 4, - .vmax = 0x73, - .vmin = 0x20, - .age_config = 0x1, - .dc_config = 0x1, - .dvt_fixed = 0x6, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0101, - .int_st = BIT(1), - .ctl0 = 0x00540003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 8, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 8, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 2, 16 }, { 2, 24 }, { 2, 0 }, { 13, 0 }, { 13, 8 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CPU_BIG, + .type = SVSB_TYPE_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .cpu_id = 6, + .tzone_name = "cpu-big", + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 1670000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x1, + .dc_config = 0x1, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 2, 16 }, { 2, 24 }, { 2, 0 }, { 13, 0 }, { 13, 8 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .volt_od = 4, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 2050000000, + .core_sel = 0x0fff0101, + .dvt_fixed = 0x6, + .vmax = 0x73, + .vmin = 0x20, }, { - .sw_id = SVSB_SWID_CPU_LITTLE, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .cpu_id = 0, - .tzone_name = "cpu_zone0", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 2000000000, - .volt_step = 6250, - .volt_base = 400000, - .volt_od = 3, - .vmax = 0x65, - .vmin = 0x20, - .age_config = 0x1, - .dc_config = 0x1, - .dvt_fixed = 0x6, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0102, - .int_st = BIT(2), - .ctl0 = 0x3210000f, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 8, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 8, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CPU_LITTLE, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .cpu_id = 0, + .tzone_name = "cpu-little", + .opp_count = MAX_OPP_ENTRIES, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x1, + .dc_config = 0x1, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(2), + .ctl0 = 0x3210000f, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .volt_od = 3, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 2000000000, + .core_sel = 0x0fff0102, + .dvt_fixed = 0x6, + .vmax = 0x65, + .vmin = 0x20, }, { - .sw_id = SVSB_SWID_CCI, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .tzone_name = "cpu_zone0", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 1400000000, - .volt_step = 6250, - .volt_base = 400000, - .volt_od = 3, - .vmax = 0x65, - .vmin = 0x20, - .age_config = 0x1, - .dc_config = 0x1, - .dvt_fixed = 0x6, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0103, - .int_st = BIT(3), - .ctl0 = 0x3210000f, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 8, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 8, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CCI, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .tzone_name = "cci", + .opp_count = MAX_OPP_ENTRIES, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x1, + .dc_config = 0x1, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(3), + .ctl0 = 0x3210000f, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .volt_od = 3, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 1400000000, + .core_sel = 0x0fff0103, + .dvt_fixed = 0x6, + .vmax = 0x65, + .vmin = 0x20, }, { - .sw_id = SVSB_SWID_GPU, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .tzone_name = "mfg", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 850000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x58, - .vmin = 0x20, - .age_config = 0x555555, - .dc_config = 0x1, - .dvt_fixed = 0x4, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0104, - .int_st = BIT(4), - .ctl0 = 0x00100003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 8, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 7, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 6, 16 }, { 6, 24 }, { 6, 0 }, { 15, 8 }, { 15, 0 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x1, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(4), + .ctl0 = 0x00100003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 6, 16 }, { 6, 24 }, { 6, 0 }, { 15, 8 }, { 15, 0 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 850000000, + .core_sel = 0x0fff0104, + .dvt_fixed = 0x4, + .vmax = 0x58, + .vmin = 0x20, }, }; static struct svs_bank svs_mt8183_banks[] = { { - .sw_id = SVSB_SWID_CPU_LITTLE, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .cpu_id = 0, - .buck_name = "proc", - .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 1989000000, - .vboot = 0x30, - .volt_step = 6250, - .volt_base = 500000, - .vmax = 0x64, - .vmin = 0x18, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x7, - .vco = 0x10, - .chk_shift = 0x77, - .core_sel = 0x8fff0000, - .int_st = BIT(0), - .ctl0 = 0x00010001, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 16, 0 }, { 16, 8 }, { 17, 16 }, { 16, 16 }, { 16, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CPU_LITTLE, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .cpu_id = 0, + .buck_name = "proc", + .opp_count = MAX_OPP_ENTRIES, + .vboot = 0x30, + .volt_step = 6250, + .volt_base = 500000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x77, + .int_st = BIT(0), + .ctl0 = 0x00010001, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 16, 0 }, { 16, 8 }, { 17, 16 }, { 16, 16 }, { 16, 24 } + } + }, + .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, + .freq_base = 1989000000, + .core_sel = 0x8fff0000, + .dvt_fixed = 0x7, + .vmax = 0x64, + .vmin = 0x18, + }, { - .sw_id = SVSB_SWID_CPU_BIG, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .cpu_id = 4, - .buck_name = "proc", - .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 1989000000, - .vboot = 0x30, - .volt_step = 6250, - .volt_base = 500000, - .vmax = 0x58, - .vmin = 0x10, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x7, - .vco = 0x10, - .chk_shift = 0x77, - .core_sel = 0x8fff0001, - .int_st = BIT(1), - .ctl0 = 0x00000001, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 18, 0 }, { 18, 8 }, { 17, 0 }, { 18, 16 }, { 18, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CPU_BIG, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .cpu_id = 4, + .buck_name = "proc", + .opp_count = MAX_OPP_ENTRIES, + .vboot = 0x30, + .volt_step = 6250, + .volt_base = 500000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x77, + .int_st = BIT(1), + .ctl0 = 0x00000001, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 18, 0 }, { 18, 8 }, { 17, 0 }, { 18, 16 }, { 18, 24 } + } + }, + .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, + .freq_base = 1989000000, + .core_sel = 0x8fff0001, + .dvt_fixed = 0x7, + .vmax = 0x58, + .vmin = 0x10, + }, { - .sw_id = SVSB_SWID_CCI, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .buck_name = "proc", - .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 1196000000, - .vboot = 0x30, - .volt_step = 6250, - .volt_base = 500000, - .vmax = 0x64, - .vmin = 0x18, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x7, - .vco = 0x10, - .chk_shift = 0x77, - .core_sel = 0x8fff0002, - .int_st = BIT(2), - .ctl0 = 0x00100003, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 4, 0 }, { 4, 8 }, { 5, 16 }, { 4, 16 }, { 4, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CCI, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .buck_name = "proc", + .opp_count = MAX_OPP_ENTRIES, + .vboot = 0x30, + .volt_step = 6250, + .volt_base = 500000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x77, + .int_st = BIT(2), + .ctl0 = 0x00100003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 0 }, { 4, 8 }, { 5, 16 }, { 4, 16 }, { 4, 24 } + } + }, + .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, + .freq_base = 1196000000, + .core_sel = 0x8fff0002, + .dvt_fixed = 0x7, + .vmax = 0x64, + .vmin = 0x18, }, { - .sw_id = SVSB_SWID_GPU, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .buck_name = "mali", - .tzone_name = "tzts2", - .volt_flags = SVSB_INIT01_PD_REQ | - SVSB_INIT01_VOLT_INC_ONLY, - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | - SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 900000000, - .vboot = 0x30, - .volt_step = 6250, - .volt_base = 500000, - .vmax = 0x40, - .vmin = 0x14, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x3, - .vco = 0x10, - .chk_shift = 0x77, - .core_sel = 0x8fff0003, - .int_st = BIT(3), - .ctl0 = 0x00050001, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 0, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 3, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 6, 0 }, { 6, 8 }, { 5, 0 }, { 6, 16 }, { 6, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .buck_name = "mali", + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .vboot = 0x30, + .volt_step = 6250, + .volt_base = 500000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x77, + .int_st = BIT(3), + .ctl0 = 0x00050001, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 3, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 6, 0 }, { 6, 8 }, { 5, 0 }, { 6, 16 }, { 6, 24 } + } + }, + .volt_flags = SVSB_INIT01_PD_REQ | SVSB_INIT01_VOLT_INC_ONLY, + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 900000000, + .core_sel = 0x8fff0003, + .dvt_fixed = 0x3, + .vmax = 0x40, + .vmin = 0x14, }, }; @@ -2874,5 +2931,6 @@ static struct platform_driver svs_driver = { module_platform_driver(svs_driver); MODULE_AUTHOR("Roger Lu "); +MODULE_AUTHOR("AngeloGioacchino Del Regno "); MODULE_DESCRIPTION("MediaTek SVS driver"); MODULE_LICENSE("GPL"); From patchwork Tue Nov 21 12:50:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167740 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp596065vqb; Tue, 21 Nov 2023 04:55:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IERqfkGAZFwnhvJ0++I4WTZuY2dyLcV7wZ9JvWSkV/rZZuVfCfhLwM4P35ZktMsIqLSqMoK X-Received: by 2002:a17:90b:1f83:b0:27d:549b:3e65 with SMTP id so3-20020a17090b1f8300b0027d549b3e65mr8296597pjb.49.1700571305357; Tue, 21 Nov 2023 04:55:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571305; cv=none; d=google.com; s=arc-20160816; b=WLXJ10IXq+GWp1/qAc+Lt2m0cweShPakVkhQCCNM1Lgu8IdpmRl/Vd1pU+cO4f625b zxuMUSpo2iaVcV73JV3G7rBswYW5jgwxVHH0FTU8oOv91b8ku8IAiRDte8ubrE+X7mig +HSbg+GaidHlJoDzXBEvsW2wR8b3v4gHFwgCRIhg5Yg6IvdW24vWalqkT5147aHqfXeG gs9PPEdU6OfQROvU9IWPXW+YYoRVIe7Eqam24FfLuU4RL68mqJ9G5C3Z5kLJgKh+TWbT 7O2yVhxEMyysNn+r1+IQkcXboit63IBlN51TUbaPPjrPWL9JEnoihd3b69HaYgvdUOX4 hGVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g/wsfGTD4qIPzV9aYVLPlzsDTVh1NFbKfRsNkAhi+fc=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=ke2Q2SgCsQF1WUM5v/EFnCr1cAYYapi8uvDT5ODxPfthhNgKSipjvDGMoRXIMQPtN6 okW/Q6AYpoUvSpOv60toa5AUB89l+dFxphn48IEdWACzFfknQ8iAcZtw/m/AXUs9u7KE Y38qK2vNT4No0bZxbnRLs/ZFKiMnMth6/sTX4rKu1+MP4asyQ9MtbunG6p1uxSyBZABl 6DI2mxDjF8IhlsaWuHwseo1sctxqyhmizLMMtzCJgD7TxaQjNzg1Y/cvJGAiZUsHrxLI udqbs8uaRl5et1Aup/qVU8ECVrEPAkrD9ldKfckmD+0czg4VrZKjuOdLHxweDlQwWqSd D+8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=U28OlFbj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id u5-20020a17090a890500b002802928e7cesi10261202pjn.147.2023.11.21.04.55.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:55:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=U28OlFbj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 483FF803E480; Tue, 21 Nov 2023 04:52:15 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233882AbjKUMwA (ORCPT + 99 others); Tue, 21 Nov 2023 07:52:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234004AbjKUMv0 (ORCPT ); Tue, 21 Nov 2023 07:51:26 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E0D31A2; Tue, 21 Nov 2023 04:51:12 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 33FE86607323; Tue, 21 Nov 2023 12:51:10 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571071; bh=7Is9gmN9hkuGxy+sJrNkxtzwuNgilsJCxJ9IKhqUks4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U28OlFbjZWTNhHg7n02D3GbangEkkeyjxK6DU74A/EClsB8By4WT4sVVfgxWsgp3u K3PtCRCEyErdirpchxpVdaWmOgv0zH+J0EmCwQuYpLgJcBrke4Mw+D9uhcXDecYtpY mlMLS5/O4qI3dags8d5kyl5Z0epQKWQWukwIUm64L13KO1/KqDGEIXS1VRy6izcmV0 oNIkmKGEf3NXQ93+nrzm1qNF9qjKBQFhVvK50btDkoae3Oukd9GwDRNA5DI00Cznj8 lACrjJWfQl4wwVAw9ShgaRj+TGGekYNij6Xf72WugNXe4u+0U4vGhjzhVD5VVjVveB raH7B/hYytneQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 19/20] arm64: dts: mediatek: mt8192: Add Smart Voltage Scaling node Date: Tue, 21 Nov 2023 13:50:43 +0100 Message-ID: <20231121125044.78642-20-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:52:15 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178256774442160 X-GMAIL-MSGID: 1783178256774442160 Add the MediaTek SVS node: this will lower the voltage of various components of the SoC based on chip quality (read from fuses) in order to save power and generate less heat. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 238f6eb25832..6dd32dbfb832 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -809,6 +809,18 @@ lvts_ap: thermal-sensor@1100b000 { #thermal-sensor-cells = <1>; }; + svs: svs@1100bc00 { + compatible = "mediatek,mt8192-svs"; + reg = <0 0x1100bc00 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, <&lvts_e_data1>; + nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; + resets = <&infracfg MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST>; + reset-names = "svs_rst"; + }; + pwm0: pwm@1100e000 { compatible = "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; From patchwork Tue Nov 21 12:50:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167729 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp594899vqb; Tue, 21 Nov 2023 04:52:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IHilqdKvRkeWcMo1n3XDm0/qyQaa+3yMGjMwot1+pJIkaWjnZRvfbuBJrz4mgQCR2qllnv+ X-Received: by 2002:a05:6a00:2410:b0:6bd:7cbd:15a2 with SMTP id z16-20020a056a00241000b006bd7cbd15a2mr8472776pfh.26.1700571161809; Tue, 21 Nov 2023 04:52:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700571161; cv=none; d=google.com; s=arc-20160816; b=xt5yB/scoPPUfbnBLqF5DqZaWemRqTi/gTWUhbNdZekNEiVekqs7M88gI9wB0cAWfJ f3be35r7kumuUHsn5zyDkTxQ6czgAmDLgrI2nU68EmMySXsJEmekmo01c4q0qeVPJzb/ KoYlAmOgQMXb/DaJa1gNQiPSkOiOWYi7/u3ZpKe5cRMxtU1zXVzpFPDfTbEJhjv2yoWo r9vsD9x0UjqJBRGsQKP5JNg5+pdk1LhsG7zwy9vwntPROVUIbWcoNBsuzj4tjWllWBF8 7JWzeOIU4YAIowplhbeHNMeemn58R4LZRFpMcW8YbDXGJ82g7/3i07n9kKarNYnJJnry ay7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2nSvjwhp8KEX+f10c8PjMOZ1/nuFqQp7c5iuH1zb1GM=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=ejtfLaDhCRTE0HdehVtBJ8preOpWqbhckGAdb3ZvbfaX6ySfXOTcZsIbG2TsqXxKqw v716+98X1HmjLD8HC4WeVhZdhIK56M9Su9CjQTLSMyTup3hSfnf5XTOI4DzI6NFcky11 Q+7BpnTS9f4xzABHPUjeRGcKlU8F+kGhcey4cX0EARWcbVYLYF+TgdPN/0RoLztpPbCg 54O7kY+9TE/Bc8Mp8nL2bJtRal2oFxYc3lwi5Noc+TTWJtdkBZkfEAq2kF/2MLZcvKk2 EPiCF+pTcNQMXxndvYq5KUe3IMOGWmiPLWRpylRvUBx26woU3lIZcYatDjAo3hOYa2LI hCJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=gTH53GTf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id by36-20020a056a0205a400b005b7fb04f1f9si11157694pgb.734.2023.11.21.04.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:52:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=gTH53GTf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 8A039802642B; Tue, 21 Nov 2023 04:52:16 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234037AbjKUMwC (ORCPT + 99 others); Tue, 21 Nov 2023 07:52:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234026AbjKUMva (ORCPT ); Tue, 21 Nov 2023 07:51:30 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5ED8CD71; Tue, 21 Nov 2023 04:51:13 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3748F6607319; Tue, 21 Nov 2023 12:51:11 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571072; bh=6uV/aa1GXqZk9w0ZoiU/aw6OTSIwDj0KZLX0pQNrucc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gTH53GTfmI0yj69H84sNUw/o1GfBc0RPwtqU956LSEUYkdzVdK+rs6Vxzt4jmo5VW gaquzXsQFkH/PivbRg+Ug2iCwrqiIPhi2cE6exT3izeEzH6HpR5CT5xCfMC3t9sL6U 9g6pZu2nHjuKUY44UEuOcCoBErJG4TKWf1HFjR9mvM1KBEV93hgEr12hIfuOQdy+vs x5FY4Pj/4SUGn9WPtpt3s3JWy6p8eSOLGDwdu2e9YOCgAptH4gq4h9ULFxdqGA25UZ pcJojGZkWJCltiCsOH+g3EvBx7muBViZzmGvX6KjkacPQ0sBypAaGn3C8H/kFPkGv8 Xdcb0wBIOsO/g== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 20/20] arm64: dts: mediatek: mt8195: Add SVS node and reduce LVTS_AP iospace Date: Tue, 21 Nov 2023 13:50:44 +0100 Message-ID: <20231121125044.78642-21-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 21 Nov 2023 04:52:16 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783178106484087745 X-GMAIL-MSGID: 1783178106484087745 Add the MediaTek SVS node: this will lower the voltage of various components of the SoC based on chip quality (read from fuses) in order to save power and generate less heat. Also, reduce the LVTS_AP iospace to 0xc00, because that's exactly where SVS starts. - LVTS_AP start: 0x1100b000 length: 0xc00 - SVS start: 0x1100bc00 length: 0x400 Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 54c674c45b49..54debd4cf8e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1115,7 +1115,7 @@ spi0: spi@1100a000 { lvts_ap: thermal-sensor@1100b000 { compatible = "mediatek,mt8195-lvts-ap"; - reg = <0 0x1100b000 0 0x1000>; + reg = <0 0x1100b000 0 0xc00>; interrupts = ; clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; @@ -1124,6 +1124,18 @@ lvts_ap: thermal-sensor@1100b000 { #thermal-sensor-cells = <1>; }; + svs: svs@1100bc00 { + compatible = "mediatek,mt8195-svs"; + reg = <0 0x1100bc00 0 0x400>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calib_data &lvts_efuse_data1>; + nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; + resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>; + reset-names = "svs_rst"; + }; + disp_pwm0: pwm@1100e000 { compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; @@ -1682,6 +1694,9 @@ lvts_efuse_data1: lvts1-calib@1bc { lvts_efuse_data2: lvts2-calib@1d0 { reg = <0x1d0 0x38>; }; + svs_calib_data: svs-calib@580 { + reg = <0x580 0x64>; + }; }; u3phy2: t-phy@11c40000 {