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[23.128.96.38]) by mx.google.com with ESMTPS id i11-20020a17090ad34b00b002851532df34si6256210pjx.131.2023.11.21.03.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:57:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=czeauBKl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 413F3802B81B; Tue, 21 Nov 2023 03:57:05 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234593AbjKUL46 (ORCPT + 99 others); Tue, 21 Nov 2023 06:56:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234686AbjKUL4l (ORCPT ); Tue, 21 Nov 2023 06:56:41 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E759018F; Tue, 21 Nov 2023 03:56:34 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0C4B566072F6; Tue, 21 Nov 2023 11:56:31 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567792; bh=sMWHddCvw/Ujx/UtO/I5fhryZnx4605LdfFnzpLxwHk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=czeauBKlRlF/wJqxiNf1ks8mQDJ3NbIxGr2qzb3Qbway6mD3g5YCjbOqTMfNRNC6Q s/nyCzzcdYxV9I4+wxsZI2AcmKXeXFVRbyzAk7dQLZNb8NospAVNL6b0fMbYoubxP1 /ZOm4QU24baJ537e2079m+8hf9SDfRU5zvy0kS7gOqwDyOEQqCdMjGgy8V5m9QgGSt k9Uv7Kd8NJ+h/4v3L5hJb8l45O7L7SNfvGXTnhela5u6wUcAFab2T7nOTAZ+YWrPTo 8P0UILhY0R6/GMfZ7uNO2/9lqrFfJeMXcKf9OyJ8aIOW05QbTH+lpN6YE1cY++wHIJ VloguQ+1N5K+w== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 01/20] arm64: dts: mediatek: mt8183: Change iospaces for thermal and svs Date: Tue, 21 Nov 2023 12:56:05 +0100 Message-ID: <20231121115624.56855-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:57:05 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174651004264412 X-GMAIL-MSGID: 1783174651004264412 The SVS iospace starts at 0x1100bc00 and not at 0x1100b000 as the latter is the thermal sensor iospace instead. Change the iospaces for both as following: - Thermal: 0x1100b000, length 0xc00 - SVS: 0x1100bc00, length 0x400 Please note that while this would be a breaking change for SVS (but not for thermal sensors), it doesn't matter because the svs driver never worked anyway because of the missing trips in tzts2, causing that thermal zone to never actually register, hence the SVS driver to fail probing anyway. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 26 ++++++++++++------------ 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5169779d01df..13c3104bc67b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1183,22 +1183,10 @@ spi0: spi@1100a000 { status = "disabled"; }; - svs: svs@1100b000 { - compatible = "mediatek,mt8183-svs"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_THERM>; - clock-names = "main"; - nvmem-cells = <&svs_calibration>, - <&thermal_calibration>; - nvmem-cell-names = "svs-calibration-data", - "t-calibration-data"; - }; - thermal: thermal@1100b000 { #thermal-sensor-cells = <1>; compatible = "mediatek,mt8183-thermal"; - reg = <0 0x1100b000 0 0x1000>; + reg = <0 0x1100b000 0 0xc00>; clocks = <&infracfg CLK_INFRA_THERM>, <&infracfg CLK_INFRA_AUXADC>; clock-names = "therm", "auxadc"; @@ -1210,6 +1198,18 @@ thermal: thermal@1100b000 { nvmem-cell-names = "calibration-data"; }; + svs: svs@1100bc00 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100bc00 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, + <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", + "t-calibration-data"; + }; + thermal_zones: thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <100>; From patchwork Tue Nov 21 11:56:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167699 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565886vqb; Tue, 21 Nov 2023 04:00:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IHlPzcxV1PrWVWiZMkoXeRxm5VHp/Eo+A0vmkO9W4DRvpRyYgdu38DCX+dZ6cbYYS9Z+OPo X-Received: by 2002:a05:6830:43:b0:6d6:4ebf:1557 with SMTP id d3-20020a056830004300b006d64ebf1557mr9316750otp.21.1700568038632; Tue, 21 Nov 2023 04:00:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700568038; cv=none; d=google.com; s=arc-20160816; b=WA8yePhBr2/wNDou7S8yXInyrI16cFafCSNRHMn81sx4G55FvhJwM6z+OsZg7NF4kA d/fKP3YkHnXGjKbYAbaRLTPSP1fzyo5bOL2zrYf6TWAyQ2Ls5VNfo0NhnmAef6c5UCY6 qASdnVMsnDd2mV7NojU3Cqu/mPUDqs+MRjhgcuN0YXT/e9unvg1RbN//iiW3RscPz+Yi 7MJjIGRtHW5c5hhokWE3wKw1A2mVbJdAVhQFVSbxRZYh1JmjGeblmyC/W+x9az+N15uq OSS7oYTWnsDl58PKciG2J82MFEK2oMOErTniFYOWCRrHAGZU8hT5Jm7dbfluQkvd1ESC 0ljQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XXs9aA28Fb/zI3HoK+Y5RpS9a5/sxHENqTOcKG51emk=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=P/gd5BbJJ4d5bZ1ImfSZTxLu+tN3UcqnM/Xvt/Fdc5hec5RcaTihSsz8jEXljB32wz zvud6H1OJY4TPSJ/jhIhleATe4q+Ilm0Ino0Kks6AV76i84gQmE1ap/6lHE4uwTXKqb4 4gPj7LBfwZtZ8KFoTJrYU29ovY3vT0SEPrCEI7ZTN8apsWUMq3nvRbJJHqOqwMkhLBjE Oac47WYl8Az472JJrHZpjaoND8Ubk4eKs6NREpDR8TpfS/pImHez2rGM/ZCzS7vVk9wR 2wlAweoPBOMTiEEZrc/FSjiMJ20cQ08mhbXdfiq5niSk6yK4mpDcNUn4dp/vQ9yJ7/aI b/gg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=e8LkjZcj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id a5-20020a05683012c500b006d2d989cf33si3580237otq.302.2023.11.21.04.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:00:37 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=e8LkjZcj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 674F88063825; Tue, 21 Nov 2023 03:57:08 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234459AbjKUL5D (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234695AbjKUL4l (ORCPT ); Tue, 21 Nov 2023 06:56:41 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25E1A192; Tue, 21 Nov 2023 03:56:35 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 138306607314; Tue, 21 Nov 2023 11:56:33 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567793; bh=N42OlgtNsTN3hPgxRyKN1KLxCwyU6QyhLsWFXT5/rjk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e8LkjZcji6amFEX4CYSjQGEnk08SxfXxz7XUCQIhIlA8hZqyoPKSFaVD4Cf6LFzcK rPrPK2DLPdaip59A9OvBCIrtfMZhSBTbmIuGvLvSzfmm7Qp3LZe9pfPYr9OicxR315 7hUbaYl55ub/uLrhoiprpXGr4SaNSWie7mUQF8N3lQaD5xPL9KLce/9YJbcEO9VgN4 rWYBKHZsk1J3U8nZnIDfmGeQL6kuzds8S5/LNUZ3sSq4jxk/AF8fESm1+QXtOGCHlX SELg1b/XRQ3iTqHiHWgWGPqzu1WmKflAVRifq8SZbgM3IKned/4ptZhIH4TzCs+6+V +RQFYv1a7Kx2A== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 02/20] soc: mediatek: mtk-svs: Subtract offset from regs_v2 to avoid conflict Date: Tue, 21 Nov 2023 12:56:06 +0100 Message-ID: <20231121115624.56855-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:57:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174830760373277 X-GMAIL-MSGID: 1783174830760373277 The svs_regs_v2 array of registers was offsetted by 0xc00 because the SVS node was supposed to have the same iostart as the thermal sensors. That's wrong for two reasons: 1. Two different devices cannot have the same iostart in devicetree, as those would technically be the same device otherwise; and 2. SVS and Thermal Sensor (be it LVTS or AUXADC thermal) are not the same IP, and those two do obviously have a different iospace. Even though there already are users of this register array, the only one that declares a devicetree node for SVS is MT8183 - but it never actually worked because the "tzts1" thermal zone missed thermal trips, hence this driver's probe always failed on that SoC. Knowing this - it is safe to say that keeping compatibility with older device trees is pointless, hence simply subtract the 0xc00 offset from the register offset array. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 108 ++++++++++++++++----------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 0f7cfbe5630b..416e9b313c0a 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -256,60 +256,60 @@ enum svs_reg_index { }; static const u32 svs_regs_v2[] = { - [DESCHAR] = 0xc00, - [TEMPCHAR] = 0xc04, - [DETCHAR] = 0xc08, - [AGECHAR] = 0xc0c, - [DCCONFIG] = 0xc10, - [AGECONFIG] = 0xc14, - [FREQPCT30] = 0xc18, - [FREQPCT74] = 0xc1c, - [LIMITVALS] = 0xc20, - [VBOOT] = 0xc24, - [DETWINDOW] = 0xc28, - [CONFIG] = 0xc2c, - [TSCALCS] = 0xc30, - [RUNCONFIG] = 0xc34, - [SVSEN] = 0xc38, - [INIT2VALS] = 0xc3c, - [DCVALUES] = 0xc40, - [AGEVALUES] = 0xc44, - [VOP30] = 0xc48, - [VOP74] = 0xc4c, - [TEMP] = 0xc50, - [INTSTS] = 0xc54, - [INTSTSRAW] = 0xc58, - [INTEN] = 0xc5c, - [CHKINT] = 0xc60, - [CHKSHIFT] = 0xc64, - [STATUS] = 0xc68, - [VDESIGN30] = 0xc6c, - [VDESIGN74] = 0xc70, - [DVT30] = 0xc74, - [DVT74] = 0xc78, - [AGECOUNT] = 0xc7c, - [SMSTATE0] = 0xc80, - [SMSTATE1] = 0xc84, - [CTL0] = 0xc88, - [DESDETSEC] = 0xce0, - [TEMPAGESEC] = 0xce4, - [CTRLSPARE0] = 0xcf0, - [CTRLSPARE1] = 0xcf4, - [CTRLSPARE2] = 0xcf8, - [CTRLSPARE3] = 0xcfc, - [CORESEL] = 0xf00, - [THERMINTST] = 0xf04, - [INTST] = 0xf08, - [THSTAGE0ST] = 0xf0c, - [THSTAGE1ST] = 0xf10, - [THSTAGE2ST] = 0xf14, - [THAHBST0] = 0xf18, - [THAHBST1] = 0xf1c, - [SPARE0] = 0xf20, - [SPARE1] = 0xf24, - [SPARE2] = 0xf28, - [SPARE3] = 0xf2c, - [THSLPEVEB] = 0xf30, + [DESCHAR] = 0x00, + [TEMPCHAR] = 0x04, + [DETCHAR] = 0x08, + [AGECHAR] = 0x0c, + [DCCONFIG] = 0x10, + [AGECONFIG] = 0x14, + [FREQPCT30] = 0x18, + [FREQPCT74] = 0x1c, + [LIMITVALS] = 0x20, + [VBOOT] = 0x24, + [DETWINDOW] = 0x28, + [CONFIG] = 0x2c, + [TSCALCS] = 0x30, + [RUNCONFIG] = 0x34, + [SVSEN] = 0x38, + [INIT2VALS] = 0x3c, + [DCVALUES] = 0x40, + [AGEVALUES] = 0x44, + [VOP30] = 0x48, + [VOP74] = 0x4c, + [TEMP] = 0x50, + [INTSTS] = 0x54, + [INTSTSRAW] = 0x58, + [INTEN] = 0x5c, + [CHKINT] = 0x60, + [CHKSHIFT] = 0x64, + [STATUS] = 0x68, + [VDESIGN30] = 0x6c, + [VDESIGN74] = 0x70, + [DVT30] = 0x74, + [DVT74] = 0x78, + [AGECOUNT] = 0x7c, + [SMSTATE0] = 0x80, + [SMSTATE1] = 0x84, + [CTL0] = 0x88, + [DESDETSEC] = 0xe0, + [TEMPAGESEC] = 0xe4, + [CTRLSPARE0] = 0xf0, + [CTRLSPARE1] = 0xf4, + [CTRLSPARE2] = 0xf8, + [CTRLSPARE3] = 0xfc, + [CORESEL] = 0x300, + [THERMINTST] = 0x304, + [INTST] = 0x308, + [THSTAGE0ST] = 0x30c, + [THSTAGE1ST] = 0x310, + [THSTAGE2ST] = 0x314, + [THAHBST0] = 0x318, + [THAHBST1] = 0x31c, + [SPARE0] = 0x320, + [SPARE1] = 0x324, + [SPARE2] = 0x328, + [SPARE3] = 0x32c, + [THSLPEVEB] = 0x330, }; /** From patchwork Tue Nov 21 11:56:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167688 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565280vqb; Tue, 21 Nov 2023 03:59:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVEK2Z7x7oswi0Wbtcs3w8xbRR6Erbaea09aJbT1prHnoONLvBrTiWd3glCd+Jm4jwYyXe X-Received: by 2002:a05:6a21:168b:b0:186:ff2d:f964 with SMTP id np11-20020a056a21168b00b00186ff2df964mr14095742pzb.36.1700567984933; Tue, 21 Nov 2023 03:59:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700567984; cv=none; d=google.com; s=arc-20160816; b=at5lbeZyUGpuwgklsEByUSfg+hfOkihZ+sR+UkRKgu1oYu7wDggXkxrVvNKSKs+InW biaIBoHcItDcMyFzjynvUPJlrj8i8xYkaIQEFm9vDbnOb6MrQzEKYirSXFjogH9tm0P+ BdZ87hwgpYRDdLNMUHRjTJAwntO1ZArCz1ypFyoqR9oF82LqwvZU8OJ0uGgV5im0pofY j23EBQq1V/uLrTUQbkRobvJojyDYJ8k6sZUXm6izjlhSzSJgwAyB19pU+dUIXnDKLbhK 3aOws9rH7VgilEyBTqCBqYnZKtdC2zgMQbUCtdy1qfFQ7Aohl6zK/cnu/zK7BDMiIbUn KswQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=W92mOS+7P+rMOkaT6iQmGddNhUN1MdLvuvbtrL+Q8VA=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=i5pGh7AHnL17XzZEXEn6bd0XrV2FL3ysdtjZYKuuynKxfpj9hSkt4Z7xcIFlkWU8ak y6Qu2jwMUyCaLnmq+Yn008/pUgnoABK5BBVyBL3tvCtfBNLPbVfC7Dc3ohX7Ed83E0rM PxrbCD37HjSzAy7mxIQMnjItpBejQQqwRuHT4DuaQrOCNYFn87j6EErYu6ay/oiIiROJ z6yyXm8ZofMzUlDSAIheW7bvGUV1NEA/1i8ZGJ7mxdoL3snpgkvPyCX0K/lb1f/mWK2c jsqRKKlBLz5SvJ28OSgKvb+6gwcuNmspx6U/pC1ZM5C4DMtGHnZNspMZ3I2q258Zsex/ VFtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=TP46gjUV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id ok17-20020a17090b1d5100b0028103a8ad9csi10972794pjb.68.2023.11.21.03.59.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:59:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=TP46gjUV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 2960D80DECF7; Tue, 21 Nov 2023 03:57:33 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234750AbjKUL5R (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234583AbjKUL4m (ORCPT ); Tue, 21 Nov 2023 06:56:42 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFAB81BC; Tue, 21 Nov 2023 03:56:36 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1C1906607319; Tue, 21 Nov 2023 11:56:34 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567794; bh=bxh5Gx+Fb0RV/Yt4vunB8wvLU6bWVnKSjAMj8DBawUs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TP46gjUVbC1uBOrqG2pYc8I7Ru6smpDQwg+hRec8zlseFzZrdN9NDdaJGnIBYZr+k /3vKVoJc0HyMsrh88aN0XQ/Q1UHrKalXQ/8CymKkqnTwrQB0it1jr6ipINg23wMynO A2kDOn1hAEhAomcP3BPaeJ6V6ixX/wkT9sHeRfQtbf2g1NP5acoj6MuYGQMHQYzDZK A5dR3RYBG4q8aj/tQx5u/aT5U7NfbY7ZaOEhAvtKB0taFPNtZG2Vaf6+07Hq4MEHND ORwsrTOcNkXtNPYWPQcy21XLV6pYwFPFLQyGClq1A5L77xV6doUCkxDR6EA1QWAgce badua8BQeJuew== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 03/20] soc: mediatek: mtk-svs: Convert sw_id and type to enumerations Date: Tue, 21 Nov 2023 12:56:07 +0100 Message-ID: <20231121115624.56855-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:57:33 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174775372174441 X-GMAIL-MSGID: 1783174775372174441 The sw_id and type specifiers currently are defined as BIT(x) for unknown reasons: nothing in this code makes any AND/OR check for those, and that would never happen anyway because both sw_id and type are exclusive, as in: - There will never be a bank that is for both CPU and GPU, or for CPU and CCI together; - A bank cannot be contemporarily of one-line and two-line type, as much as it cannot contemporarily have both HIGH and LOW roles Change those definitions to enumerations and also add some kerneldoc to better describe what they are for and what they indicate. While at it, also change the names adding _SWID or _TYPE to increase human readability. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 192 ++++++++++++++++++--------------- 1 file changed, 106 insertions(+), 86 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 416e9b313c0a..ddbb9ba3e47d 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -32,16 +32,6 @@ #include #include -/* svs bank 1-line software id */ -#define SVSB_CPU_LITTLE BIT(0) -#define SVSB_CPU_BIG BIT(1) -#define SVSB_CCI BIT(2) -#define SVSB_GPU BIT(3) - -/* svs bank 2-line type */ -#define SVSB_LOW BIT(8) -#define SVSB_HIGH BIT(9) - /* svs bank mode support */ #define SVSB_MODE_ALL_DISABLE 0 #define SVSB_MODE_INIT01 BIT(1) @@ -174,6 +164,36 @@ static DEFINE_SPINLOCK(svs_lock); #define svs_dentry_data(name) {__stringify(name), &svs_##name##_debug_fops} #endif +/** + * enum svsb_sw_id - SVS Bank Software ID + * @SVSB_SWID_CPU_LITTLE: CPU little cluster Bank + * @SVSB_SWID_CPU_BIG: CPU big cluster Bank + * @SVSB_SWID_CCI: Cache Coherent Interconnect Bank + * @SVSB_SWID_GPU: GPU Bank + * @SVSB_SWID_MAX: Total number of Banks + */ +enum svsb_sw_id { + SVSB_SWID_CPU_LITTLE, + SVSB_SWID_CPU_BIG, + SVSB_SWID_CCI, + SVSB_SWID_GPU, + SVSB_SWID_MAX +}; + +/** + * enum svsb_type - SVS Bank 2-line: Type and Role + * @SVSB_TYPE_NONE: One-line type Bank - Global role + * @SVSB_TYPE_LOW: Two-line type Bank - Low bank role + * @SVSB_TYPE_HIGH: Two-line type Bank - High bank role + * @SVSB_TYPE_MAX: Total number of bank types + */ +enum svsb_type { + SVSB_TYPE_NONE, + SVSB_TYPE_LOW, + SVSB_TYPE_HIGH, + SVSB_TYPE_MAX +}; + /** * enum svsb_phase - svs bank phase enumeration * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition @@ -549,10 +569,10 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) * 2-line bank updates its corresponding opp volts. * 1-line bank updates all opp volts. */ - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { opp_start = 0; opp_stop = svsb->turn_pt; - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { opp_start = svsb->turn_pt; opp_stop = svsb->opp_count; } else { @@ -576,8 +596,8 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) temp_voffset += svsb->tzone_ltemp_voffset; /* 2-line bank update all opp volts when running mon mode */ - if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_HIGH || - svsb->type == SVSB_LOW)) { + if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_TYPE_HIGH || + svsb->type == SVSB_TYPE_LOW)) { opp_start = 0; opp_stop = svsb->opp_count; } @@ -881,7 +901,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) /* Target is to set svsb->volt[] by algorithm */ if (turn_pt < middle_index) { - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { /* volt[0] ~ volt[turn_pt - 1] */ for (i = 0; i < turn_pt; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); @@ -890,7 +910,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); shift_byte++; } - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ j = svsb->opp_count - 7; svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); @@ -912,7 +932,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) svsb->freq_pct[i]); } } else { - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ j = turn_pt - 7; svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); @@ -932,7 +952,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) svsb->volt[0], svsb->volt[j], svsb->freq_pct[i]); - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { /* volt[turn_pt] ~ volt[opp_count - 1] */ for (i = turn_pt; i < svsb->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); @@ -944,10 +964,10 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) } } - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { opp_start = 0; opp_stop = svsb->turn_pt; - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { opp_start = svsb->turn_pt; opp_stop = svsb->opp_count; } @@ -998,11 +1018,11 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) /* Target is to fill out freq_pct74 / freq_pct30 by algorithm */ if (turn_pt < middle_index) { - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { /* * If we don't handle this situation, - * SVSB_HIGH's FREQPCT74 / FREQPCT30 would keep "0" - * and this leads SVSB_LOW to work abnormally. + * SVSB_TYPE_HIGH's FREQPCT74 / FREQPCT30 would keep "0" + * and this leads SVSB_TYPE_LOW to work abnormally. */ if (turn_pt == 0) freq_pct30 = svsb->freq_pct[0]; @@ -1015,7 +1035,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) *freq_pct |= (svsb->freq_pct[i] << b_sft); shift_byte++; } - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { /* * freq_pct[turn_pt] + * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] @@ -1032,7 +1052,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) } } } else { - if (svsb->type == SVSB_HIGH) { + if (svsb->type == SVSB_TYPE_HIGH) { /* * freq_pct[0] + * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] @@ -1047,7 +1067,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) *freq_pct |= (svsb->freq_pct[i] << b_sft); shift_byte++; } - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ for (i = turn_pt; i < svsb->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); @@ -1550,7 +1570,7 @@ static int svs_init02(struct svs_platform *svsp) if (!(svsb->mode_support & SVSB_MODE_INIT02)) continue; - if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { + if (svsb->type == SVSB_TYPE_HIGH || svsb->type == SVSB_TYPE_LOW) { if (svs_sync_bank_volts_from_opp(svsb)) { dev_err(svsb->dev, "sync volt fail\n"); ret = -EPERM; @@ -1677,19 +1697,19 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) svsb = &svsp->banks[idx]; switch (svsb->sw_id) { - case SVSB_CPU_LITTLE: + case SVSB_SWID_CPU_LITTLE: svsb->name = "SVSB_CPU_LITTLE"; break; - case SVSB_CPU_BIG: + case SVSB_SWID_CPU_BIG: svsb->name = "SVSB_CPU_BIG"; break; - case SVSB_CCI: + case SVSB_SWID_CCI: svsb->name = "SVSB_CCI"; break; - case SVSB_GPU: - if (svsb->type == SVSB_HIGH) + case SVSB_SWID_GPU: + if (svsb->type == SVSB_TYPE_HIGH) svsb->name = "SVSB_GPU_HIGH"; - else if (svsb->type == SVSB_LOW) + else if (svsb->type == SVSB_TYPE_LOW) svsb->name = "SVSB_GPU_LOW"; else svsb->name = "SVSB_GPU"; @@ -1821,13 +1841,13 @@ static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) if (ft_pgm == 0) svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; - if (svsb->type == SVSB_LOW) { + if (svsb->type == SVSB_TYPE_LOW) { svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); - } else if (svsb->type == SVSB_HIGH) { + } else if (svsb->type == SVSB_TYPE_HIGH) { svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); @@ -1886,13 +1906,13 @@ static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) if (vmin == 0x1) svsb->vmin = 0x1e; - if (svsb->type == SVSB_LOW) { + if (svsb->type == SVSB_TYPE_LOW) { svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0); - } else if (svsb->type == SVSB_HIGH) { + } else if (svsb->type == SVSB_TYPE_HIGH) { svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); @@ -1946,13 +1966,13 @@ static bool svs_mt8188_efuse_parsing(struct svs_platform *svsp) for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; - if (svsb->type == SVSB_LOW) { + if (svsb->type == SVSB_TYPE_LOW) { svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); - } else if (svsb->type == SVSB_HIGH) { + } else if (svsb->type == SVSB_TYPE_HIGH) { svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); @@ -2007,14 +2027,14 @@ static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) svsb = &svsp->banks[idx]; switch (svsb->sw_id) { - case SVSB_CPU_BIG: - if (svsb->type == SVSB_HIGH) { + case SVSB_SWID_CPU_BIG: + if (svsb->type == SVSB_TYPE_HIGH) { svsb->mdes = (svsp->efuse[2] >> 24) & GENMASK(7, 0); svsb->bdes = (svsp->efuse[2] >> 16) & GENMASK(7, 0); svsb->mtdes = svsp->efuse[2] & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[13] >> 8) & GENMASK(7, 0); svsb->dcbdet = svsp->efuse[13] & GENMASK(7, 0); - } else if (svsb->type == SVSB_LOW) { + } else if (svsb->type == SVSB_TYPE_LOW) { svsb->mdes = (svsp->efuse[3] >> 24) & GENMASK(7, 0); svsb->bdes = (svsp->efuse[3] >> 16) & GENMASK(7, 0); svsb->mtdes = svsp->efuse[3] & GENMASK(7, 0); @@ -2022,21 +2042,21 @@ static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) svsb->dcbdet = (svsp->efuse[14] >> 16) & GENMASK(7, 0); } break; - case SVSB_CPU_LITTLE: + case SVSB_SWID_CPU_LITTLE: svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0); svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0); break; - case SVSB_CCI: + case SVSB_SWID_CCI: svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); break; - case SVSB_GPU: + case SVSB_SWID_GPU: svsb->mdes = (svsp->efuse[6] >> 24) & GENMASK(7, 0); svsb->bdes = (svsp->efuse[6] >> 16) & GENMASK(7, 0); svsb->mtdes = svsp->efuse[6] & GENMASK(7, 0); @@ -2098,7 +2118,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; switch (svsb->sw_id) { - case SVSB_CPU_LITTLE: + case SVSB_SWID_CPU_LITTLE: svsb->bdes = svsp->efuse[16] & GENMASK(7, 0); svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0); @@ -2110,7 +2130,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) else svsb->volt_od += 2; break; - case SVSB_CPU_BIG: + case SVSB_SWID_CPU_BIG: svsb->bdes = svsp->efuse[18] & GENMASK(7, 0); svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0); @@ -2122,7 +2142,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) else svsb->volt_od += 12; break; - case SVSB_CCI: + case SVSB_SWID_CCI: svsb->bdes = svsp->efuse[4] & GENMASK(7, 0); svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0); @@ -2134,7 +2154,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) else svsb->volt_od += 2; break; - case SVSB_GPU: + case SVSB_SWID_GPU: svsb->bdes = svsp->efuse[6] & GENMASK(7, 0); svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0); svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0); @@ -2219,16 +2239,16 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) svsb->mts = mts; switch (svsb->sw_id) { - case SVSB_CPU_LITTLE: + case SVSB_SWID_CPU_LITTLE: tb_roomt = x_roomt[3]; break; - case SVSB_CPU_BIG: + case SVSB_SWID_CPU_BIG: tb_roomt = x_roomt[4]; break; - case SVSB_CCI: + case SVSB_SWID_CCI: tb_roomt = x_roomt[3]; break; - case SVSB_GPU: + case SVSB_SWID_GPU: tb_roomt = x_roomt[1]; break; default: @@ -2321,9 +2341,9 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; - if (svsb->type == SVSB_HIGH) + if (svsb->type == SVSB_TYPE_HIGH) svsb->opp_dev = svs_add_device_link(svsp, "gpu"); - else if (svsb->type == SVSB_LOW) + else if (svsb->type == SVSB_TYPE_LOW) svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); if (IS_ERR(svsb->opp_dev)) @@ -2355,14 +2375,14 @@ static int svs_mt8186_platform_probe(struct svs_platform *svsp) svsb = &svsp->banks[idx]; switch (svsb->sw_id) { - case SVSB_CPU_LITTLE: - case SVSB_CPU_BIG: + case SVSB_SWID_CPU_LITTLE: + case SVSB_SWID_CPU_BIG: svsb->opp_dev = get_cpu_device(svsb->cpu_id); break; - case SVSB_CCI: + case SVSB_SWID_CCI: svsb->opp_dev = svs_add_device_link(svsp, "cci"); break; - case SVSB_GPU: + case SVSB_SWID_GPU: svsb->opp_dev = svs_add_device_link(svsp, "gpu"); break; default: @@ -2394,14 +2414,14 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) svsb = &svsp->banks[idx]; switch (svsb->sw_id) { - case SVSB_CPU_LITTLE: - case SVSB_CPU_BIG: + case SVSB_SWID_CPU_LITTLE: + case SVSB_SWID_CPU_BIG: svsb->opp_dev = get_cpu_device(svsb->cpu_id); break; - case SVSB_CCI: + case SVSB_SWID_CCI: svsb->opp_dev = svs_add_device_link(svsp, "cci"); break; - case SVSB_GPU: + case SVSB_SWID_GPU: svsb->opp_dev = svs_add_device_link(svsp, "gpu"); break; default: @@ -2420,8 +2440,8 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) static struct svs_bank svs_mt8195_banks[] = { { - .sw_id = SVSB_GPU, - .type = SVSB_LOW, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, @@ -2443,8 +2463,8 @@ static struct svs_bank svs_mt8195_banks[] = { .ctl0 = 0x00540003, }, { - .sw_id = SVSB_GPU, - .type = SVSB_HIGH, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .tzone_name = "gpu1", @@ -2475,8 +2495,8 @@ static struct svs_bank svs_mt8195_banks[] = { static struct svs_bank svs_mt8192_banks[] = { { - .sw_id = SVSB_GPU, - .type = SVSB_LOW, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .tzone_name = "gpu1", @@ -2503,8 +2523,8 @@ static struct svs_bank svs_mt8192_banks[] = { .tzone_ltemp_voffset = 7, }, { - .sw_id = SVSB_GPU, - .type = SVSB_HIGH, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .tzone_name = "gpu1", @@ -2535,8 +2555,8 @@ static struct svs_bank svs_mt8192_banks[] = { static struct svs_bank svs_mt8188_banks[] = { { - .sw_id = SVSB_GPU, - .type = SVSB_LOW, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, @@ -2558,8 +2578,8 @@ static struct svs_bank svs_mt8188_banks[] = { .ctl0 = 0x00100003, }, { - .sw_id = SVSB_GPU, - .type = SVSB_HIGH, + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .tzone_name = "gpu1", @@ -2590,8 +2610,8 @@ static struct svs_bank svs_mt8188_banks[] = { static struct svs_bank svs_mt8186_banks[] = { { - .sw_id = SVSB_CPU_BIG, - .type = SVSB_LOW, + .sw_id = SVSB_SWID_CPU_BIG, + .type = SVSB_TYPE_LOW, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .cpu_id = 6, @@ -2615,8 +2635,8 @@ static struct svs_bank svs_mt8186_banks[] = { .ctl0 = 0x00540003, }, { - .sw_id = SVSB_CPU_BIG, - .type = SVSB_HIGH, + .sw_id = SVSB_SWID_CPU_BIG, + .type = SVSB_TYPE_HIGH, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, .cpu_id = 6, @@ -2646,7 +2666,7 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_ltemp_voffset = 8, }, { - .sw_id = SVSB_CPU_LITTLE, + .sw_id = SVSB_SWID_CPU_LITTLE, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .cpu_id = 0, @@ -2675,7 +2695,7 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_ltemp_voffset = 8, }, { - .sw_id = SVSB_CCI, + .sw_id = SVSB_SWID_CCI, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .tzone_name = "cpu_zone0", @@ -2703,7 +2723,7 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_ltemp_voffset = 8, }, { - .sw_id = SVSB_GPU, + .sw_id = SVSB_SWID_GPU, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .tzone_name = "mfg", @@ -2733,7 +2753,7 @@ static struct svs_bank svs_mt8186_banks[] = { static struct svs_bank svs_mt8183_banks[] = { { - .sw_id = SVSB_CPU_LITTLE, + .sw_id = SVSB_SWID_CPU_LITTLE, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .cpu_id = 0, @@ -2757,7 +2777,7 @@ static struct svs_bank svs_mt8183_banks[] = { .ctl0 = 0x00010001, }, { - .sw_id = SVSB_CPU_BIG, + .sw_id = SVSB_SWID_CPU_BIG, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .cpu_id = 4, @@ -2781,7 +2801,7 @@ static struct svs_bank svs_mt8183_banks[] = { .ctl0 = 0x00000001, }, { - .sw_id = SVSB_CCI, + .sw_id = SVSB_SWID_CCI, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .buck_name = "proc", @@ -2804,7 +2824,7 @@ static struct svs_bank svs_mt8183_banks[] = { .ctl0 = 0x00100003, }, { - .sw_id = SVSB_GPU, + .sw_id = SVSB_SWID_GPU, .set_freq_pct = svs_set_bank_freq_pct_v2, .get_volts = svs_get_bank_volts_v2, .buck_name = "mali", From patchwork Tue Nov 21 11:56:08 2023 Content-Type: text/plain; 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[2620:137:e000::3:8]) by mx.google.com with ESMTPS id g6-20020a63f406000000b005c1cd5977f7si10103397pgi.75.2023.11.21.03.58.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:58:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=adLi8EjK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 355258029A82; Tue, 21 Nov 2023 03:57:52 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234355AbjKUL5G (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234690AbjKUL4l (ORCPT ); Tue, 21 Nov 2023 06:56:41 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37A451AA; Tue, 21 Nov 2023 03:56:37 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 25571660731B; Tue, 21 Nov 2023 11:56:35 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567796; bh=lCOeXkBHj3GxnYKp57VPx13B7VONqu2PAmr9JmQp0B4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=adLi8EjKU/pSSuIY0oiyYNLp8EDYc9ZOZmpiLT2preSIyZXYbdqe/f3QcenB0qnxR x904L8s4XMPEPapwPWm9sBV42g2Xg7wy0d9r3TQxMl1V4VFk4iO3qsZy9EkJmBqhy/ EHdq+yy6N/ue4/g2rP0cLUrBDOKTFqAmDy94ejVs8kADInhQnleoekW7tcN4CBZWor A/ZiPikB5ughWo0rJ9olbxh4Ty4sRX7y1623z9QEABaRUJPBZt6VdFAFAv1uQTVR/D Lw6vD8rH1wOIqbDdP+YLdzsEQhurzWPalpkRsMiJ7/lW7y/jzOsw9kXk9xEykBYqBA V0Z1dotceCbAw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 04/20] soc: mediatek: mtk-svs: Build bank name string dynamically Date: Tue, 21 Nov 2023 12:56:08 +0100 Message-ID: <20231121115624.56855-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:57:52 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174666393744469 X-GMAIL-MSGID: 1783174666393744469 In svs_bank_resource_setup() there is a "big" switch assigning different names depending on sw_id and type and this will surely grow: for example MT8186 has got a two-line type (high/low) SVS bank for CPU_BIG, and this would require more switch nesting. Simplify all of this by changing that to a devm_kasprintf() call that will concatenate the SW_ID string (e.g. SVSB_CPU_LITTLE) with the Type string (e.g. _LOW), resulting in the expected full bank name (e.g. SVSB_CPU_LITTLE_LOW). This being a dynamic allocation can be slower, but this happens only once in the life of this driver and it's not a performance path, so it's totally acceptable. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 39 +++++++++++++++------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index ddbb9ba3e47d..1c7592fd6ae7 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -332,6 +332,14 @@ static const u32 svs_regs_v2[] = { [THSLPEVEB] = 0x330, }; +static const char * const svs_swid_names[SVSB_SWID_MAX] = { + "SVSB_CPU_LITTLE", "SVSB_CPU_BIG", "SVSB_CCI", "SVSB_GPU" +}; + +static const char * const svs_type_names[SVSB_TYPE_MAX] = { + "", "_LOW", "_HIGH" +}; + /** * struct svs_platform - svs platform control * @base: svs platform register base @@ -1696,34 +1704,21 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; - switch (svsb->sw_id) { - case SVSB_SWID_CPU_LITTLE: - svsb->name = "SVSB_CPU_LITTLE"; - break; - case SVSB_SWID_CPU_BIG: - svsb->name = "SVSB_CPU_BIG"; - break; - case SVSB_SWID_CCI: - svsb->name = "SVSB_CCI"; - break; - case SVSB_SWID_GPU: - if (svsb->type == SVSB_TYPE_HIGH) - svsb->name = "SVSB_GPU_HIGH"; - else if (svsb->type == SVSB_TYPE_LOW) - svsb->name = "SVSB_GPU_LOW"; - else - svsb->name = "SVSB_GPU"; - break; - default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + if (svsb->sw_id >= SVSB_SWID_MAX || svsb->type >= SVSB_TYPE_MAX) { + dev_err(svsb->dev, "unknown bank sw_id or type\n"); return -EINVAL; } - svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), - GFP_KERNEL); + svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), GFP_KERNEL); if (!svsb->dev) return -ENOMEM; + svsb->name = devm_kasprintf(svsp->dev, GFP_KERNEL, "%s%s", + svs_swid_names[svsb->sw_id], + svs_type_names[svsb->type]); + if (!svsb->name) + return -ENOMEM; + ret = dev_set_name(svsb->dev, "%s", svsb->name); if (ret) return ret; From patchwork Tue Nov 21 11:56:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167687 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565264vqb; Tue, 21 Nov 2023 03:59:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IGIs0d9E8nSk2q0Ghym17oor2zBx0A9+GKrU93Pqx0p98bbIAykXxyylteJ7IaZUgl4Ekj1 X-Received: by 2002:a17:90a:1188:b0:27f:df1a:caab with SMTP id e8-20020a17090a118800b0027fdf1acaabmr11801011pja.21.1700567982853; Tue, 21 Nov 2023 03:59:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700567982; cv=none; d=google.com; s=arc-20160816; b=sduktL9wtXTtdpUgmJkiylGvJZOFsNkz84J58NBc59/lhS3OuGipBlS7UHqBh1pj3P 0dc0bCtrzbBoX1aAC8upFBev8+AdVdJ35TCugs/269xHmuZ2dRKJ1Nsiz1HRZzxluDpl ajl9NfmmeI5CwdoSaK8fQAWBgPeTfgSQ01tpuY8PQ6KHkADMerHL5kTbg7Js/NXw9jMI eVY4oyLsA1ZoExwENW/tCjL3GKgDAB7X2bZx3lgZ7rSeyfp8WRt1kc7TpSowvxSJLPOB p13oR6v2pdAzf3xocuDLyegpPd03+WeHAN26C+2P8jShX3P44O7Iab7o9IMSrBxVjcm8 lqhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sq9G32K6TtoLD+AvzTy4qXTHDqDo8A0lDQFf/DMBYSM=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=TlXTuf1vAf/n0IXKExIfnv5WgpwGMJcTY9pndXKVALSeF2QPSaoxWTG4nrcQld4Qvo eMEEYg0Wb6ve1x5TyNHgRITUqZKJuNKvo35tSPwAleh6pliAcl8jinvCilCkj6nRRC0L 3ooiuMT4VMC4Lud/n3/38C/eZzfA1dckLFTaz4MjOEFfohDGlTmBzUvSelaKV31ZCxua OrIRsbVranzsNrOnecklYfdxW+B4z/6S4Yy+Q1VlpvButXl6cWXvL7jlmSsuGtdE917b yC8HWLqFq+KBUcwQJtxmK26mXnkCb/qxX0JfFX/akge0aGzz9AaIWI6hUHzqyXAgJtrB EobA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=EXLibqZS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id z15-20020a17090a1fcf00b0026b31ed4895si11919873pjz.29.2023.11.21.03.59.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:59:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=EXLibqZS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 09D0580DEA7C; Tue, 21 Nov 2023 03:57:20 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234731AbjKUL5J (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234196AbjKUL4m (ORCPT ); Tue, 21 Nov 2023 06:56:42 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3AA8ED61; Tue, 21 Nov 2023 03:56:39 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2D3786607326; Tue, 21 Nov 2023 11:56:36 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567797; bh=HjqA+sAHeyELuvvhdsMlpINGaociXjYFjdm6q68a7V8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EXLibqZSgqMFvSVmoKDxfiKEQt35SplGXYfEg0Lcj17c8DSbVnMxGi6iEm0voHTvZ imrVUalRfN3zbP8nWm7kIs3ThcWyUfo3BfPOxmJXPfHlbycx83nbyqSQjLe/zleNtF RMylCGCl5GUUqZbV0vHkBUjZml8Ju6LjfT9WKBJML4qcW+Ri42HmoowQabxNEE+cpw rOn2wHx21vMBYPSCq7p1JBEHF5wl24uxPgKofemsTZ/RMuaml4SgMi8L8wHuwdmnSi zW4mdpWRfTJ+a8eKU6nyt83qLmTExAbnqrko6tpp6VnrZGyWwBrgkxepK1G3PwtS8Q E/N/3R5fqCZRg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 05/20] soc: mediatek: mtk-svs: Reduce memory footprint of struct svs_bank Date: Tue, 21 Nov 2023 12:56:09 +0100 Message-ID: <20231121115624.56855-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:57:21 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174773413008709 X-GMAIL-MSGID: 1783174773413008709 Many 32-bit members of this struct can be size reduced to either 16-bit or even 8-bit, for a total saving of ~61 bytes per bank. Keeping in mind that one SoC declares at least two banks, this brings a minimum of ~122 bytes saving (depending on compiler optimization). Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 51 +++++++++++++++++----------------- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 1c7592fd6ae7..6c27fb523bfa 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -456,13 +456,13 @@ struct svs_bank { char *buck_name; char *tzone_name; enum svsb_phase phase; - s32 volt_od; + short int volt_od; u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX]; u32 pm_runtime_enabled_count; - u32 mode_support; + u8 mode_support; u32 freq_base; u32 turn_freq_base; - u32 vboot; + u8 vboot; u32 opp_dfreq[MAX_OPP_ENTRIES]; u32 opp_dvolt[MAX_OPP_ENTRIES]; u32 freq_pct[MAX_OPP_ENTRIES]; @@ -470,36 +470,36 @@ struct svs_bank { u32 volt_step; u32 volt_base; u32 volt_flags; - u32 vmax; - u32 vmin; + u8 vmax; + u8 vmin; u32 age_config; - u32 age_voffset_in; + u16 age_voffset_in; u32 dc_config; - u32 dc_voffset_in; - u32 dvt_fixed; - u32 vco; - u32 chk_shift; + u16 dc_voffset_in; + u8 dvt_fixed; + u8 vco; + u8 chk_shift; u32 core_sel; - u32 opp_count; + u8 opp_count; u32 int_st; - u32 sw_id; - u32 cpu_id; + u8 sw_id; + u8 cpu_id; u32 ctl0; u32 temp; u32 tzone_htemp; - u32 tzone_htemp_voffset; + u16 tzone_htemp_voffset; u32 tzone_ltemp; - u32 tzone_ltemp_voffset; - u32 bts; - u32 mts; - u32 bdes; - u32 mdes; - u32 mtdes; - u32 dcbdet; - u32 dcmdet; + u16 tzone_ltemp_voffset; + u16 bts; + u16 mts; + u16 bdes; + u16 mdes; + u8 mtdes; + u8 dcbdet; + u8 dcmdet; u32 turn_pt; u32 vbin_turn_pt; - u32 type; + u8 type; }; static u32 percent(u32 numerator, u32 denominator) @@ -1267,6 +1267,7 @@ static inline void svs_error_isr_handler(struct svs_platform *svsp) static inline void svs_init01_isr_handler(struct svs_platform *svsp) { struct svs_bank *svsb = svsp->pbank; + u32 val; dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", __func__, svs_readl_relaxed(svsp, VDESIGN74), @@ -1276,8 +1277,8 @@ static inline void svs_init01_isr_handler(struct svs_platform *svsp) svs_save_bank_register_data(svsp, SVSB_PHASE_INIT01); svsb->phase = SVSB_PHASE_INIT01; - svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) & - GENMASK(15, 0)) + 1; + val = ~(svs_readl_relaxed(svsp, DCVALUES) & GENMASK(15, 0)) + 1; + svsb->dc_voffset_in = val & GENMASK(15, 0); if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE || (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT && svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY)) From patchwork Tue Nov 21 11:56:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167689 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565296vqb; Tue, 21 Nov 2023 03:59:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IHlTqdoC4r9TI63NKxY/mcpNYXCFBN9rsH62vv+R8Ie33urVf4RO4LInnsK5wIS/44no3DQ X-Received: by 2002:a17:90a:6881:b0:280:a4a1:5d03 with SMTP id a1-20020a17090a688100b00280a4a15d03mr3763948pjd.4.1700567987630; Tue, 21 Nov 2023 03:59:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700567987; cv=none; d=google.com; s=arc-20160816; b=mkGFpUkvFAB4xvPbxyWbXUYOm99YkRuWo0dqL8cyQ/fA/fANluW8mdbWC9MaaU9SwR pwwmz4WCTYs8HjLPM4xB4CcZraB6spf0WjEHaIhCTD0RQTk0OH+WP+eP4T/JCoahh/By 6uOGxOKHQkf1s5XdFmrWKmex59E4ul4ioWCZ8ej7DFPfef7PNlORgobHkoQAu8AEe7w+ v5lYBXdPzIYC7Jga7FdEf5epqIg3sHWa4SrVx4AotkVFaX5355BX6ILStsgFLcZbsoKH eJPqcTGxURWwqNqBXI1WJYXF/wkCv3ds0pZEHiINqWnVPmtth/9YvqGfZUZw6Jj7y6bw Cc+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=G4CiWflMa0UUyp9NbGyD/T0A000MhIAnhks0L2DnG2Q=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=vXb3S5p1+hlTyeIAdaeDt6gUq5jC3HQWyXfnxysCNBS/V7MjFqHs14L+VYXpm/TCIc wh1D5A7hO7TbdHHzLDF9BKoVkJLk7TyXRuOhWYGqvt+SVzWs+RRTj2pTM0btJwJ/EsXB Th5kkl6RO5GnqCm+KkjjzDvUdi8pp1y9AEWMEHRg68HzHqmXntSvP+JKmhAIXHVPuf0O +mfa2M4QAGySXclhybUAtoxVB577y32AVLMpkxMrhc6DFoleQEgexr1/tf5UKHeAxgam wPDkJ38cvNs9e2JVsNX7AvNObzyj3PaBUkn9S/DZMeM0U0UF/z4suNBVn2BNnz+qCj6L aNeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=BOJXhvq4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id h23-20020a17090adb9700b00283bc49ad11si7555638pjv.183.2023.11.21.03.59.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:59:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=BOJXhvq4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D88D280FC73A; Tue, 21 Nov 2023 03:57:37 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234737AbjKUL5O (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234596AbjKUL4m (ORCPT ); Tue, 21 Nov 2023 06:56:42 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A3F7131; Tue, 21 Nov 2023 03:56:39 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 347AE660732E; Tue, 21 Nov 2023 11:56:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567798; bh=rbMxFG/9Z/MvXIMSXdH+Z5ELUWvpXJ2G/c2LivRCtOk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BOJXhvq4C9UV/vImSye1MfJJrb0nTSDZS32sdnmUOS93jx/wHGT85watYQwvucA8K e7pEls/wtVZp5e6i0GG+ffeJ4wTz62QLYPS+VIdRm3oujpBz0n7XdE/AEWo2ahi8d9 JM4dWTqvf11DWirTYh1dFvwYHpi8cKoOiRDISlnEQ+KqdSWwT5oS4eXgHA+psjm1KT kXjhniyB+uMidk2Dz/fIlcBB7x0FqpXAGD0r1HtAETKf0xlIvHbeNCa29nviOAZWiU RP5rfwyc2B1YtyoSb/etDScxpw+M/UjreXP83L12Rjvxl+kVySOv9sPx/Bff82dA0U a0YZSVjc/2suw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 06/20] soc: mediatek: mtk-svs: Change the thermal sensor device name Date: Tue, 21 Nov 2023 12:56:10 +0100 Message-ID: <20231121115624.56855-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:57:38 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174778058024828 X-GMAIL-MSGID: 1783174778058024828 This driver tries to create a device link to the thermal sensor device: change all instances of "lvts" and "thermal" to "thermal-sensor", as that's what the devicetree node name must be. Note for MT8183: As specified in a previous commit, this SoC never got SVS probing, so this is not a breaking change and it does not require fallback for older device trees. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 6c27fb523bfa..b5beb33c95ba 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2329,7 +2329,7 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), "cannot get svs reset control\n"); - dev = svs_add_device_link(svsp, "lvts"); + dev = svs_add_device_link(svsp, "thermal-sensor"); if (IS_ERR(dev)) return dev_err_probe(svsp->dev, PTR_ERR(dev), "failed to get lvts device\n"); @@ -2362,7 +2362,7 @@ static int svs_mt8186_platform_probe(struct svs_platform *svsp) return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), "cannot get svs reset control\n"); - dev = svs_add_device_link(svsp, "lvts"); + dev = svs_add_device_link(svsp, "thermal-sensor"); if (IS_ERR(dev)) return dev_err_probe(svsp->dev, PTR_ERR(dev), "failed to get lvts device\n"); @@ -2401,7 +2401,7 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) struct svs_bank *svsb; u32 idx; - dev = svs_add_device_link(svsp, "thermal"); + dev = svs_add_device_link(svsp, "thermal-sensor"); if (IS_ERR(dev)) return dev_err_probe(svsp->dev, PTR_ERR(dev), "failed to get thermal device\n"); From patchwork Tue Nov 21 11:56:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167684 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp564701vqb; Tue, 21 Nov 2023 03:58:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IE5BjxKtMh8lp9YKOiOIoVCUPmoZHcebGGZI1cFX4z/vJZ9bJsC7kfgJWQGk5Tv39z1GbEV X-Received: by 2002:a17:90a:191a:b0:280:1695:7b5 with SMTP id 26-20020a17090a191a00b00280169507b5mr8184624pjg.12.1700567901870; Tue, 21 Nov 2023 03:58:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700567901; cv=none; d=google.com; s=arc-20160816; b=y6UPDVHdbjGG+d1ArL0Tj0QhVP08ETF3kYGoQeGNjFcUF+zXpHEg2Mn4bOVB3GZukP kc6ipkab5h2hk21XZpDL/zaB3hj0wCHsmLqpBQ7na/hX4/ito2pEEY5AOnq3mbqybaK6 ZALD8tkjxk73NT6a0AMZIEiUfBusx2QbFy7BUOTR9cSzR4MIni2CoKgr2zudZ4eSPdH9 9UzMXTBG1fIHhNZahgpVltmg8xaE0Lm8hCceU/7f2o8qEaQJ/U1QkXwIW1I6nztcO4sr Rx8i02n5JA7BdkMWnPS/q+rPLtU2W9wON1T+o7D9+H6lyVT67irTB+iJPaTBLh9MVx+/ S8tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dloUf1foTLvmfIU52Wp1Zyxe4yiIJTvKjylKM09rNkQ=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=xX7IBaAEVjJN9aCIHvIcl3S3XiCXqTQNncjNJlbKdOYcuia+ZYdtOzQPvcvhckt5XU 8/2WXEHgewrqGKGSGnrley+jCus/UcsFg2AcJr2fIY83FcuU9kJJa8JTD3D+/jAB+9Pn BuejRSgyGErt7RWy7b+f9VcVdyHrVIJhfpQSxgA/mVaNl2t5HbpUSfqaEG3E0urzHtRs obQE1GLgFz17rXksw+EhxzR7ABD++iZ8psm79gv20CkukAAqt8dtmavGF4V8SLOqlLam YL+yk9jRXWEJ8Zwn4P+h9Q8VrBj0PhBP1m2k7B3DrL40pwOx3PsYvfj++YSifVi+l3/Z FPNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=a4lEWDUB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from agentk.vger.email (agentk.vger.email. [23.128.96.32]) by mx.google.com with ESMTPS id p21-20020a17090a931500b0027769032e57si12298409pjo.52.2023.11.21.03.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:58:21 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=a4lEWDUB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 9FE1D80C47B6; Tue, 21 Nov 2023 03:58:11 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234584AbjKUL5U (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234659AbjKUL4o (ORCPT ); Tue, 21 Nov 2023 06:56:44 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 329F6D5F; Tue, 21 Nov 2023 03:56:40 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 393646607286; Tue, 21 Nov 2023 11:56:38 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567799; bh=y4hC7rjcvzTRTeQC8pyo7KQ1ZhxtsknG+ldiwzI/d40=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a4lEWDUBYAYOdtl+gW2+VN8SHrWi3YN7fv79PVM5uX19xytbyS1mmkLyq/qd3sY4s wxAYfOp1mlNj5U/293LYIlWMO0RIQEC2mvzFrIHM0PJPFF7SfS0JXjPet3bgY6n8uC +Dr9sV7J2WxoMPb5BTK+xtk1lZU1CLn5oIkM74b3YDlDLzHXD2ypqrJjQExfSeFdaY /r3Jmh1MtaayI+cKLtFN60D2AKPKjIHAg5WLJgf5z6TlzWBEEM1FpvLUpF4G68f+di bDyJAPGnduKJqNfPi3+Znkxpt0wWbPodDhqVKrG2AZBjlA8PVDjCe5MWI+x+vsXBO3 jkMhyJ7quSbsw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 07/20] soc: mediatek: mtk-svs: Add a map to retrieve fused values Date: Tue, 21 Nov 2023 12:56:11 +0100 Message-ID: <20231121115624.56855-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:58:11 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174688152065835 X-GMAIL-MSGID: 1783174688152065835 In preparation for adding a common efuse parsing function which will greatly reduce code duplication, add a SoC-specific mapping that will be used to retrieve the right SVS calibration values from the fuses. The maps are two: one is a Global Map used for reading parameters that are SVS-global, and one is a Bank Map for reading calibrations for each SVS Bank. While at it, also populate the map in the platform data for each SoC. Being this a preparation commit, there are no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 87 ++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index b5beb33c95ba..6c6f133c327f 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -340,6 +340,26 @@ static const char * const svs_type_names[SVSB_TYPE_MAX] = { "", "_LOW", "_HIGH" }; +enum svs_fusemap_dev { + BDEV_BDES, + BDEV_MDES, + BDEV_MTDES, + BDEV_DCBDET, + BDEV_DCMDET, + BDEV_MAX +}; + +enum svs_fusemap_glb { + GLB_FT_PGM, + GLB_VMIN, + GLB_MAX +}; + +struct svs_fusemap { + s8 index; + u8 ofst; +}; + /** * struct svs_platform - svs platform control * @base: svs platform register base @@ -375,12 +395,14 @@ struct svs_platform_data { struct svs_bank *banks; bool (*efuse_parsing)(struct svs_platform *svsp); int (*probe)(struct svs_platform *svsp); + const struct svs_fusemap *glb_fuse_map; const u32 *regs; u32 bank_max; }; /** * struct svs_bank - svs bank representation + * @dev_fuse_map: Bank fuse map data * @dev: bank device * @opp_dev: device for opp table/buck control * @init_completion: the timeout completion for bank init @@ -444,6 +466,7 @@ struct svs_platform_data { * opp_volt[i] = (volt[i] * volt_step) + volt_base; */ struct svs_bank { + const struct svs_fusemap *dev_fuse_map; struct device *dev; struct device *opp_dev; struct completion init_completion; @@ -2457,6 +2480,9 @@ static struct svs_bank svs_mt8195_banks[] = { .core_sel = 0x0fff0100, .int_st = BIT(0), .ctl0 = 0x00540003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 10, 16 }, { 10, 24 }, { 10, 0 }, { 8, 0 }, { 8, 8 } + } }, { .sw_id = SVSB_SWID_GPU, @@ -2486,6 +2512,9 @@ static struct svs_bank svs_mt8195_banks[] = { .tzone_htemp_voffset = 0, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 9, 16 }, { 9, 24 }, { 9, 0 }, { 8, 0 }, { 8, 8 } + }, }, }; @@ -2517,6 +2546,9 @@ static struct svs_bank svs_mt8192_banks[] = { .tzone_htemp_voffset = 0, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 10, 16 }, { 10, 24 }, { 10, 0 }, { 17, 0 }, { 17, 8 } + } }, { .sw_id = SVSB_SWID_GPU, @@ -2546,6 +2578,9 @@ static struct svs_bank svs_mt8192_banks[] = { .tzone_htemp_voffset = 0, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 9, 16 }, { 9, 24 }, { 17, 0 }, { 17, 16 }, { 17, 24 } + } }, }; @@ -2572,6 +2607,9 @@ static struct svs_bank svs_mt8188_banks[] = { .core_sel = 0x0fff0000, .int_st = BIT(0), .ctl0 = 0x00100003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } + } }, { .sw_id = SVSB_SWID_GPU, @@ -2601,6 +2639,9 @@ static struct svs_bank svs_mt8188_banks[] = { .tzone_htemp_voffset = 0, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } + } }, }; @@ -2629,6 +2670,9 @@ static struct svs_bank svs_mt8186_banks[] = { .core_sel = 0x0fff0100, .int_st = BIT(0), .ctl0 = 0x00540003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 3, 16 }, { 3, 24 }, { 3, 0 }, { 14, 16 }, { 14, 24 } + } }, { .sw_id = SVSB_SWID_CPU_BIG, @@ -2660,6 +2704,9 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_htemp_voffset = 8, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 2, 16 }, { 2, 24 }, { 2, 0 }, { 13, 0 }, { 13, 8 } + } }, { .sw_id = SVSB_SWID_CPU_LITTLE, @@ -2689,6 +2736,9 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_htemp_voffset = 8, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } + } }, { .sw_id = SVSB_SWID_CCI, @@ -2717,6 +2767,9 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_htemp_voffset = 8, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } + } }, { .sw_id = SVSB_SWID_GPU, @@ -2744,6 +2797,9 @@ static struct svs_bank svs_mt8186_banks[] = { .tzone_htemp_voffset = 8, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 6, 16 }, { 6, 24 }, { 6, 0 }, { 15, 8 }, { 15, 0 } + } }, }; @@ -2771,6 +2827,9 @@ static struct svs_bank svs_mt8183_banks[] = { .core_sel = 0x8fff0000, .int_st = BIT(0), .ctl0 = 0x00010001, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 16, 0 }, { 16, 8 }, { 17, 16 }, { 16, 16 }, { 16, 24 } + } }, { .sw_id = SVSB_SWID_CPU_BIG, @@ -2795,6 +2854,9 @@ static struct svs_bank svs_mt8183_banks[] = { .core_sel = 0x8fff0001, .int_st = BIT(1), .ctl0 = 0x00000001, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 18, 0 }, { 18, 8 }, { 17, 0 }, { 18, 16 }, { 18, 24 } + } }, { .sw_id = SVSB_SWID_CCI, @@ -2818,6 +2880,9 @@ static struct svs_bank svs_mt8183_banks[] = { .core_sel = 0x8fff0002, .int_st = BIT(2), .ctl0 = 0x00100003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 0 }, { 4, 8 }, { 5, 16 }, { 4, 16 }, { 4, 24 } + } }, { .sw_id = SVSB_SWID_GPU, @@ -2848,6 +2913,9 @@ static struct svs_bank svs_mt8183_banks[] = { .tzone_htemp_voffset = 0, .tzone_ltemp = 25000, .tzone_ltemp_voffset = 3, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 6, 0 }, { 6, 8 }, { 5, 0 }, { 6, 16 }, { 6, 24 } + } }, }; @@ -2858,6 +2926,9 @@ static const struct svs_platform_data svs_mt8195_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8195_banks), + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { + { 0, 0 }, { 19, 4 } + } }; static const struct svs_platform_data svs_mt8192_platform_data = { @@ -2867,6 +2938,10 @@ static const struct svs_platform_data svs_mt8192_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8192_banks), + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { + /* FT_PGM not present */ + { -1, 0 }, { 19, 4 } + } }; static const struct svs_platform_data svs_mt8188_platform_data = { @@ -2876,6 +2951,10 @@ static const struct svs_platform_data svs_mt8188_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8188_banks), + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { + /* FT_PGM and VMIN not present */ + { -1, 0 }, { -1, 0 } + } }; static const struct svs_platform_data svs_mt8186_platform_data = { @@ -2885,6 +2964,10 @@ static const struct svs_platform_data svs_mt8186_platform_data = { .probe = svs_mt8186_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8186_banks), + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { + /* FT_PGM and VMIN not present */ + { -1, 0 }, { -1, 0 } + } }; static const struct svs_platform_data svs_mt8183_platform_data = { @@ -2894,6 +2977,10 @@ static const struct svs_platform_data svs_mt8183_platform_data = { .probe = svs_mt8183_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8183_banks), + .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { + /* VMIN not present */ + { 0, 4 }, { -1, 0 } + } }; static const struct of_device_id svs_of_match[] = { From patchwork Tue Nov 21 11:56:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167690 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565297vqb; 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[23.128.96.37]) by mx.google.com with ESMTPS id lk5-20020a17090308c500b001bdc10170casi10685538plb.36.2023.11.21.03.59.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:59:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=AAip3lX8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D7BAF80E73E9; Tue, 21 Nov 2023 03:57:37 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234759AbjKUL5Z (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234696AbjKUL4s (ORCPT ); Tue, 21 Nov 2023 06:56:48 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88571D6A; Tue, 21 Nov 2023 03:56:41 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3F33D6607323; Tue, 21 Nov 2023 11:56:39 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567800; bh=n+I9YOPDM99MnwpUCp/Jyp5QiCWQ9S9IzP9LXdnM4XE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AAip3lX8sainuX5kpVdTIrGCqKuS6Q4JEdymjzNCyX6p5R1ldIL5l5QjdevQ7ANDT 6fH5FjFcBrylxvPMSwvi2ISCwFQu0Hiedm73yvbd0Cc3krTXSTjyaIbCAEFJvIvv5y 8IAdg7aVKFvLlxlwJl+bH7qcRInxOp7Qf8XLNq3rZXLtXsK0b4Apl+m6KgVFtTObbe HICu6OcbM9msMBbTz4EsE8OCItJ1m7+6C+PqRUrsFwuG8mkBkhjIoLDfZfcvvYRIBt SqOo4+YI3/KawA7hNDwDMsp/Lgq4yXlcmoPW4xaAkphx9J3TLPlc2pN00WVX1RH/5S VgqiJAkqfc1/w== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 08/20] soc: mediatek: mtk-svs: Add SVS-Thermal coefficient to SoC platform data Date: Tue, 21 Nov 2023 12:56:12 +0100 Message-ID: <20231121115624.56855-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:57:38 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174778461462646 X-GMAIL-MSGID: 1783174778461462646 In preparation for commonizing the efuse parsing function, add the SVS-Thermal coefficients for all SoCs for which said function can be commonized (MT8186, MT8188, MT8192, MT8195) and assign those to their platform data structure. That will be used to calculate the MTS parameter with the equation MTS = (ts_coeff * 2) / 1000 This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 6c6f133c327f..ab564d48092b 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -118,6 +118,10 @@ #define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16) #define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24) +/* SVS Thermal Coefficients */ +#define SVSB_TS_COEFF_MT8195 250460 +#define SVSB_TS_COEFF_MT8186 204650 + /* svs bank related setting */ #define BITS8 8 #define MAX_OPP_ENTRIES 16 @@ -374,6 +378,7 @@ struct svs_fusemap { * @bank_max: total number of svs banks * @efuse: svs efuse data received from NVMEM framework * @tefuse: thermal efuse data received from NVMEM framework + * @ts_coeff: thermal sensors coefficient */ struct svs_platform { void __iomem *base; @@ -388,6 +393,7 @@ struct svs_platform { u32 bank_max; u32 *efuse; u32 *tefuse; + u32 ts_coeff; }; struct svs_platform_data { @@ -398,6 +404,7 @@ struct svs_platform_data { const struct svs_fusemap *glb_fuse_map; const u32 *regs; u32 bank_max; + u32 ts_coeff; }; /** @@ -2926,6 +2933,7 @@ static const struct svs_platform_data svs_mt8195_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8195_banks), + .ts_coeff = SVSB_TS_COEFF_MT8195, .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { { 0, 0 }, { 19, 4 } } @@ -2938,6 +2946,7 @@ static const struct svs_platform_data svs_mt8192_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8192_banks), + .ts_coeff = SVSB_TS_COEFF_MT8195, .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { /* FT_PGM not present */ { -1, 0 }, { 19, 4 } @@ -2951,6 +2960,7 @@ static const struct svs_platform_data svs_mt8188_platform_data = { .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8188_banks), + .ts_coeff = SVSB_TS_COEFF_MT8195, .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { /* FT_PGM and VMIN not present */ { -1, 0 }, { -1, 0 } @@ -2964,6 +2974,7 @@ static const struct svs_platform_data svs_mt8186_platform_data = { .probe = svs_mt8186_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8186_banks), + .ts_coeff = SVSB_TS_COEFF_MT8186, .glb_fuse_map = (const struct svs_fusemap[GLB_MAX]) { /* FT_PGM and VMIN not present */ { -1, 0 }, { -1, 0 } @@ -3021,6 +3032,7 @@ static int svs_probe(struct platform_device *pdev) svsp->banks = svsp_data->banks; svsp->regs = svsp_data->regs; svsp->bank_max = svsp_data->bank_max; + svsp->ts_coeff = svsp_data->ts_coeff; ret = svsp_data->probe(svsp); if (ret) From patchwork Tue Nov 21 11:56:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167691 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565322vqb; Tue, 21 Nov 2023 03:59:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IHc07X/zhDzpdeNUgsUS9jh4GnseNYSIFgs+L6JkxLu3utRAKrx2pnAN7UOJ7NNMvPokwBv X-Received: by 2002:a05:6808:201f:b0:3b2:e48d:97b4 with SMTP id q31-20020a056808201f00b003b2e48d97b4mr14488042oiw.26.1700567989996; Tue, 21 Nov 2023 03:59:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700567989; cv=none; d=google.com; s=arc-20160816; b=nemG4xm322l0IQ4Qh5ww3HJCAlWYJ1iY2qjaPwitAIOY/MPUfZ11V4RGNSFlaIw7lb pokpkh8gmFY2+r5OSS94mjuJ+spzvSFUyE9UFp7uwNlUAzHdYVuz/DaDZImaBmhcYnKh hwEs3TKRg7sxaXvs3LNEW2a34P46bKcp430F82RaDqsKUPe1mE8nXWKhJ5H53jnZeXtj XbXuVmpnF26VWMz+114HHQnRDasygeV5+ZX+ziO96iQXGmQEyJ6kTIdzLusu1MpAfx/W pj9TEh84qfVDI2XBhm+e9E5rWxVnANy6iKSrAx+IrVNWfMGEEZgL08Z37PCg9Y8l4T1c UtvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/sTmpSUpUoBKaV3NeAFIU7m6PHTjrLFL8tG3Y3lCQEU=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=DIRAPgSFlmIbFwsozzf9rUX+0HKEbY69FZvrnLcPwkPGqGUe8AfkmNSbiMfpOb3dmy tapjgyMVRbFTVeGI0R1ZkmA3rJ2PU/KYEtcsKXgCXjF3euMTBnP/zB0k9jgikGBkQse1 +r8lBhiccC81+SUAPZW6ebKcxsaQKz71/ZrZEUYGx3FXPDLGtoQxKCqXkHaTMk1lp2j/ BZiKsItf/IAd4eQGd4MKVfGjKOnThRdpFNrXFtlGkaHfPphcXA1X7shJR6pc/1AEzh6x zQljIPYqbclOLm02W0ywlptgcSldyCmX7W/TZFCxTKWl7McxOBNYOGj7UEvrrhPGlNKf Bn+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=eAZdz6wB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id b36-20020a631b24000000b005b8f9dbbd5fsi10410137pgb.409.2023.11.21.03.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:59:49 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=eAZdz6wB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 5AFCF8104510; Tue, 21 Nov 2023 03:57:43 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234626AbjKUL52 (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234699AbjKUL4t (ORCPT ); Tue, 21 Nov 2023 06:56:49 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 441A2D47; Tue, 21 Nov 2023 03:56:42 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4752B6607325; Tue, 21 Nov 2023 11:56:40 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567801; bh=YAm2XwYefU2Wi2EmslwaPruVfwk8nKNQAa35BFgYSvI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eAZdz6wBDUxe/xFVk/DNfuWHvnngIcYV/5EIalT9o0s5s5zdYyOSPAy54MAAsldVc xvth4ox12dkpyxAdVHUuSyG8DLQ/qk0wASACPNF7io8uGC3tQA+mI/UbThqb6fYsbm il8HicYUL1jNMa8+VnCuorIk1WWzwJKU9fPokLWAya29dJpJuVBODgAIn306rCMbOm cbt3EPut0XwcGuJ0Prx+1dGvauuq1R/GO34UYyoR85zN7RFf5781E0u44XmNvaW7Nn jrqUviNyLVrQpOqJhJu0b1XBFlm1960ZsjKTrn4IkhCuGtZlgqHA2WiQah7qsjmMmR bCohB00TFTK9A== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 09/20] soc: mediatek: mtk-svs: Move t-calibration-data retrieval to svs_probe() Date: Tue, 21 Nov 2023 12:56:13 +0100 Message-ID: <20231121115624.56855-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:57:43 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174780886723496 X-GMAIL-MSGID: 1783174780886723496 The t-calibration-data (SVS-Thermal calibration data) shall exist for all SoCs or SVS won't work anyway: move it to the common svs_probe() function and remove it from all of the per-SoC efuse_parsing() probe callbacks. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 32 ++++++-------------------------- 1 file changed, 6 insertions(+), 26 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index ab564d48092b..1042af2aee3f 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1884,11 +1884,6 @@ static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) svsb->vmax += svsb->dvt_fixed; } - ret = svs_get_efuse_data(svsp, "t-calibration-data", - &svsp->tefuse, &svsp->tefuse_max); - if (ret) - return false; - for (i = 0; i < svsp->tefuse_max; i++) if (svsp->tefuse[i] != 0) break; @@ -1949,11 +1944,6 @@ static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) svsb->vmax += svsb->dvt_fixed; } - ret = svs_get_efuse_data(svsp, "t-calibration-data", - &svsp->tefuse, &svsp->tefuse_max); - if (ret) - return false; - for (i = 0; i < svsp->tefuse_max; i++) if (svsp->tefuse[i] != 0) break; @@ -2009,11 +1999,6 @@ static bool svs_mt8188_efuse_parsing(struct svs_platform *svsp) svsb->vmax += svsb->dvt_fixed; } - ret = svs_get_efuse_data(svsp, "t-calibration-data", - &svsp->tefuse, &svsp->tefuse_max); - if (ret) - return false; - for (i = 0; i < svsp->tefuse_max; i++) if (svsp->tefuse[i] != 0) break; @@ -2097,11 +2082,6 @@ static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) svsb->vmax += svsb->dvt_fixed; } - ret = svs_get_efuse_data(svsp, "t-calibration-data", - &svsp->tefuse, &svsp->tefuse_max); - if (ret) - return false; - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); if (!golden_temp) golden_temp = 50; @@ -2198,11 +2178,6 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) } } - ret = svs_get_efuse_data(svsp, "t-calibration-data", - &svsp->tefuse, &svsp->tefuse_max); - if (ret) - return false; - /* Thermal efuse parsing */ adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0); adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0); @@ -3040,8 +3015,13 @@ static int svs_probe(struct platform_device *pdev) ret = svs_get_efuse_data(svsp, "svs-calibration-data", &svsp->efuse, &svsp->efuse_max); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Cannot read SVS calibration\n"); + + ret = svs_get_efuse_data(svsp, "t-calibration-data", + &svsp->tefuse, &svsp->tefuse_max); if (ret) { - ret = -EPERM; + dev_err_probe(&pdev->dev, ret, "Cannot read SVS-Thermal calibration\n"); goto svs_probe_free_efuse; } From patchwork Tue Nov 21 11:56:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167697 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565715vqb; Tue, 21 Nov 2023 04:00:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IHA96cL7F6+PASGOwAetS+bl62yShfrjuqbGJFCPtjTGwhy8/DF+/ngkB5lprnz9TAhS6XU X-Received: by 2002:a05:6a00:301d:b0:693:3c11:4293 with SMTP id ay29-20020a056a00301d00b006933c114293mr10102017pfb.14.1700568024876; Tue, 21 Nov 2023 04:00:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700568024; cv=none; d=google.com; s=arc-20160816; b=KHzyLziUGoPgHDVSrAvC/hP92rc9VDHpOSgcYerAyOiM6CZys3NEGjBGrxKTUZPUVM OzsbvdUk5vduhTmLyIma+TvMfgsjSjIBTew+PVQlsAMH1WE9u3zQky0PPYDkzIqYxT9W KFJ4MuPFu9vxoGFbo+qTM9DBsQGqyc4Br4LvI0E4iHwi2epZ1wjnLqCGTl/RF7PeAYoD 4O9Crwm71xTZgDvAmtpYkeoiK6HVwvmKaXGzRgdF9uj5RQMjmhvm5yB+t5R9RQB3s7T1 Sr2vKiHYffE2ACw5fy+UTffBp2BvCwLcvvy9ghatQOlUriildkVKzuKH3vepAP5xLBqO 4RFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2jxZKtVyXB2tzqqlGVSJEMZeZf6/8BJWPByJAAdW+g4=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=jUMqK95A5UKc9dJWBFKwV8/KxIadVSQe8nrkcoHfr+Qb3OE8rxfNGaln/yPN++pKY7 UnPQbfYULCWsCu8Ldr7oWUKFZt0yjRKoYOe5M1urM69BujNrzQFapnvi0zkzQkbynhaK 5QRL9dxNOT1v/1Eai0Yx/qhQsJp/QqIIaDfp3Ya8sHeGiYf2+IwnPyNIpnmmeDwSSWrW JMq+UABFkYT1ZyjYoeUMhMuR4s8M4Xe4HuPiRr6dayk2kxKEjP+8ucA6Hast4cVmeOWA 8RhiLkFYwBDWnEUNtX6VbTtWIoZr90BQ1zlBzZ3Bq+5KiHiX8g/xwfebAKwANgG4ADvf 5qtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=HyFL+ES7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from lipwig.vger.email (lipwig.vger.email. [23.128.96.33]) by mx.google.com with ESMTPS id bw26-20020a056a02049a00b005bddb7249d3si11302369pgb.414.2023.11.21.04.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:00:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=HyFL+ES7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 8F53580ADC4C; Tue, 21 Nov 2023 03:59:19 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234615AbjKUL5k (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234711AbjKUL4u (ORCPT ); Tue, 21 Nov 2023 06:56:50 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9235CD76; Tue, 21 Nov 2023 03:56:43 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 52FED66072F6; Tue, 21 Nov 2023 11:56:41 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567802; bh=hkZjJ7q8rV2xyxskAur6iNWuCHUO3iI4tzSStjxhlcA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HyFL+ES7D/wGO2KdkhLZTW57/sSNnVJahWssqzmSZbuvNuy20H7/WwW+Fglx6jKtl MwQtwbBEyjUTWnJoW9NYY7Tw5/Ma1LEpUny8PQqLDg3pOIMttYhayHE3/xXN5orPwP WklLX4DaZrqhaCzBTBKHiP1TlTj5454sdpQtuuYIIWtrBIsmzC1WvThauVebb8FJUd eAWEqffxZsgvM9ZSjDeXa27kBY8HeS7dc4vWZyj5W7Am7YSbN/JnnLjr0gBZypI1dg zXNxpvAi5fPjlDZNZRXPbsiLvQezb4wku7QdI5l2B8Mczn346qk1tZklkW28w+ZzHA +xQ1O4lGs2pUA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 10/20] soc: mediatek: mtk-svs: Commonize efuse parse function for most SoCs Date: Tue, 21 Nov 2023 12:56:14 +0100 Message-ID: <20231121115624.56855-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:59:19 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174817229058454 X-GMAIL-MSGID: 1783174817229058454 Remove almost all of the per-SoC .efuse_parsing() callbacks and replace them with one common callback svs_common_parse_efuse(): to do that, also change the function signature of the callback to add the newly required pointer to struct svs_platform_data, containing the SVS-global fuse map. This is done for MT8186, MT8188, MT8192, MT8195. As for MT8183, the efuse parse function was simplified by using the new fuse maps. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 332 +++++++-------------------------- 1 file changed, 66 insertions(+), 266 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 1042af2aee3f..517a27c58888 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -122,6 +122,9 @@ #define SVSB_TS_COEFF_MT8195 250460 #define SVSB_TS_COEFF_MT8186 204650 +/* Algo helpers */ +#define FUSE_DATA_NOT_VALID U32_MAX + /* svs bank related setting */ #define BITS8 8 #define MAX_OPP_ENTRIES 16 @@ -399,7 +402,7 @@ struct svs_platform { struct svs_platform_data { char *name; struct svs_bank *banks; - bool (*efuse_parsing)(struct svs_platform *svsp); + bool (*efuse_parsing)(struct svs_platform *svsp, const struct svs_platform_data *pdata); int (*probe)(struct svs_platform *svsp); const struct svs_fusemap *glb_fuse_map; const u32 *regs; @@ -1838,264 +1841,83 @@ static int svs_get_efuse_data(struct svs_platform *svsp, return 0; } -static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) +static u32 svs_get_fuse_val(u32 *fuse_array, const struct svs_fusemap *fmap, u8 nbits) { - struct svs_bank *svsb; - u32 idx, i, ft_pgm, vmin, golden_temp; - int ret; - - for (i = 0; i < svsp->efuse_max; i++) - if (svsp->efuse[i]) - dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", - i, svsp->efuse[i]); - - if (!svsp->efuse[10]) { - dev_notice(svsp->dev, "svs_efuse[10] = 0x0?\n"); - return false; - } - - /* Svs efuse parsing */ - ft_pgm = svsp->efuse[0] & GENMASK(7, 0); - vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); - - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - - if (vmin == 0x1) - svsb->vmin = 0x1e; - - if (ft_pgm == 0) - svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; - - if (svsb->type == SVSB_TYPE_LOW) { - svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); - } else if (svsb->type == SVSB_TYPE_HIGH) { - svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); - } - - svsb->vmax += svsb->dvt_fixed; - } - - for (i = 0; i < svsp->tefuse_max; i++) - if (svsp->tefuse[i] != 0) - break; + u32 val; - if (i == svsp->tefuse_max) - golden_temp = 50; /* All thermal efuse data are 0 */ - else - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + if (fmap->index < 0) + return FUSE_DATA_NOT_VALID; - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - svsb->mts = 500; - svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; - } + val = fuse_array[fmap->index] >> fmap->ofst; + val &= GENMASK(nbits - 1, 0); - return true; + return val; } -static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) +static bool svs_is_available(struct svs_platform *svsp) { - struct svs_bank *svsb; - u32 idx, i, vmin, golden_temp; - int ret; + int i, num_populated = 0; - for (i = 0; i < svsp->efuse_max; i++) + /* If at least two fuse arrays are populated, SVS is calibrated */ + for (i = 0; i < svsp->efuse_max; i++) { if (svsp->efuse[i]) - dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", - i, svsp->efuse[i]); - - if (!svsp->efuse[9]) { - dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n"); - return false; - } - - /* Svs efuse parsing */ - vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); - - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - - if (vmin == 0x1) - svsb->vmin = 0x1e; - - if (svsb->type == SVSB_TYPE_LOW) { - svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0); - } else if (svsb->type == SVSB_TYPE_HIGH) { - svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0); - } + num_populated++; - svsb->vmax += svsb->dvt_fixed; + if (num_populated > 1) + return true; } - for (i = 0; i < svsp->tefuse_max; i++) - if (svsp->tefuse[i] != 0) - break; - - if (i == svsp->tefuse_max) - golden_temp = 50; /* All thermal efuse data are 0 */ - else - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); - - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - svsb->mts = 500; - svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; - } - - return true; + return false; } -static bool svs_mt8188_efuse_parsing(struct svs_platform *svsp) +static bool svs_common_parse_efuse(struct svs_platform *svsp, + const struct svs_platform_data *pdata) { - struct svs_bank *svsb; - u32 idx, i, golden_temp; - int ret; + const struct svs_fusemap *gfmap = pdata->glb_fuse_map; + struct svs_fusemap tfm = { 0, 24 }; + u32 golden_temp, val; + u8 ft_pgm, vmin; + int i; - for (i = 0; i < svsp->efuse_max; i++) - if (svsp->efuse[i]) - dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", - i, svsp->efuse[i]); - - if (!svsp->efuse[5]) { - dev_notice(svsp->dev, "svs_efuse[5] = 0x0?\n"); + if (!svs_is_available(svsp)) return false; - } - - /* Svs efuse parsing */ - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - - if (svsb->type == SVSB_TYPE_LOW) { - svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); - } else if (svsb->type == SVSB_TYPE_HIGH) { - svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); - svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0); - } - - svsb->vmax += svsb->dvt_fixed; - } - - for (i = 0; i < svsp->tefuse_max; i++) - if (svsp->tefuse[i] != 0) - break; - - if (i == svsp->tefuse_max) - golden_temp = 50; /* All thermal efuse data are 0 */ - else - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); - - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - svsb->mts = 500; - svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; - } - return true; -} + /* Get golden temperature from SVS-Thermal calibration */ + val = svs_get_fuse_val(svsp->tefuse, &tfm, 8); -static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) -{ - struct svs_bank *svsb; - u32 idx, i, golden_temp; - int ret; + /* If golden temp is not programmed, use the default of 50 */ + golden_temp = val ? val : 50; - for (i = 0; i < svsp->efuse_max; i++) - if (svsp->efuse[i]) - dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", - i, svsp->efuse[i]); + /* Parse fused SVS calibration */ + ft_pgm = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_FT_PGM], 8); + vmin = svs_get_fuse_val(svsp->efuse, &gfmap[GLB_VMIN], 2); - if (!svsp->efuse[0]) { - dev_notice(svsp->dev, "svs_efuse[0] = 0x0?\n"); - return false; - } + for (i = 0; i < svsp->bank_max; i++) { + struct svs_bank *svsb = &svsp->banks[i]; + const struct svs_fusemap *dfmap = svsb->dev_fuse_map; - /* Svs efuse parsing */ - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; + if (vmin == 1) + svsb->vmin = 0x1e; - switch (svsb->sw_id) { - case SVSB_SWID_CPU_BIG: - if (svsb->type == SVSB_TYPE_HIGH) { - svsb->mdes = (svsp->efuse[2] >> 24) & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[2] >> 16) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[2] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[13] >> 8) & GENMASK(7, 0); - svsb->dcbdet = svsp->efuse[13] & GENMASK(7, 0); - } else if (svsb->type == SVSB_TYPE_LOW) { - svsb->mdes = (svsp->efuse[3] >> 24) & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[3] >> 16) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[3] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[14] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[14] >> 16) & GENMASK(7, 0); - } - break; - case SVSB_SWID_CPU_LITTLE: - svsb->mdes = (svsp->efuse[4] >> 24) & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[4] >> 16) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[4] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[14] >> 8) & GENMASK(7, 0); - svsb->dcbdet = svsp->efuse[14] & GENMASK(7, 0); - break; - case SVSB_SWID_CCI: - svsb->mdes = (svsp->efuse[5] >> 24) & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[15] >> 24) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[15] >> 16) & GENMASK(7, 0); - break; - case SVSB_SWID_GPU: - svsb->mdes = (svsp->efuse[6] >> 24) & GENMASK(7, 0); - svsb->bdes = (svsp->efuse[6] >> 16) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[6] & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[15] >> 8) & GENMASK(7, 0); - svsb->dcbdet = svsp->efuse[15] & GENMASK(7, 0); - break; - default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); - return false; - } + if (ft_pgm == 0) + svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; + svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8); + svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8); + svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8); + svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8); + svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8); svsb->vmax += svsb->dvt_fixed; - } - - golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); - if (!golden_temp) - golden_temp = 50; - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - svsb->mts = 409; - svsb->bts = (((500 * golden_temp + 204650) / 1000) - 25) * 4; + svsb->mts = (svsp->ts_coeff * 2) / 1000; + svsb->bts = (((500 * golden_temp + svsp->ts_coeff) / 1000) - 25) * 4; } return true; } -static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) +static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, + const struct svs_platform_data *pdata) { struct svs_bank *svsb; int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0; @@ -2115,65 +1937,43 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) } /* Svs efuse parsing */ - ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0); + ft_pgm = svs_get_fuse_val(svsp->efuse, &pdata->glb_fuse_map[GLB_FT_PGM], 4); for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + const struct svs_fusemap *dfmap = svsb->dev_fuse_map; if (ft_pgm <= 1) svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; + svsb->mtdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MTDES], 8); + svsb->bdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_BDES], 8); + svsb->mdes = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_MDES], 8); + svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8); + svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8); + switch (svsb->sw_id) { case SVSB_SWID_CPU_LITTLE: - svsb->bdes = svsp->efuse[16] & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0); - svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0); - + case SVSB_SWID_CCI: if (ft_pgm <= 3) svsb->volt_od += 10; else svsb->volt_od += 2; break; case SVSB_SWID_CPU_BIG: - svsb->bdes = svsp->efuse[18] & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0); - if (ft_pgm <= 3) svsb->volt_od += 15; else svsb->volt_od += 12; break; - case SVSB_SWID_CCI: - svsb->bdes = svsp->efuse[4] & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0); - svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); - - if (ft_pgm <= 3) - svsb->volt_od += 10; - else - svsb->volt_od += 2; - break; case SVSB_SWID_GPU: - svsb->bdes = svsp->efuse[6] & GENMASK(7, 0); - svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0); - svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0); - svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0); - svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); - - if (ft_pgm >= 2) { + if (ft_pgm != FUSE_DATA_NOT_VALID && ft_pgm >= 2) { svsb->freq_base = 800000000; /* 800MHz */ svsb->dvt_fixed = 2; } break; default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); return false; } } @@ -2904,7 +2704,7 @@ static struct svs_bank svs_mt8183_banks[] = { static const struct svs_platform_data svs_mt8195_platform_data = { .name = "mt8195-svs", .banks = svs_mt8195_banks, - .efuse_parsing = svs_mt8195_efuse_parsing, + .efuse_parsing = svs_common_parse_efuse, .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8195_banks), @@ -2917,7 +2717,7 @@ static const struct svs_platform_data svs_mt8195_platform_data = { static const struct svs_platform_data svs_mt8192_platform_data = { .name = "mt8192-svs", .banks = svs_mt8192_banks, - .efuse_parsing = svs_mt8192_efuse_parsing, + .efuse_parsing = svs_common_parse_efuse, .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8192_banks), @@ -2931,7 +2731,7 @@ static const struct svs_platform_data svs_mt8192_platform_data = { static const struct svs_platform_data svs_mt8188_platform_data = { .name = "mt8188-svs", .banks = svs_mt8188_banks, - .efuse_parsing = svs_mt8188_efuse_parsing, + .efuse_parsing = svs_common_parse_efuse, .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8188_banks), @@ -2945,7 +2745,7 @@ static const struct svs_platform_data svs_mt8188_platform_data = { static const struct svs_platform_data svs_mt8186_platform_data = { .name = "mt8186-svs", .banks = svs_mt8186_banks, - .efuse_parsing = svs_mt8186_efuse_parsing, + .efuse_parsing = svs_common_parse_efuse, .probe = svs_mt8186_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8186_banks), @@ -3025,7 +2825,7 @@ static int svs_probe(struct platform_device *pdev) goto svs_probe_free_efuse; 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[23.128.96.38]) by mx.google.com with ESMTPS id qc3-20020a17090b288300b00277651787f1si11250842pjb.145.2023.11.21.03.58.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:58:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=oupFyi+d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 29BE4802D1DF; Tue, 21 Nov 2023 03:58:48 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234775AbjKUL5g (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234708AbjKUL4t (ORCPT ); Tue, 21 Nov 2023 06:56:49 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79D0110E5; Tue, 21 Nov 2023 03:56:44 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 57F686607314; Tue, 21 Nov 2023 11:56:42 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567803; bh=Ugc04MbnUnt7uzZ2TQCUP0pKACMxidFV1p9AUF2t0WA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oupFyi+dkVp3wZPbsyOa6kNYGMQKF22jHyHa2CWm5XkIUaNDHrD0Y11bwOUSupE8C bE4nAWLsQkYntF1emkKPXejuYjs4DOVAI7cTQIGOf8SHK7u68fLXsryzI9UzOY13Hc 85qWFkyFUA4kPYiha8KnqviWMbcgImTOE17HIhXfL694BEhXrdfym53f43IzBiCEPm h0K0kkR7lVEESu46CFCt49aL1F8AUwR1TFlABwNbBcWyIKscokh4aYL0qlUZFDGtHY YHLnfLBmemuh5ldvIp/GmZxLJ7OJoC38y8PKU6RyyVw9y51ucXTBx4vKRdSlBZvYi5 1HKIY1kh6Y0Tg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 11/20] soc: mediatek: mtk-svs: Drop supplementary svs per-bank pointer Date: Tue, 21 Nov 2023 12:56:15 +0100 Message-ID: <20231121115624.56855-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:58:48 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174724931739007 X-GMAIL-MSGID: 1783174724931739007 Drop the "pbank" pointer from struct svs_bank: this was used to simply pass a pointer to the SVS bank that the flow was working on. That for instance needs more locking, and it's avoidable by adding one more parameter to functions working on specific banks, either a bank index number, or passing the svs_bank pointer directly from the caller. Even if the locking can now be reduced, for now, it was still left in place for the sake of making sure to not introduce any stability and/or reliability regression. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 87 ++++++++++++++++------------------ 1 file changed, 40 insertions(+), 47 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 517a27c58888..e7df3a577b4c 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -372,7 +372,6 @@ struct svs_fusemap { * @base: svs platform register base * @dev: svs platform device * @main_clk: main clock for svs bank - * @pbank: svs bank pointer needing to be protected by spin_lock section * @banks: svs banks that svs platform supports * @rst: svs platform reset control * @efuse_max: total number of svs efuse @@ -387,7 +386,6 @@ struct svs_platform { void __iomem *base; struct device *dev; struct clk *main_clk; - struct svs_bank *pbank; struct svs_bank *banks; struct reset_control *rst; size_t efuse_max; @@ -483,8 +481,8 @@ struct svs_bank { struct regulator *buck; struct thermal_zone_device *tzd; struct mutex lock; /* lock to protect voltage update process */ - void (*set_freq_pct)(struct svs_platform *svsp); - void (*get_volts)(struct svs_platform *svsp); + void (*set_freq_pct)(struct svs_platform *svsp, struct svs_bank *svsb); + void (*get_volts)(struct svs_platform *svsp, struct svs_bank *svsb); char *name; char *buck_name; char *tzone_name; @@ -555,10 +553,8 @@ static void svs_writel_relaxed(struct svs_platform *svsp, u32 val, writel_relaxed(val, svsp->base + svsp->regs[rg_i]); } -static void svs_switch_bank(struct svs_platform *svsp) +static void svs_switch_bank(struct svs_platform *svsp, struct svs_bank *svsb) { - struct svs_bank *svsb = svsp->pbank; - svs_writel_relaxed(svsp, svsb->core_sel, CORESEL); } @@ -693,8 +689,7 @@ static void svs_bank_disable_and_restore_default_volts(struct svs_platform *svsp return; spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; - svs_switch_bank(svsp); + svs_switch_bank(svsp, svsb); svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); spin_unlock_irqrestore(&svs_lock, flags); @@ -926,9 +921,8 @@ static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx) return DIV_ROUND_UP(vx, 100); } -static void svs_get_bank_volts_v3(struct svs_platform *svsp) +static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *svsb) { - struct svs_bank *svsb = svsp->pbank; u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0; u32 middle_index = (svsb->opp_count / 2); @@ -1041,9 +1035,8 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp) } } -static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) +static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *svsb) { - struct svs_bank *svsb = svsp->pbank; u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0; u32 b_sft, shift_byte = 0, turn_pt; u32 middle_index = (svsb->opp_count / 2); @@ -1124,9 +1117,8 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) svs_writel_relaxed(svsp, freq_pct30, FREQPCT30); } -static void svs_get_bank_volts_v2(struct svs_platform *svsp) +static void svs_get_bank_volts_v2(struct svs_platform *svsp, struct svs_bank *svsb) { - struct svs_bank *svsb = svsp->pbank; u32 temp, i; temp = svs_readl_relaxed(svsp, VOP74); @@ -1181,9 +1173,8 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp) } } -static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) +static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp, struct svs_bank *svsb) { - struct svs_bank *svsb = svsp->pbank; u32 freqpct74_val, freqpct30_val; freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) | @@ -1201,12 +1192,13 @@ static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) } static void svs_set_bank_phase(struct svs_platform *svsp, + unsigned int bank_idx, enum svsb_phase target_phase) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs; - svs_switch_bank(svsp); + svs_switch_bank(svsp, svsb); des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) | FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes); @@ -1225,7 +1217,7 @@ static void svs_set_bank_phase(struct svs_platform *svsp, svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG); svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG); - svsb->set_freq_pct(svsp); + svsb->set_freq_pct(svsp, svsb); limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) | FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) | @@ -1267,18 +1259,20 @@ static void svs_set_bank_phase(struct svs_platform *svsp, } static inline void svs_save_bank_register_data(struct svs_platform *svsp, + unsigned short bank_idx, enum svsb_phase phase) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; enum svs_reg_index rg_i; for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++) svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i); } -static inline void svs_error_isr_handler(struct svs_platform *svsp) +static inline void svs_error_isr_handler(struct svs_platform *svsp, + unsigned short bank_idx) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n", __func__, svs_readl_relaxed(svsp, CORESEL)); @@ -1290,16 +1284,17 @@ static inline void svs_error_isr_handler(struct svs_platform *svsp) svs_readl_relaxed(svsp, SMSTATE1)); dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP)); - svs_save_bank_register_data(svsp, SVSB_PHASE_ERROR); + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_ERROR); svsb->phase = SVSB_PHASE_ERROR; svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); } -static inline void svs_init01_isr_handler(struct svs_platform *svsp) +static inline void svs_init01_isr_handler(struct svs_platform *svsp, + unsigned short bank_idx) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; u32 val; dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", @@ -1307,7 +1302,7 @@ static inline void svs_init01_isr_handler(struct svs_platform *svsp) svs_readl_relaxed(svsp, VDESIGN30), svs_readl_relaxed(svsp, DCVALUES)); - svs_save_bank_register_data(svsp, SVSB_PHASE_INIT01); + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT01); svsb->phase = SVSB_PHASE_INIT01; val = ~(svs_readl_relaxed(svsp, DCVALUES) & GENMASK(15, 0)) + 1; @@ -1325,32 +1320,34 @@ static inline void svs_init01_isr_handler(struct svs_platform *svsp) svsb->core_sel &= ~SVSB_DET_CLK_EN; } -static inline void svs_init02_isr_handler(struct svs_platform *svsp) +static inline void svs_init02_isr_handler(struct svs_platform *svsp, + unsigned short bank_idx) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", __func__, svs_readl_relaxed(svsp, VOP74), svs_readl_relaxed(svsp, VOP30), svs_readl_relaxed(svsp, DCVALUES)); - svs_save_bank_register_data(svsp, SVSB_PHASE_INIT02); + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT02); svsb->phase = SVSB_PHASE_INIT02; - svsb->get_volts(svsp); + svsb->get_volts(svsp, svsb); svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS); } -static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp) +static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp, + unsigned short bank_idx) { - struct svs_bank *svsb = svsp->pbank; + struct svs_bank *svsb = &svsp->banks[bank_idx]; - svs_save_bank_register_data(svsp, SVSB_PHASE_MON); + svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_MON); svsb->phase = SVSB_PHASE_MON; - svsb->get_volts(svsp); + svsb->get_volts(svsp, svsb); svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS); @@ -1368,7 +1365,6 @@ static irqreturn_t svs_isr(int irq, void *data) WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; /* Find out which svs bank fires interrupt */ if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) { @@ -1376,20 +1372,20 @@ static irqreturn_t svs_isr(int irq, void *data) continue; } - svs_switch_bank(svsp); + svs_switch_bank(svsp, svsb); int_sts = svs_readl_relaxed(svsp, INTSTS); svs_en = svs_readl_relaxed(svsp, SVSEN); if (int_sts == SVSB_INTSTS_F0_COMPLETE && svs_en == SVSB_PTPEN_INIT01) - svs_init01_isr_handler(svsp); + svs_init01_isr_handler(svsp, idx); else if (int_sts == SVSB_INTSTS_F0_COMPLETE && svs_en == SVSB_PTPEN_INIT02) - svs_init02_isr_handler(svsp); + svs_init02_isr_handler(svsp, idx); else if (int_sts & SVSB_INTSTS_FLD_MONVOP) - svs_mon_mode_isr_handler(svsp); + svs_mon_mode_isr_handler(svsp, idx); else - svs_error_isr_handler(svsp); + svs_error_isr_handler(svsp, idx); spin_unlock_irqrestore(&svs_lock, flags); break; @@ -1518,8 +1514,7 @@ static int svs_init01(struct svs_platform *svsp) } spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; - svs_set_bank_phase(svsp, SVSB_PHASE_INIT01); + svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT01); spin_unlock_irqrestore(&svs_lock, flags); time_left = wait_for_completion_timeout(&svsb->init_completion, @@ -1588,8 +1583,7 @@ static int svs_init02(struct svs_platform *svsp) reinit_completion(&svsb->init_completion); spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; - svs_set_bank_phase(svsp, SVSB_PHASE_INIT02); + svs_set_bank_phase(svsp, idx, SVSB_PHASE_INIT02); spin_unlock_irqrestore(&svs_lock, flags); time_left = wait_for_completion_timeout(&svsb->init_completion, @@ -1645,8 +1639,7 @@ static void svs_mon_mode(struct svs_platform *svsp) continue; spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; - svs_set_bank_phase(svsp, SVSB_PHASE_MON); + svs_set_bank_phase(svsp, idx, SVSB_PHASE_MON); spin_unlock_irqrestore(&svs_lock, flags); } } From patchwork Tue Nov 21 11:56:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167681 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp564538vqb; Tue, 21 Nov 2023 03:57:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IGPCYifPjiutca8OLETFbPQV2VWgW3S4f8l1yE0vJJ/KPWuYFnTtu9gZpXG8p8Ylitris4q X-Received: by 2002:a17:90b:3e85:b0:27d:882f:e6c5 with SMTP id rj5-20020a17090b3e8500b0027d882fe6c5mr8445487pjb.9.1700567876506; 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[2620:137:e000::3:8]) by mx.google.com with ESMTPS id w12-20020a17090a8a0c00b00280cd49099asi12748348pjn.46.2023.11.21.03.57.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:57:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=bVrM2xji; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 2D001802B559; Tue, 21 Nov 2023 03:57:46 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234769AbjKUL5c (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234618AbjKUL4t (ORCPT ); Tue, 21 Nov 2023 06:56:49 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83525D66; Tue, 21 Nov 2023 03:56:45 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5E1276607319; Tue, 21 Nov 2023 11:56:43 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567804; bh=zNfya3IwOleE3gv7u+f222r6Eh2oBHfy4LgRig9Wjl4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bVrM2xjiiOpHT1WFNYbQiLOIm4IKSnWHVz2zRUlCmWgwE/GQt53wmVCsAmEnwWVfy 32oyNkeJgVEYR8iF+2tifdd06ecgapOcqHD54aUPdnEfG1cZIpnaE8oIStUuvXYLTA +fcCh+mlyrUNuV7G2K6OPynHzm80/G+cIbw8oOnq2ZrIELrwN65KkBWiaojO/W86M8 /t3YaV0oIILzFMahy7TT4k4Wm9W8Rz62Na0CS0pGr2TUi1rFexgCeiAkiitL0suLE6 zG7c0zIO1AgaSAi2oNrfUUF66tUYQIY4HwvGXgCOMXOhnMFPvntbZPoZL+krzeMyFZ Q6zNJzDresGDg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 12/20] soc: mediatek: mtk-svs: Commonize MT8192 probe function for MT8186 Date: Tue, 21 Nov 2023 12:56:16 +0100 Message-ID: <20231121115624.56855-13-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:57:46 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174661247156442 X-GMAIL-MSGID: 1783174661247156442 Include the additions of svs_mt8186_platform_probe() in the common svs_mt8192_platform_probe() function, remove the former, and use the latter as .probe() callback for MT8186. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 44 ++++++---------------------------- 1 file changed, 7 insertions(+), 37 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index e7df3a577b4c..cd5064683506 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2119,7 +2119,6 @@ static struct device *svs_add_device_link(struct svs_platform *svsp, static int svs_mt8192_platform_probe(struct svs_platform *svsp) { struct device *dev; - struct svs_bank *svsb; u32 idx; svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); @@ -2133,40 +2132,7 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) "failed to get lvts device\n"); for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; - - if (svsb->type == SVSB_TYPE_HIGH) - svsb->opp_dev = svs_add_device_link(svsp, "gpu"); - else if (svsb->type == SVSB_TYPE_LOW) - svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); - - if (IS_ERR(svsb->opp_dev)) - return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), - "failed to get OPP device for bank %d\n", - idx); - } - - return 0; -} - -static int svs_mt8186_platform_probe(struct svs_platform *svsp) -{ - struct device *dev; - struct svs_bank *svsb; - u32 idx; - - svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); - if (IS_ERR(svsp->rst)) - return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), - "cannot get svs reset control\n"); - - dev = svs_add_device_link(svsp, "thermal-sensor"); - if (IS_ERR(dev)) - return dev_err_probe(svsp->dev, PTR_ERR(dev), - "failed to get lvts device\n"); - - for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; + struct svs_bank *svsb = &svsp->banks[idx]; switch (svsb->sw_id) { case SVSB_SWID_CPU_LITTLE: @@ -2177,7 +2143,11 @@ static int svs_mt8186_platform_probe(struct svs_platform *svsp) svsb->opp_dev = svs_add_device_link(svsp, "cci"); break; case SVSB_SWID_GPU: - svsb->opp_dev = svs_add_device_link(svsp, "gpu"); + if (svsb->type == SVSB_TYPE_LOW) + svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); + else + svsb->opp_dev = svs_add_device_link(svsp, "gpu"); + break; break; default: dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); @@ -2739,7 +2709,7 @@ static const struct svs_platform_data svs_mt8186_platform_data = { .name = "mt8186-svs", .banks = svs_mt8186_banks, .efuse_parsing = svs_common_parse_efuse, - .probe = svs_mt8186_platform_probe, + .probe = svs_mt8192_platform_probe, .regs = svs_regs_v2, .bank_max = ARRAY_SIZE(svs_mt8186_banks), .ts_coeff = SVSB_TS_COEFF_MT8186, From patchwork Tue Nov 21 11:56:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167683 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp564590vqb; Tue, 21 Nov 2023 03:58:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IGGn9bDmp9Xq9H/kkbw6ik1f95DvXIXGFzHbUJD26WmRPDLYxeNoShZBa9jNCLE5g1eheH8 X-Received: by 2002:a05:6a00:4c82:b0:6cb:4c84:43ce with SMTP id eb2-20020a056a004c8200b006cb4c8443cemr13288474pfb.34.1700567883559; Tue, 21 Nov 2023 03:58:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700567883; cv=none; d=google.com; s=arc-20160816; b=vIlaDAFieQLbvuhNFb60l8XvsxEzBeBt8lo1T3OvIDjSkCdB+IehRdBTs66es1rJmn wwhpClVRCTYVOWg5XWIMAZD1TRNIuaEifXSxRsbq1JohojFulzjd5h0DGM/xOVkF8RJD kOaVDBt9RsLqz5Law4xgSHPBPCLWRfHbyNDrqdM8Q0D5Vh9hZrShML9WPeFpOMVcU1iz ZEgufrD16p8hVNI851SNVhogJF15r7StWzwAQdgV67F8boBYLgVCom3YDTlan4dZqm3p +7Ocgu92xm8SabAaKvBTZKWhYOg+A8HZxurWvnrqwAnBJIAvouV7+P3UYX2vz9PY7ow8 covQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IAsuYrChTQ+mBfJ8/Sih8DwoRlV6uZI64nyaA9Bhlv4=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=YXWj3jOyo2zoBvzes3j3P5I+nkrN7NJZiW14c8kS8X6cEifJJvmhH1G4Z8fRnLovgo cOPVlexc8tQKUSOs+it7vCHhrQ+fiQSirkO0r0O8MgHs2TanVVQoUE9KBtmtfLd87fkV aafak9K//Xsagpxj+9OmUtKDxBAhBcYUylUt+aM5P2DschHUc74xBYwuKd4ooALvbNj3 y0HmFzz2HylmF+1C05y/WAT8NKe7uVbgyKIb0dLqOz8pomoAOrXWCeEJMXI0re3vKuZ+ bSDkIVXWC8V5A6g63BaMQ4qyQE9+NYaTOTaWgwofhSDgs8JhIYApp2HnFhHcRt6cN1tD E+kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=aHceQ1vn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from agentk.vger.email (agentk.vger.email. [23.128.96.32]) by mx.google.com with ESMTPS id g6-20020aa79f06000000b006cbc1f9b4e0si700440pfr.261.2023.11.21.03.58.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:58:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=aHceQ1vn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 373528030E7B; Tue, 21 Nov 2023 03:57:54 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234750AbjKUL5o (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234620AbjKUL4u (ORCPT ); Tue, 21 Nov 2023 06:56:50 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BDB8184; Tue, 21 Nov 2023 03:56:46 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 670666607286; Tue, 21 Nov 2023 11:56:44 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567805; bh=8hsTcNhO6pxrVZKfxLeF/xkr1pZ2hVQ5uEBZ0ICc55k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aHceQ1vnHLfI/3+yTa2b7QL3S0LI+9WlXjTnX+1I+7R6QLQ2voofHoPC3YRlLZ/0w H7Qj10n/A7JdsOcTFietCEnmzPO5wa2+chGKztg03Jm9uIwXTXm7nHSta9DW0GIlbG MKUhgeXEMPqBB7kMjURu14yuNzk8XCzhyQxPTStLQ6QWrpFfpMiRVmat9gcXxawTh8 Xz7T5RcX2r8D8/SP/D/c3RuaMTRlsJLJB77T+wbTTwvyLDbSvr4/u03PBLQbYQPBJb l43CIJKgfN4WXpIY7DKLjJLdEZS7hAQwVgWEtlmsUHEgL0v/R8h8C5psmlIlDSKN0i P+sWo4uig3Gkw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 13/20] soc: mediatek: mtk-svs: Remove redundant print in svs_get_efuse_data Date: Tue, 21 Nov 2023 12:56:17 +0100 Message-ID: <20231121115624.56855-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:57:54 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174668970338397 X-GMAIL-MSGID: 1783174668970338397 Callers of svs_get_efuse_data() are already printing an error in case anything goes wrong, and the error print for nvmem_cell_read() failure is redundant: remove it. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index cd5064683506..5fd9884dd20f 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1822,8 +1822,6 @@ static int svs_get_efuse_data(struct svs_platform *svsp, *svsp_efuse = nvmem_cell_read(cell, svsp_efuse_max); if (IS_ERR(*svsp_efuse)) { - dev_err(svsp->dev, "cannot read \"%s\" efuse: %ld\n", - nvmem_cell_name, PTR_ERR(*svsp_efuse)); nvmem_cell_put(cell); return PTR_ERR(*svsp_efuse); } From patchwork Tue Nov 21 11:56:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167692 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565367vqb; Tue, 21 Nov 2023 03:59:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IEA4sY6AxzcdhPw+THpEFjqCuZOndhAHox5j5t4rMi0ep2Cm1bIs3StyHDwBqUjeG8jSaes X-Received: by 2002:a05:6a20:2d25:b0:186:3083:4a64 with SMTP id g37-20020a056a202d2500b0018630834a64mr13760258pzl.23.1700567997183; Tue, 21 Nov 2023 03:59:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700567997; cv=none; d=google.com; s=arc-20160816; b=pzy/gJ97pwp9SDdLpD/rf4PI5pxrBLYOmhyzI7ZCG8kESzxfeXYO57Yd6Uimwy0Fee 03SuQDFGyWf2BDmxwgpArhm4nHzXWAUzTTvZyLAyxhglj0YvkCVdYGxjOWbmhNXJ94gD ffoE6uMJkUymy5fxe05ENEAiaWRCQzTygp84RydHLuBa8MaQIeWzzxOnJPx4BQ6AO6ku 28Mp1szOtqXPzJp3THIxZx8Kk/Mj1s0bfZAInHHYHRIeVJyAMYLKXv+e6PLhX04PL7Jg DT+88SNxhTjfcxVTWb7COypeXuTJ2ZWwo9xi+Manq7yhLmmGUbmFP/NlpVzrWnG9hjEW 1qxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BEImrCI/kXGGUJLIMX0kD855YKMvbpgOQwIUEihf9gQ=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=xWjgHN/rwxBLVZdz6p4OuJx02mu7GWF/BiI8le/QsnJT/D6tjY4tJhZE2oC9F7Mpxb UmLtxr1YLHuweY52Xs4cir2zjrOqXI8VInQa11ev6h7FchZYyOv3w81UECnUmtIC/0ID 13twIFbpKcjKQT9DSqpMHE4bp/I6WNDA7qTiKF2DgNe6V6YOYJ2Qf0idCYgCg+I8J/vy r1xUZEdvdfeVhrjBTVMRRwIxvQWAaGUivv8b2x/DbvK2At9E9d4YlfcDpdNyyB7kubVy A5DyA6KimzBkOyVClGtRFCIMul8BjdyxIzzcxs8ZwHyXlEP8ubgNPMmFDjblgEyz40y3 tG0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=OpDnSoPG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id e20-20020a656894000000b005c2017e77c0si9785272pgt.475.2023.11.21.03.59.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:59:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=OpDnSoPG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 2FAD081068CD; Tue, 21 Nov 2023 03:57:59 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234620AbjKUL5t (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234631AbjKUL4v (ORCPT ); Tue, 21 Nov 2023 06:56:51 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5999D63; Tue, 21 Nov 2023 03:56:47 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 73D99660731B; Tue, 21 Nov 2023 11:56:45 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567806; bh=EEiAga7/PEKFwq5/KS3naIy5UuB1z5wjPE5byYQKsG4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OpDnSoPGdSH1UzaeAKrP95OFmvISNmdjMD2sQMrcis1DwAE0iY57IcLuXpXMKNvG1 wgsn5gdgujm2irWdQuxHZk48L9cYQ5xahqFRwXRiRAiNQaobt+ahTQL8Y+XzUD2Dzo KtfZX8b2pVFWiO25m7E0s8NonOIxatF6SyRaSEXb3l/3L+nYrQogcikjHDda1rOek0 x00Jc8svE91glrxLm8VmYo2le9ZC1wXKMtXbYNLWZFlOtn7FfFIhazsOBxRYPXkikS ggSj/54pHRz8N7cMVU4Xg94djhV1anjwj9wf9p6UalW+scbGHy1zsQms5hAJixltE8 Vn1Smp6ABGFmw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 14/20] soc: mediatek: mtk-svs: Compress of_device_id entries Date: Tue, 21 Nov 2023 12:56:18 +0100 Message-ID: <20231121115624.56855-15-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:57:59 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174788468137560 X-GMAIL-MSGID: 1783174788468137560 Compress each entry to one line, as they fit in 84 columns, which is acceptable. While at it, also change the capital 'S' to 's' in 'sentinel'. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 5fd9884dd20f..ac36c2efcafa 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2731,24 +2731,12 @@ static const struct svs_platform_data svs_mt8183_platform_data = { }; static const struct of_device_id svs_of_match[] = { - { - .compatible = "mediatek,mt8195-svs", - .data = &svs_mt8195_platform_data, - }, { - .compatible = "mediatek,mt8192-svs", - .data = &svs_mt8192_platform_data, - }, { - .compatible = "mediatek,mt8188-svs", - .data = &svs_mt8188_platform_data, - }, { - .compatible = "mediatek,mt8186-svs", - .data = &svs_mt8186_platform_data, - }, { - .compatible = "mediatek,mt8183-svs", - .data = &svs_mt8183_platform_data, - }, { - /* Sentinel */ - }, + { .compatible = "mediatek,mt8195-svs", .data = &svs_mt8195_platform_data }, + { .compatible = "mediatek,mt8192-svs", .data = &svs_mt8192_platform_data }, + { .compatible = "mediatek,mt8188-svs", .data = &svs_mt8188_platform_data }, + { .compatible = "mediatek,mt8186-svs", .data = &svs_mt8186_platform_data }, + { .compatible = "mediatek,mt8183-svs", .data = &svs_mt8183_platform_data }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, svs_of_match); From patchwork Tue Nov 21 11:56:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167700 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp566124vqb; Tue, 21 Nov 2023 04:00:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IFIrtFks79wqLSYp9DbJZzmz4nQKtY9netk7BhZZx0JVwfoLkLePSiKws6ukxzZWSnJLgjW X-Received: by 2002:a17:902:d48b:b0:1cc:47c1:c2cb with SMTP id c11-20020a170902d48b00b001cc47c1c2cbmr3614938plg.2.1700568056871; Tue, 21 Nov 2023 04:00:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700568056; cv=none; d=google.com; s=arc-20160816; b=ekTDfrplCAjeJBKkzPSuVwN7Ipyt3cP10E9n3pDVM6g2SEVO7V73KFwfexGAtdvLqs 6975fZSrYAywUkpcGNYa7ClnjLl+3JAjG5EkOWySlQilVwuKS5MOT6+waUnSKv6tdxOR HtG6lcXWZ0fx7Nx95kXu6kYmwQd+aSho0Eu2b+b/1Bcfx0DPcz6ZJ1r1402FMJ3RKEVq GKrpTmdb2lMq0j6yaRGNraMl1EErlfcMI22B/MCijmKwOAfJDwCEDXerQAyh52SAR0G5 kvUuacFlUgDnGS0BKKbi8csQm9wlZV6kwaZ48069vs8ZsppRCoGsP2uO9ibgdUVxqvok 3ygQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=a5feH2/jkDCbwJZEcvQP2UexdyAXhgSRCA68qIaap+0=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=eTuKjticwumksA+BbQ3ir1lhf8zLQk9VTmrzr1Vp7ds5z0z6mUfNqxhbqBGGhGXEOL so4wVUut9xNw90Wmnq9xJ5qUT7y8l+U8XPaiBV+o0Bfis+/RDoDZxh328D0QOtdT/fWa tpKH3ssk2fyry4I8Vc0P2R+6GQ4OAhm9/aE2M5Ur6QnN08At+P1S5obHmoptG9egQTDS eZ+5oBwXpnVqOEGwS4g53+fHU8dJLyaB83T3IbnSvzQr2EXjnoxTJbV1GZcAb0bFEZcQ 0J+kNOtwYQXRBkgFg3+Ns8BrNB5aJdkUBzw0K2qrWyDL57cLL1eQrz4S6LdiW1x9Vop8 qCsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=NQzzsLAP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id h3-20020a635303000000b005bdbdd396eesi9847887pgb.633.2023.11.21.04.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:00:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=NQzzsLAP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id C3E7C80AD10B; Tue, 21 Nov 2023 03:58:11 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234732AbjKUL5w (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234629AbjKUL4v (ORCPT ); Tue, 21 Nov 2023 06:56:51 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F09D125; Tue, 21 Nov 2023 03:56:48 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7AA076607323; Tue, 21 Nov 2023 11:56:46 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567807; bh=mvDbP9LsG0x+WjQA4KRWvixfVCE355+sCyiuJX+FpKc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NQzzsLAPLWVCrdYb1WdDBdgCttHjg+D0GSUKO8RjcPy/S1k2NgVgf3dkE+E0FXCdV W7rrIfGI8UW1pl/ucspvIOj8CKAZX1Em5cBzG54xGK+yDXik/0Ej6GAyFbVzX+MEXw /N533xEVo4QceCSm+oyT2e1aL8RdKexn5Mx4Y6V9L5igobnE3IJqHjkpGGZIFhSgDe EnEGPDuOMKWivrUJi+OfHz56fSte8UE+K7sJpVvHztWxKUff84obzi2lwfggeuy/JU 2Iv13hIZftMUP85+47DDkz60ar/mP5ZhAuSk64Ci6MH4NuVW32zzvGlREIl+N5+Lb9 fytD6j3AUfIsw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 15/20] soc: mediatek: mtk-svs: Cleanup of svs_probe() function Date: Tue, 21 Nov 2023 12:56:19 +0100 Message-ID: <20231121115624.56855-16-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:58:12 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174851212772906 X-GMAIL-MSGID: 1783174851212772906 Cleanup the svs_probe() function: use dev_err_probe() where possible, change some efuse read failure gotos and then remove now impossible IS_ERR_OR_NULL() checks (as they will never return true) for nvmem (efuse read) failures. Also remove some unnecessary blank lines. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 32 +++++++++++--------------------- 1 file changed, 11 insertions(+), 21 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index ac36c2efcafa..ae0cc22a2941 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2775,14 +2775,13 @@ static int svs_probe(struct platform_device *pdev) } if (!svsp_data->efuse_parsing(svsp, svsp_data)) { - dev_err(svsp->dev, "efuse data parsing failed\n"); - ret = -EPERM; + ret = dev_err_probe(svsp->dev, -EINVAL, "efuse data parsing failed\n"); goto svs_probe_free_tefuse; } ret = svs_bank_resource_setup(svsp); if (ret) { - dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret); + dev_err_probe(svsp->dev, ret, "svs bank resource setup fail\n"); goto svs_probe_free_tefuse; } @@ -2794,43 +2793,40 @@ static int svs_probe(struct platform_device *pdev) svsp->main_clk = devm_clk_get(svsp->dev, "main"); if (IS_ERR(svsp->main_clk)) { - dev_err(svsp->dev, "failed to get clock: %ld\n", - PTR_ERR(svsp->main_clk)); - ret = PTR_ERR(svsp->main_clk); + ret = dev_err_probe(svsp->dev, PTR_ERR(svsp->main_clk), + "failed to get clock\n"); goto svs_probe_free_tefuse; } ret = clk_prepare_enable(svsp->main_clk); if (ret) { - dev_err(svsp->dev, "cannot enable main clk: %d\n", ret); + dev_err_probe(svsp->dev, ret, "cannot enable main clk\n"); goto svs_probe_free_tefuse; } svsp->base = of_iomap(svsp->dev->of_node, 0); if (IS_ERR_OR_NULL(svsp->base)) { - dev_err(svsp->dev, "cannot find svs register base\n"); - ret = -EINVAL; + ret = dev_err_probe(svsp->dev, -EINVAL, "cannot find svs register base\n"); goto svs_probe_clk_disable; } ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, IRQF_ONESHOT, svsp_data->name, svsp); if (ret) { - dev_err(svsp->dev, "register irq(%d) failed: %d\n", - svsp_irq, ret); + dev_err_probe(svsp->dev, ret, "register irq(%d) failed\n", svsp_irq); goto svs_probe_iounmap; } ret = svs_start(svsp); if (ret) { - dev_err(svsp->dev, "svs start fail: %d\n", ret); + dev_err_probe(svsp->dev, ret, "svs start fail\n"); goto svs_probe_iounmap; } #ifdef CONFIG_DEBUG_FS ret = svs_create_debug_cmds(svsp); if (ret) { - dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret); + dev_err_probe(svsp->dev, ret, "svs create debug cmds fail\n"); goto svs_probe_iounmap; } #endif @@ -2839,18 +2835,12 @@ static int svs_probe(struct platform_device *pdev) svs_probe_iounmap: iounmap(svsp->base); - svs_probe_clk_disable: clk_disable_unprepare(svsp->main_clk); - svs_probe_free_tefuse: - if (!IS_ERR_OR_NULL(svsp->tefuse)) - kfree(svsp->tefuse); - + kfree(svsp->tefuse); svs_probe_free_efuse: - if (!IS_ERR_OR_NULL(svsp->efuse)) - kfree(svsp->efuse); - + kfree(svsp->efuse); return ret; } From patchwork Tue Nov 21 11:56:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167695 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565489vqb; Tue, 21 Nov 2023 04:00:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IHIrwPFAKNGvfKromAFPOX66rUci7670Y/W8lmerf2TMYd/bxAjD46fcmvlqDS+Of+rSzV+ X-Received: by 2002:a05:6808:1410:b0:3b2:e536:a442 with SMTP id w16-20020a056808141000b003b2e536a442mr14621095oiv.16.1700568006064; Tue, 21 Nov 2023 04:00:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700568006; cv=none; d=google.com; s=arc-20160816; b=KrkPiKs+2TOG7kzL6JnsIr+vV2q8W3JbY+97S7iLD3NE92AZTVBEs1xf9btEkg+VUW gIJtAEbSySNOXMUlDhKeOZrm71fdXCR+yvaT5ffeoEovPdJEaXWEva+jszsJZYY/C9b4 jvtlxJObHypt4NmhZjC2xz3RPE0MgYWYEwAIhDsxQh4GYNefy6+Nc8PFbz7UDu0AjDNb tK8vG6MPacTzfQkH/5xcPIE758+38l7t3OzCn7+TOo2YAP5Z2uY2j09OnMH3I8PbTkEO oCplNXcURkvgB6B8o3BERob1vXZ+1gsxuUjmvJ+zq2zDmSB2OqBY3u9z0WB3153S7OG3 kQvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KpBUxqYvBKX4tX03KjbJxbiKYB0CW1q5AbspkuYc90k=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=rgws8GmUJr2H1iS7WupYv6i/i45MqFlGE6BjmaCUbbCf7BivcANLJnJejoMkfzL88l Xwv1qxPgrNhycjmzsZI4sqmQjxKSvDCjTG+ZD0kn7sagmTUj/vYnrih+shnSbN2bJJHm LEGNF1e3rk/MwfvvGRtnOpblVjhc9dnLrNJGg07KRfVmeFHDUmzohFJRnk0CKMTnm9Wl FoOuLK7xX2RvJjvzbiMSKk1OcYZx23pKgaFLEi6Wzox9utVI2T+Su35EUnyWTQ/Yuv/0 Iwv6JZ02HH+CbllPvGV7lnlQd3ZgMBZxV8TwzPK1EtRhRu2SPozdtBGKjzP4iHs2K1P2 a9hA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=GYYbo9Ql; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id l184-20020a6325c1000000b00578e0ff59bbsi10410922pgl.865.2023.11.21.04.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:00:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=GYYbo9Ql; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id E00EC81121E1; Tue, 21 Nov 2023 03:58:14 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234811AbjKUL6B (ORCPT + 99 others); Tue, 21 Nov 2023 06:58:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234198AbjKUL4x (ORCPT ); Tue, 21 Nov 2023 06:56:53 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84D6A1A2; Tue, 21 Nov 2023 03:56:49 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 852916607324; Tue, 21 Nov 2023 11:56:47 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567808; bh=XEVVBoXHkUpKz+mYu2BhuD+v7qTvXaba6bcEiQ5SYSg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GYYbo9QldXFXkudLNK5rBpyLOm3Syq0rkmS15Dw5elqhdCQEjLJ8kZzlIAH/9feSQ fKlAppZeczG0BvHBMcVMzFWOKlTqcdLR38gs+mDI8TFzbgqxnvL3+7ke7vlfaIarOE WD4+zgmW1iKsLDiocSUyAnRL7xZwxGw2tTmygpebAcSBxHok6hcBdGsl3UxPU4RhG9 8XEQk0x8kv80N5b4iMA7KyObYnlaCUOR78JlP1dzoe2MuBlgaduv01uzC1TJkOv2/K NbRxwgmUpxDmArQm49ItmhnUMfHWIiHPkJZFJP92lDNXXN9DWJqILJhvwM+4X/RRD7 +oX/uQYLfW/Jg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 16/20] soc: mediatek: mtk-svs: Check if SVS mode is available in the beginning Date: Tue, 21 Nov 2023 12:56:20 +0100 Message-ID: <20231121115624.56855-17-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:58:15 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174797596911517 X-GMAIL-MSGID: 1783174797596911517 The svs_init01() and svs_init02() functions are already checking if the INIT01 and INIT02 modes are available - but that's done in for loops and for each SVS bank. Give those a shortcut to get out early if no SVS bank features the desired init mode: this is especially done to avoid some locking in the svs_init01(), but also to avoid multiple for loops to check the same, when no bank supports a specific mode. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index ae0cc22a2941..16a16c5a3f24 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1400,6 +1400,16 @@ static irqreturn_t svs_isr(int irq, void *data) return IRQ_HANDLED; } +static bool svs_mode_available(struct svs_platform *svsp, u8 mode) +{ + int i; + + for (i = 0; i < svsp->bank_max; i++) + if (svsp->banks[i].mode_support & mode) + return true; + return false; +} + static int svs_init01(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -1408,6 +1418,9 @@ static int svs_init01(struct svs_platform *svsp) int ret = 0, r; u32 opp_freq, opp_vboot, buck_volt, idx, i; + if (!svs_mode_available(svsp, SVSB_MODE_INIT01)) + return 0; + /* Keep CPUs' core power on for svs_init01 initialization */ cpuidle_pause_and_lock(); @@ -1575,6 +1588,9 @@ static int svs_init02(struct svs_platform *svsp) int ret; u32 idx; + if (!svs_mode_available(svsp, SVSB_MODE_INIT02)) + return 0; + for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; From patchwork Tue Nov 21 11:56:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167696 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565503vqb; Tue, 21 Nov 2023 04:00:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IFq2TlE9GzqF15Fyc2bFtnQMNqbivbfos50PtS+bp89cu2hdqYxFiwIZXsEalPqAdbDw45j X-Received: by 2002:a05:6808:a9b:b0:3a9:c2fe:335c with SMTP id q27-20020a0568080a9b00b003a9c2fe335cmr12201892oij.52.1700568007569; Tue, 21 Nov 2023 04:00:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700568007; cv=none; d=google.com; s=arc-20160816; b=AmL0FEqOOp3pwC0pBjqxRKVmR2HFtRTP/zgaX2+VtwkF4YZ8KRxYZh7FRvhYI5njgt Olbd8r9wUB+kM9DG3Vj96Fj5LB5dnIta9kRQUvhM41rBttsD4P4GXDCdglB44STPRTqw 2qnA240qPH2HC+J9fJQ3VLljwVlc1Jd6ceDMIyoSXreZQLOVxZcTFj8igrQTtdTyLgRO lAmm5uDF7nxc0s9t4zUm6t57EcVg2HMnDnjiW0gQh3NmkLk+IN4QQzlnMPU6dcsbzbj6 VGtFbzRrdUt9r24ROaRq2K09MwzEYaGPAsKLOcnTPrn1BCxoLU0gaCG0CIG0AKL2WDaH kHAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bshaVLl7I5VmG/9PhcP3nuXBjaqS8pv5wJ1Ry067DEY=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=xBU+M6qv5DOOcZVg14bH2gTrlYEmh8HyRg9c3rAgKvIqFOlUPW0zTNO/zsok45Jtks xCo2JjW+fZ6QEGr/kM31koIfdxx4DQz/F0iayQtUw7t/w+Rtb++gE2crqHz5UZxo9Ba8 fADc3p78QX7GQjuorKhBlqAzKX4NJICRt/1tfEZvTqNuhdDzjmXVx+QGlf/1K6gnavkz oag9FnOw1DV4UTaooaNLTRlNGHKs4my2M8eoEvvsTfd2s799ZkelKSgCAJ6wBjbxu+RV BZccAbQ7sVPpCcqNvXgmOIJn9/K+9GW2GsPfCaCmZQP1YOi17TRoWZczDqoVg9G0jF5G APXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=dHgS1RJq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id bn22-20020a056a02031600b005b96af23fe8si10901724pgb.424.2023.11.21.04.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:00:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=dHgS1RJq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D403381121ED; Tue, 21 Nov 2023 03:58:16 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234730AbjKUL6E (ORCPT + 99 others); Tue, 21 Nov 2023 06:58:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234616AbjKUL4y (ORCPT ); Tue, 21 Nov 2023 06:56:54 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F29713D; Tue, 21 Nov 2023 03:56:50 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 8D74B6607326; Tue, 21 Nov 2023 11:56:48 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567809; bh=P8X/98SRN6b58tyqRku7rqXinlOozOu5V7sRiK56qy0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dHgS1RJq0Qde42IELsuCTHqSQUUMs2O5o3pr6jsaRfeWgucPLnjDnNFC+734Mq2l8 ev3lxVepD9nZeneSZtjzM9cCNvo0vLgJh5rTGhiRsh/Aq1XNMzckz1syPTnrmkvOeN badIDZ0WLaQGPbm9sRVl+I3MSUE/LrPj14tQEQOccy6XJqFy8x3KQW0RAaMX9uwumR OGX/i75TqF4MZ8mlRJrzvgpeVRXxowj0odh5PX8/dK85bg6ds3rLu47pz12MGAV9a9 WWpEf6mwTIHCnv3Y4fXFfUmJz6iQlnQH1reXh2BtjImAQiFaxF7DnCTU8bIrmoCw2R tICxMBVJU6E+Q== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 17/20] soc: mediatek: mtk-svs: Use ULONG_MAX to compare floor frequency Date: Tue, 21 Nov 2023 12:56:21 +0100 Message-ID: <20231121115624.56855-18-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:58:17 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174798988357930 X-GMAIL-MSGID: 1783174798988357930 The `freq` variable is of type unsigned long and, even though it does currently work with u32 because no frequency is higher than U32_MAX, it is not guaranteed that in the future we will see one. Initialize the freq variable with ULONG_MAX instead of U32_MAX. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 16a16c5a3f24..df39e7430ba9 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1804,7 +1804,7 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) return count; } - for (i = 0, freq = U32_MAX; i < svsb->opp_count; i++, freq--) { + for (i = 0, freq = ULONG_MAX; i < svsb->opp_count; i++, freq--) { opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); if (IS_ERR(opp)) { dev_err(svsb->dev, "cannot find freq = %ld\n", From patchwork Tue Nov 21 11:56:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167698 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565824vqb; Tue, 21 Nov 2023 04:00:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IHlg9jS1ySfmBafWuNyksprdZrwis/dxf/gnhhpcs+pguKwTEH0vMXFQVn9dOrtO+sNbpC4 X-Received: by 2002:a17:903:11c9:b0:1cc:4677:2f0e with SMTP id q9-20020a17090311c900b001cc46772f0emr14755247plh.45.1700568032159; Tue, 21 Nov 2023 04:00:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700568032; cv=none; d=google.com; s=arc-20160816; b=uBdRYFHTPE03whn15S1kJu8HI4HZzCJ2yUF8k4tNjlILSYKgHFzmnfjgUS14SKKbAH g7Cq/gdjbSTE6BDAf6atWCIGEZoquIkJtCF23zDQ6WXGFYgAMqlmf8Vgb5cS6UEE8dEN TbldErsRkbqPW8vJfKB9D3a1+yON9rxe0/LJ1N4sPIq8+uDckfvQFuo5BOczZUlTv11g D61KupjiboNfXCNMumdmbWQ194z1nE3aQv37ERhhUU8xppQGqUnkSFO5QjVw8tsfl75m oZ9TcxM3/E34844Ypkf2d0ZCrhA7akrFzxFhPQDWvgQ8kpv9Fql09SrtQtpFjyOStCtP xIqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fdG5BmuUkc1ZMEkiEdfTj0e0Jjv8hEQyJAct0OUGOkA=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=lN1LW8xw1bJNMLQerL6RLQuzfARMsPqyVQu0jGMG5yIO9NzvAqMp3ZXyGSCYV/Dmic 3Hz51IbtMISmDuftBY94KM9b1IXecR1wO9RKKgt//h5K08RGHx2mxviqoW5Qrmrv4f0H Kwf5/iM4cnV+ajiSGztuJXT7w/bQ2nQIOUOFrbuGpRxG8J7Iq4f9JXQWrms97uN74gJJ gq1Zd01pesTqZ5mlUnPr/IAjJx4XytsqUw8nYbllZQ1icDC3oiRJbYW9kz/7ICW6KAbN GOudOMklggol1CAZfFn82g+cM4E6hzN51vQZ4YHdRrUFMiL+lunYDe0al26DGKeP0KPw nGvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=MjLnR2Qy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from lipwig.vger.email (lipwig.vger.email. [23.128.96.33]) by mx.google.com with ESMTPS id be3-20020a170902aa0300b001bc2fd76db1si9865830plb.65.2023.11.21.04.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:00:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=MjLnR2Qy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 0948C8027E1F; Tue, 21 Nov 2023 03:59:57 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234818AbjKUL6J (ORCPT + 99 others); Tue, 21 Nov 2023 06:58:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234655AbjKUL5A (ORCPT ); Tue, 21 Nov 2023 06:57:00 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97477138; Tue, 21 Nov 2023 03:56:51 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 965A46607325; Tue, 21 Nov 2023 11:56:49 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567810; bh=Pu4oDjRhp53TiMI39QPJwqnQNaHhKRmvMoh9oOhmbto=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MjLnR2Qy8oeAsDRY0Xdbr4OafSXctmnJ1R9iGwWFK7/yrAxmG3Utzau6ohX8FrbYY EOpJ5mAtP1GEhnEUCXuk1Ox8VQ6EPCXWRH3S4z7uSoCXzBF8rXWv+LYM5WX32XnImq Z6vSQAuDob9PPT9+dZO3y9FBETbWFiCs2APKZZ6/fIJyLMQ7TLwR7PEJ4K+Azn6WkO wUWdBRtMMfCTbc3ZhBkRXHmumJDiuKUOO+2pe3QgpGttAUA3IZY6HdQGDKNPxvlewp 49I8dU5W0/R8jKAOG1bleNChSLELvaDe39N3xrAZv3FKWvhUebXUz5/bZzYbBsWpHV PBuvAqQfYNEhw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 18/20] soc: mediatek: mtk-svs: Constify runtime-immutable members of svs_bank Date: Tue, 21 Nov 2023 12:56:22 +0100 Message-ID: <20231121115624.56855-19-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:59:57 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174824476580997 X-GMAIL-MSGID: 1783174824476580997 Some members of struct svs_bank are not changed during runtime, so those are not variables but constants: move all of those to a new structure called svs_bank_pdata and refactor the code to make use of that and reorder members by size where possible. This effectively moves at least 50 bytes to the text segment. While at it, also uniform the thermal zone names across the banks. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 1198 +++++++++++++++++--------------- 1 file changed, 628 insertions(+), 570 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index df39e7430ba9..edf4ab14bc23 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2022 MediaTek Inc. + * Copyright (C) 2022 Collabora Ltd. + * AngeloGioacchino Del Regno */ #include @@ -377,10 +379,10 @@ struct svs_fusemap { * @efuse_max: total number of svs efuse * @tefuse_max: total number of thermal efuse * @regs: svs platform registers map - * @bank_max: total number of svs banks * @efuse: svs efuse data received from NVMEM framework * @tefuse: thermal efuse data received from NVMEM framework * @ts_coeff: thermal sensors coefficient + * @bank_max: total number of svs banks */ struct svs_platform { void __iomem *base; @@ -391,10 +393,10 @@ struct svs_platform { size_t efuse_max; size_t tefuse_max; const u32 *regs; - u32 bank_max; u32 *efuse; u32 *tefuse; u32 ts_coeff; + u16 bank_max; }; struct svs_platform_data { @@ -404,59 +406,92 @@ struct svs_platform_data { int (*probe)(struct svs_platform *svsp); const struct svs_fusemap *glb_fuse_map; const u32 *regs; - u32 bank_max; u32 ts_coeff; + u16 bank_max; }; /** - * struct svs_bank - svs bank representation + * struct svs_bank_pdata - SVS Bank immutable config parameters * @dev_fuse_map: Bank fuse map data + * @buck_name: Regulator name + * @tzone_name: Thermal zone name + * @age_config: Bank age configuration + * @ctl0: TS-x selection + * @dc_config: Bank dc configuration + * @int_st: Bank interrupt identification + * @turn_freq_base: Reference frequency for 2-line turn point + * @tzone_htemp: Thermal zone high temperature threshold + * @tzone_ltemp: Thermal zone low temperature threshold + * @volt_step: Bank voltage step + * @volt_base: Bank voltage base + * @tzone_htemp_voffset: Thermal zone high temperature voltage offset + * @tzone_ltemp_voffset: Thermal zone low temperature voltage offset + * @chk_shift: Bank chicken shift + * @cpu_id: CPU core ID for SVS CPU bank use only + * @opp_count: Bank opp count + * @vboot: Voltage request for bank init01 only + * @vco: Bank VCO value + * @sw_id: Bank software identification + * @type: SVS Bank Type (1 or 2-line) and Role (high/low) + * @set_freq_pct: function pointer to set bank frequency percent table + * @get_volts: function pointer to get bank voltages + */ +struct svs_bank_pdata { + const struct svs_fusemap *dev_fuse_map; + char *buck_name; + char *tzone_name; + u32 age_config; + u32 ctl0; + u32 dc_config; + u32 int_st; + u32 turn_freq_base; + u32 tzone_htemp; + u32 tzone_ltemp; + u32 volt_step; + u32 volt_base; + u16 tzone_htemp_voffset; + u16 tzone_ltemp_voffset; + u8 chk_shift; + u8 cpu_id; + u8 opp_count; + u8 vboot; + u8 vco; + u8 sw_id; + u8 type; + + /* Callbacks */ + void (*set_freq_pct)(struct svs_platform *svsp, struct svs_bank *svsb); + void (*get_volts)(struct svs_platform *svsp, struct svs_bank *svsb); +}; + +/** + * struct svs_bank - svs bank representation + * @pdata: SVS Bank immutable config parameters * @dev: bank device * @opp_dev: device for opp table/buck control * @init_completion: the timeout completion for bank init * @buck: regulator used by opp_dev * @tzd: thermal zone device for getting temperature * @lock: mutex lock to protect voltage update process - * @set_freq_pct: function pointer to set bank frequency percent table - * @get_volts: function pointer to get bank voltages * @name: bank name - * @buck_name: regulator name - * @tzone_name: thermal zone name * @phase: bank current phase * @volt_od: bank voltage overdrive * @reg_data: bank register data in different phase for debug purpose * @pm_runtime_enabled_count: bank pm runtime enabled count - * @mode_support: bank mode support. + * @mode_support: bank mode support * @freq_base: reference frequency for bank init - * @turn_freq_base: refenrece frequency for 2-line turn point - * @vboot: voltage request for bank init01 only * @opp_dfreq: default opp frequency table * @opp_dvolt: default opp voltage table * @freq_pct: frequency percent table for bank init * @volt: bank voltage table - * @volt_step: bank voltage step - * @volt_base: bank voltage base * @volt_flags: bank voltage flags * @vmax: bank voltage maximum * @vmin: bank voltage minimum - * @age_config: bank age configuration * @age_voffset_in: bank age voltage offset - * @dc_config: bank dc configuration * @dc_voffset_in: bank dc voltage offset * @dvt_fixed: bank dvt fixed value - * @vco: bank VCO value - * @chk_shift: bank chicken shift * @core_sel: bank selection - * @opp_count: bank opp count - * @int_st: bank interrupt identification - * @sw_id: bank software identification - * @cpu_id: cpu core id for SVS CPU bank use only - * @ctl0: TS-x selection * @temp: bank temperature - * @tzone_htemp: thermal zone high temperature threshold - * @tzone_htemp_voffset: thermal zone high temperature voltage offset - * @tzone_ltemp: thermal zone low temperature threshold - * @tzone_ltemp_voffset: thermal zone low temperature voltage offset * @bts: svs efuse data * @mts: svs efuse data * @bdes: svs efuse data @@ -466,61 +501,41 @@ struct svs_platform_data { * @dcmdet: svs efuse data * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank * @vbin_turn_pt: voltage bin turn point helps know which svsb_volt should be overridden - * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank * - * Svs bank will generate suitalbe voltages by below general math equation + * Svs bank will generate suitable voltages by below general math equation * and provide these voltages to opp voltage table. * * opp_volt[i] = (volt[i] * volt_step) + volt_base; */ struct svs_bank { - const struct svs_fusemap *dev_fuse_map; + const struct svs_bank_pdata pdata; struct device *dev; struct device *opp_dev; struct completion init_completion; struct regulator *buck; struct thermal_zone_device *tzd; - struct mutex lock; /* lock to protect voltage update process */ - void (*set_freq_pct)(struct svs_platform *svsp, struct svs_bank *svsb); - void (*get_volts)(struct svs_platform *svsp, struct svs_bank *svsb); + struct mutex lock; + int pm_runtime_enabled_count; + short int volt_od; char *name; - char *buck_name; - char *tzone_name; enum svsb_phase phase; - short int volt_od; u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX]; - u32 pm_runtime_enabled_count; u8 mode_support; - u32 freq_base; - u32 turn_freq_base; - u8 vboot; u32 opp_dfreq[MAX_OPP_ENTRIES]; u32 opp_dvolt[MAX_OPP_ENTRIES]; u32 freq_pct[MAX_OPP_ENTRIES]; u32 volt[MAX_OPP_ENTRIES]; - u32 volt_step; - u32 volt_base; u32 volt_flags; - u8 vmax; - u8 vmin; - u32 age_config; + u32 freq_base; + u32 turn_pt; + u32 vbin_turn_pt; + u32 core_sel; + u32 temp; u16 age_voffset_in; - u32 dc_config; u16 dc_voffset_in; u8 dvt_fixed; - u8 vco; - u8 chk_shift; - u32 core_sel; - u8 opp_count; - u32 int_st; - u8 sw_id; - u8 cpu_id; - u32 ctl0; - u32 temp; - u32 tzone_htemp; - u16 tzone_htemp_voffset; - u32 tzone_ltemp; - u16 tzone_ltemp_voffset; + u8 vmax; + u8 vmin; u16 bts; u16 mts; u16 bdes; @@ -528,9 +543,6 @@ struct svs_bank { u8 mtdes; u8 dcbdet; u8 dcmdet; - u32 turn_pt; - u32 vbin_turn_pt; - u8 type; }; static u32 percent(u32 numerator, u32 denominator) @@ -572,10 +584,11 @@ static u32 svs_opp_volt_to_bank_volt(u32 opp_u_volt, u32 svsb_volt_step, static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb) { + const struct svs_bank_pdata *bdata = &svsb->pdata; struct dev_pm_opp *opp; u32 i, opp_u_volt; - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < bdata->opp_count; i++) { opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, svsb->opp_dfreq[i], true); @@ -587,8 +600,8 @@ static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb) opp_u_volt = dev_pm_opp_get_voltage(opp); svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt, - svsb->volt_step, - svsb->volt_base); + bdata->volt_step, + bdata->volt_base); dev_pm_opp_put(opp); } @@ -598,6 +611,7 @@ static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb) static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) { int ret = -EPERM, tzone_temp = 0; + const struct svs_bank_pdata *bdata = &svsb->pdata; u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop; mutex_lock(&svsb->lock); @@ -606,15 +620,15 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) * 2-line bank updates its corresponding opp volts. * 1-line bank updates all opp volts. */ - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { opp_start = 0; opp_stop = svsb->turn_pt; - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { opp_start = svsb->turn_pt; - opp_stop = svsb->opp_count; + opp_stop = bdata->opp_count; } else { opp_start = 0; - opp_stop = svsb->opp_count; + opp_stop = bdata->opp_count; } /* Get thermal effect */ @@ -623,20 +637,20 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && svsb->temp < SVSB_TEMP_LOWER_BOUND)) { dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n", - svsb->tzone_name, ret, svsb->temp); + bdata->tzone_name, ret, svsb->temp); svsb->phase = SVSB_PHASE_ERROR; } - if (tzone_temp >= svsb->tzone_htemp) - temp_voffset += svsb->tzone_htemp_voffset; - else if (tzone_temp <= svsb->tzone_ltemp) - temp_voffset += svsb->tzone_ltemp_voffset; + if (tzone_temp >= bdata->tzone_htemp) + temp_voffset += bdata->tzone_htemp_voffset; + else if (tzone_temp <= bdata->tzone_ltemp) + temp_voffset += bdata->tzone_ltemp_voffset; /* 2-line bank update all opp volts when running mon mode */ - if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_TYPE_HIGH || - svsb->type == SVSB_TYPE_LOW)) { + if (svsb->phase == SVSB_PHASE_MON && (bdata->type == SVSB_TYPE_HIGH || + bdata->type == SVSB_TYPE_LOW)) { opp_start = 0; - opp_stop = svsb->opp_count; + opp_stop = bdata->opp_count; } } @@ -653,8 +667,8 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) case SVSB_PHASE_MON: svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin); opp_volt = svs_bank_volt_to_opp_volt(svsb_volt, - svsb->volt_step, - svsb->volt_base); + bdata->volt_step, + bdata->volt_base); break; default: dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase); @@ -816,7 +830,7 @@ static int svs_status_debug_show(struct seq_file *m, void *v) svsb->name, tzone_temp, svsb->vbin_turn_pt, svsb->turn_pt); - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < svsb->pdata.opp_count; i++) { opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, svsb->opp_dfreq[i], true); if (IS_ERR(opp)) { @@ -923,9 +937,10 @@ static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx) static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *svsb) { + const struct svs_bank_pdata *bdata = &svsb->pdata; u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0; - u32 middle_index = (svsb->opp_count / 2); + u32 middle_index = (bdata->opp_count / 2); if (svsb->phase == SVSB_PHASE_MON && svsb->volt_flags & SVSB_MON_VOLT_IGNORE) @@ -936,7 +951,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv /* Target is to set svsb->volt[] by algorithm */ if (turn_pt < middle_index) { - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { /* volt[0] ~ volt[turn_pt - 1] */ for (i = 0; i < turn_pt; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); @@ -945,12 +960,12 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); shift_byte++; } - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ - j = svsb->opp_count - 7; + j = bdata->opp_count - 7; svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); shift_byte++; - for (i = j; i < svsb->opp_count; i++) { + for (i = j; i < bdata->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); vop = (shift_byte < REG_BYTES) ? &vop30 : &vop74; @@ -967,7 +982,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv svsb->freq_pct[i]); } } else { - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ j = turn_pt - 7; svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); @@ -987,9 +1002,9 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv svsb->volt[0], svsb->volt[j], svsb->freq_pct[i]); - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { /* volt[turn_pt] ~ volt[opp_count - 1] */ - for (i = turn_pt; i < svsb->opp_count; i++) { + for (i = turn_pt; i < bdata->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); vop = (shift_byte < REG_BYTES) ? &vop30 : &vop74; @@ -999,12 +1014,12 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv } } - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { opp_start = 0; opp_stop = svsb->turn_pt; - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { opp_start = svsb->turn_pt; - opp_stop = svsb->opp_count; + opp_stop = bdata->opp_count; } for (i = opp_start; i < opp_stop; i++) @@ -1014,11 +1029,11 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv /* For voltage bin support */ if (svsb->opp_dfreq[0] > svsb->freq_base) { svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], - svsb->volt_step, - svsb->volt_base); + bdata->volt_step, + bdata->volt_base); /* Find voltage bin turn point */ - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < bdata->opp_count; i++) { if (svsb->opp_dfreq[i] <= svsb->freq_base) { svsb->vbin_turn_pt = i; break; @@ -1037,12 +1052,13 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp, struct svs_bank *sv static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *svsb) { + const struct svs_bank_pdata *bdata = &svsb->pdata; u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0; u32 b_sft, shift_byte = 0, turn_pt; - u32 middle_index = (svsb->opp_count / 2); + u32 middle_index = (bdata->opp_count / 2); - for (i = 0; i < svsb->opp_count; i++) { - if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) { + for (i = 0; i < bdata->opp_count; i++) { + if (svsb->opp_dfreq[i] <= bdata->turn_freq_base) { svsb->turn_pt = i; break; } @@ -1052,7 +1068,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank /* Target is to fill out freq_pct74 / freq_pct30 by algorithm */ if (turn_pt < middle_index) { - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { /* * If we don't handle this situation, * SVSB_TYPE_HIGH's FREQPCT74 / FREQPCT30 would keep "0" @@ -1069,15 +1085,15 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *freq_pct |= (svsb->freq_pct[i] << b_sft); shift_byte++; } - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { /* * freq_pct[turn_pt] + * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] */ freq_pct30 = svsb->freq_pct[turn_pt]; shift_byte++; - j = svsb->opp_count - 7; - for (i = j; i < svsb->opp_count; i++) { + j = bdata->opp_count - 7; + for (i = j; i < bdata->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); freq_pct = (shift_byte < REG_BYTES) ? &freq_pct30 : &freq_pct74; @@ -1086,7 +1102,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank } } } else { - if (svsb->type == SVSB_TYPE_HIGH) { + if (bdata->type == SVSB_TYPE_HIGH) { /* * freq_pct[0] + * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] @@ -1101,9 +1117,9 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank *freq_pct |= (svsb->freq_pct[i] << b_sft); shift_byte++; } - } else if (svsb->type == SVSB_TYPE_LOW) { + } else if (bdata->type == SVSB_TYPE_LOW) { /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ - for (i = turn_pt; i < svsb->opp_count; i++) { + for (i = turn_pt; i < bdata->opp_count; i++) { b_sft = BITS8 * (shift_byte % REG_BYTES); freq_pct = (shift_byte < REG_BYTES) ? &freq_pct30 : &freq_pct74; @@ -1119,6 +1135,7 @@ static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp, struct svs_bank static void svs_get_bank_volts_v2(struct svs_platform *svsp, struct svs_bank *svsb) { + const struct svs_bank_pdata *bdata = &svsb->pdata; u32 temp, i; temp = svs_readl_relaxed(svsp, VOP74); @@ -1146,17 +1163,17 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp, struct svs_bank *sv svsb->volt[14], svsb->freq_pct[15]); - for (i = 0; i < svsb->opp_count; i++) + for (i = 0; i < bdata->opp_count; i++) svsb->volt[i] += svsb->volt_od; /* For voltage bin support */ if (svsb->opp_dfreq[0] > svsb->freq_base) { svsb->volt[0] = svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], - svsb->volt_step, - svsb->volt_base); + bdata->volt_step, + bdata->volt_base); /* Find voltage bin turn point */ - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < bdata->opp_count; i++) { if (svsb->opp_dfreq[i] <= svsb->freq_base) { svsb->vbin_turn_pt = i; break; @@ -1196,6 +1213,7 @@ static void svs_set_bank_phase(struct svs_platform *svsp, enum svsb_phase target_phase) { struct svs_bank *svsb = &svsp->banks[bank_idx]; + const struct svs_bank_pdata *bdata = &svsb->pdata; u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs; svs_switch_bank(svsp, svsb); @@ -1204,7 +1222,7 @@ static void svs_set_bank_phase(struct svs_platform *svsp, FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes); svs_writel_relaxed(svsp, des_char, DESCHAR); - temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, svsb->vco) | + temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, bdata->vco) | FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) | FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed); svs_writel_relaxed(svsp, temp_char, TEMPCHAR); @@ -1213,11 +1231,11 @@ static void svs_set_bank_phase(struct svs_platform *svsp, FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet); svs_writel_relaxed(svsp, det_char, DETCHAR); - svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG); - svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG); + svs_writel_relaxed(svsp, bdata->dc_config, DCCONFIG); + svs_writel_relaxed(svsp, bdata->age_config, AGECONFIG); svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG); - svsb->set_freq_pct(svsp, svsb); + bdata->set_freq_pct(svsp, svsb); limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) | FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) | @@ -1227,13 +1245,13 @@ static void svs_set_bank_phase(struct svs_platform *svsp, svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW); svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG); - svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT); - svs_writel_relaxed(svsp, svsb->ctl0, CTL0); + svs_writel_relaxed(svsp, bdata->chk_shift, CHKSHIFT); + svs_writel_relaxed(svsp, bdata->ctl0, CTL0); svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); switch (target_phase) { case SVSB_PHASE_INIT01: - svs_writel_relaxed(svsp, svsb->vboot, VBOOT); + svs_writel_relaxed(svsp, bdata->vboot, VBOOT); svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN); svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN); break; @@ -1324,6 +1342,7 @@ static inline void svs_init02_isr_handler(struct svs_platform *svsp, unsigned short bank_idx) { struct svs_bank *svsb = &svsp->banks[bank_idx]; + const struct svs_bank_pdata *bdata = &svsb->pdata; dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", __func__, svs_readl_relaxed(svsp, VOP74), @@ -1333,7 +1352,7 @@ static inline void svs_init02_isr_handler(struct svs_platform *svsp, svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_INIT02); svsb->phase = SVSB_PHASE_INIT02; - svsb->get_volts(svsp, svsb); + bdata->get_volts(svsp, svsb); svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS); @@ -1343,11 +1362,12 @@ static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp, unsigned short bank_idx) { struct svs_bank *svsb = &svsp->banks[bank_idx]; + const struct svs_bank_pdata *bdata = &svsb->pdata; svs_save_bank_register_data(svsp, bank_idx, SVSB_PHASE_MON); svsb->phase = SVSB_PHASE_MON; - svsb->get_volts(svsp, svsb); + bdata->get_volts(svsp, svsb); svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS); @@ -1356,18 +1376,20 @@ static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp, static irqreturn_t svs_isr(int irq, void *data) { struct svs_platform *svsp = data; + const struct svs_bank_pdata *bdata; struct svs_bank *svsb = NULL; unsigned long flags; u32 idx, int_sts, svs_en; for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); spin_lock_irqsave(&svs_lock, flags); /* Find out which svs bank fires interrupt */ - if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) { + if (bdata->int_st & svs_readl_relaxed(svsp, INTST)) { spin_unlock_irqrestore(&svs_lock, flags); continue; } @@ -1412,6 +1434,7 @@ static bool svs_mode_available(struct svs_platform *svsp, u8 mode) static int svs_init01(struct svs_platform *svsp) { + const struct svs_bank_pdata *bdata; struct svs_bank *svsb; unsigned long flags, time_left; bool search_done; @@ -1427,6 +1450,7 @@ static int svs_init01(struct svs_platform *svsp) /* Svs bank init01 preparation - power enable */ for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; if (!(svsb->mode_support & SVSB_MODE_INIT01)) continue; @@ -1434,7 +1458,7 @@ static int svs_init01(struct svs_platform *svsp) ret = regulator_enable(svsb->buck); if (ret) { dev_err(svsb->dev, "%s enable fail: %d\n", - svsb->buck_name, ret); + bdata->buck_name, ret); goto svs_init01_resume_cpuidle; } @@ -1464,6 +1488,7 @@ static int svs_init01(struct svs_platform *svsp) */ for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; if (!(svsb->mode_support & SVSB_MODE_INIT01)) continue; @@ -1473,11 +1498,11 @@ static int svs_init01(struct svs_platform *svsp) * fix to that freq until svs_init01 is done. */ search_done = false; - opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, - svsb->volt_step, - svsb->volt_base); + opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot, + bdata->volt_step, + bdata->volt_base); - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < bdata->opp_count; i++) { opp_freq = svsb->opp_dfreq[i]; if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) { ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, @@ -1509,13 +1534,14 @@ static int svs_init01(struct svs_platform *svsp) /* Svs bank init01 begins */ for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; if (!(svsb->mode_support & SVSB_MODE_INIT01)) continue; - opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, - svsb->volt_step, - svsb->volt_base); + opp_vboot = svs_bank_volt_to_opp_volt(bdata->vboot, + bdata->volt_step, + bdata->volt_base); buck_volt = regulator_get_voltage(svsb->buck); if (buck_volt != opp_vboot) { @@ -1542,11 +1568,12 @@ static int svs_init01(struct svs_platform *svsp) svs_init01_finish: for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; if (!(svsb->mode_support & SVSB_MODE_INIT01)) continue; - for (i = 0; i < svsb->opp_count; i++) { + for (i = 0; i < bdata->opp_count; i++) { r = dev_pm_opp_enable(svsb->opp_dev, svsb->opp_dfreq[i]); if (r) @@ -1572,7 +1599,7 @@ static int svs_init01(struct svs_platform *svsp) r = regulator_disable(svsb->buck); if (r) dev_err(svsb->dev, "%s disable fail: %d\n", - svsb->buck_name, r); + bdata->buck_name, r); } svs_init01_resume_cpuidle: @@ -1583,6 +1610,7 @@ static int svs_init01(struct svs_platform *svsp) static int svs_init02(struct svs_platform *svsp) { + const struct svs_bank_pdata *bdata; struct svs_bank *svsb; unsigned long flags, time_left; int ret; @@ -1618,11 +1646,12 @@ static int svs_init02(struct svs_platform *svsp) */ for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; if (!(svsb->mode_support & SVSB_MODE_INIT02)) continue; - if (svsb->type == SVSB_TYPE_HIGH || svsb->type == SVSB_TYPE_LOW) { + if (bdata->type == SVSB_TYPE_HIGH || bdata->type == SVSB_TYPE_LOW) { if (svs_sync_bank_volts_from_opp(svsb)) { dev_err(svsb->dev, "sync volt fail\n"); ret = -EPERM; @@ -1680,12 +1709,12 @@ static int svs_start(struct svs_platform *svsp) static int svs_suspend(struct device *dev) { struct svs_platform *svsp = dev_get_drvdata(dev); - struct svs_bank *svsb; int ret; u32 idx; for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; + struct svs_bank *svsb = &svsp->banks[idx]; + svs_bank_disable_and_restore_default_volts(svsp, svsb); } @@ -1736,6 +1765,7 @@ static int svs_resume(struct device *dev) static int svs_bank_resource_setup(struct svs_platform *svsp) { + const struct svs_bank_pdata *bdata; struct svs_bank *svsb; struct dev_pm_opp *opp; unsigned long freq; @@ -1746,8 +1776,9 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; - if (svsb->sw_id >= SVSB_SWID_MAX || svsb->type >= SVSB_TYPE_MAX) { + if (bdata->sw_id >= SVSB_SWID_MAX || bdata->type >= SVSB_TYPE_MAX) { dev_err(svsb->dev, "unknown bank sw_id or type\n"); return -EINVAL; } @@ -1757,8 +1788,8 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) return -ENOMEM; svsb->name = devm_kasprintf(svsp->dev, GFP_KERNEL, "%s%s", - svs_swid_names[svsb->sw_id], - svs_type_names[svsb->type]); + svs_swid_names[bdata->sw_id], + svs_type_names[bdata->type]); if (!svsb->name) return -ENOMEM; @@ -1779,10 +1810,10 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) if (svsb->mode_support & SVSB_MODE_INIT01) { svsb->buck = devm_regulator_get_optional(svsb->opp_dev, - svsb->buck_name); + bdata->buck_name); if (IS_ERR(svsb->buck)) { dev_err(svsb->dev, "cannot get \"%s-supply\"\n", - svsb->buck_name); + bdata->buck_name); return PTR_ERR(svsb->buck); } } @@ -1797,14 +1828,14 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) } count = dev_pm_opp_get_opp_count(svsb->opp_dev); - if (svsb->opp_count != count) { + if (bdata->opp_count != count) { dev_err(svsb->dev, "opp_count not \"%u\" but get \"%d\"?\n", - svsb->opp_count, count); + bdata->opp_count, count); return count; } - for (i = 0, freq = ULONG_MAX; i < svsb->opp_count; i++, freq--) { + for (i = 0, freq = ULONG_MAX; i < bdata->opp_count; i++, freq--) { opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); if (IS_ERR(opp)) { dev_err(svsb->dev, "cannot find freq = %ld\n", @@ -1901,7 +1932,8 @@ static bool svs_common_parse_efuse(struct svs_platform *svsp, for (i = 0; i < svsp->bank_max; i++) { struct svs_bank *svsb = &svsp->banks[i]; - const struct svs_fusemap *dfmap = svsb->dev_fuse_map; + const struct svs_bank_pdata *bdata = &svsb->pdata; + const struct svs_fusemap *dfmap = bdata->dev_fuse_map; if (vmin == 1) svsb->vmin = 0x1e; @@ -1927,11 +1959,11 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, const struct svs_platform_data *pdata) { struct svs_bank *svsb; + const struct svs_bank_pdata *bdata; int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0; int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t; int o_slope, o_slope_sign, ts_id; u32 idx, i, ft_pgm, mts, temp0, temp1, temp2; - int ret; for (i = 0; i < svsp->efuse_max; i++) if (svsp->efuse[i]) @@ -1948,7 +1980,8 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; - const struct svs_fusemap *dfmap = svsb->dev_fuse_map; + bdata = &svsb->pdata; + const struct svs_fusemap *dfmap = bdata->dev_fuse_map; if (ft_pgm <= 1) svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; @@ -1959,7 +1992,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, svsb->dcbdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCBDET], 8); svsb->dcmdet = svs_get_fuse_val(svsp->efuse, &dfmap[BDEV_DCMDET], 8); - switch (svsb->sw_id) { + switch (bdata->sw_id) { case SVSB_SWID_CPU_LITTLE: case SVSB_SWID_CCI: if (ft_pgm <= 3) @@ -2044,9 +2077,10 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; + bdata = &svsb->pdata; svsb->mts = mts; - switch (svsb->sw_id) { + switch (bdata->sw_id) { case SVSB_SWID_CPU_LITTLE: tb_roomt = x_roomt[3]; break; @@ -2060,7 +2094,7 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp, tb_roomt = x_roomt[1]; break; default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); goto remove_mt8183_svsb_mon_mode; } @@ -2147,24 +2181,24 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) for (idx = 0; idx < svsp->bank_max; idx++) { struct svs_bank *svsb = &svsp->banks[idx]; + const struct svs_bank_pdata *bdata = &svsb->pdata; - switch (svsb->sw_id) { + switch (bdata->sw_id) { case SVSB_SWID_CPU_LITTLE: case SVSB_SWID_CPU_BIG: - svsb->opp_dev = get_cpu_device(svsb->cpu_id); + svsb->opp_dev = get_cpu_device(bdata->cpu_id); break; case SVSB_SWID_CCI: svsb->opp_dev = svs_add_device_link(svsp, "cci"); break; case SVSB_SWID_GPU: - if (svsb->type == SVSB_TYPE_LOW) + if (bdata->type == SVSB_TYPE_LOW) svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); else svsb->opp_dev = svs_add_device_link(svsp, "gpu"); break; - break; default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); return -EINVAL; } @@ -2180,7 +2214,6 @@ static int svs_mt8192_platform_probe(struct svs_platform *svsp) static int svs_mt8183_platform_probe(struct svs_platform *svsp) { struct device *dev; - struct svs_bank *svsb; u32 idx; dev = svs_add_device_link(svsp, "thermal-sensor"); @@ -2189,12 +2222,13 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) "failed to get thermal device\n"); for (idx = 0; idx < svsp->bank_max; idx++) { - svsb = &svsp->banks[idx]; + struct svs_bank *svsb = &svsp->banks[idx]; + const struct svs_bank_pdata *bdata = &svsb->pdata; - switch (svsb->sw_id) { + switch (bdata->sw_id) { case SVSB_SWID_CPU_LITTLE: case SVSB_SWID_CPU_BIG: - svsb->opp_dev = get_cpu_device(svsb->cpu_id); + svsb->opp_dev = get_cpu_device(bdata->cpu_id); break; case SVSB_SWID_CCI: svsb->opp_dev = svs_add_device_link(svsp, "cci"); @@ -2203,7 +2237,7 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) svsb->opp_dev = svs_add_device_link(svsp, "gpu"); break; default: - dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + dev_err(svsb->dev, "unknown sw_id: %u\n", bdata->sw_id); return -EINVAL; } @@ -2218,463 +2252,486 @@ static int svs_mt8183_platform_probe(struct svs_platform *svsp) static struct svs_bank svs_mt8195_banks[] = { { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_LOW, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, - .mode_support = SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 640000000, - .turn_freq_base = 640000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x38, - .vmin = 0x14, - .age_config = 0x555555, - .dc_config = 0x1, - .dvt_fixed = 0x1, - .vco = 0x18, - .chk_shift = 0x87, - .core_sel = 0x0fff0100, - .int_st = BIT(0), - .ctl0 = 0x00540003, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 10, 16 }, { 10, 24 }, { 10, 0 }, { 8, 0 }, { 8, 8 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .int_st = BIT(0), + .ctl0 = 0x00540003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 10, 16 }, { 10, 24 }, { 10, 0 }, { 8, 0 }, { 8, 8 } + } + }, + .mode_support = SVSB_MODE_INIT02, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .freq_base = 640000000, + .core_sel = 0x0fff0100, + .dvt_fixed = 0x1, + .vmax = 0x38, + .vmin = 0x14, }, { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_HIGH, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .tzone_name = "gpu1", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 880000000, - .turn_freq_base = 640000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x38, - .vmin = 0x14, - .age_config = 0x555555, - .dc_config = 0x1, - .dvt_fixed = 0x6, - .vco = 0x18, - .chk_shift = 0x87, - .core_sel = 0x0fff0101, - .int_st = BIT(1), - .ctl0 = 0x00540003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 0, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 7, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 9, 16 }, { 9, 24 }, { 9, 0 }, { 8, 0 }, { 8, 8 } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 9, 16 }, { 9, 24 }, { 9, 0 }, { 8, 0 }, { 8, 8 } + }, }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 880000000, + .core_sel = 0x0fff0101, + .dvt_fixed = 0x6, + .vmax = 0x38, + .vmin = 0x14, }, }; static struct svs_bank svs_mt8192_banks[] = { { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_LOW, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .tzone_name = "gpu1", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, - .mode_support = SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 688000000, - .turn_freq_base = 688000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x60, - .vmin = 0x1a, - .age_config = 0x555555, - .dc_config = 0x1, - .dvt_fixed = 0x1, - .vco = 0x18, - .chk_shift = 0x87, - .core_sel = 0x0fff0100, - .int_st = BIT(0), - .ctl0 = 0x00540003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 0, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 7, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 10, 16 }, { 10, 24 }, { 10, 0 }, { 17, 0 }, { 17, 8 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 688000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .int_st = BIT(0), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 10, 16 }, { 10, 24 }, { 10, 0 }, { 17, 0 }, { 17, 8 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support = SVSB_MODE_INIT02, + .freq_base = 688000000, + .core_sel = 0x0fff0100, + .dvt_fixed = 0x1, + .vmax = 0x60, + .vmin = 0x1a, }, { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_HIGH, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .tzone_name = "gpu1", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 902000000, - .turn_freq_base = 688000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x60, - .vmin = 0x1a, - .age_config = 0x555555, - .dc_config = 0x1, - .dvt_fixed = 0x6, - .vco = 0x18, - .chk_shift = 0x87, - .core_sel = 0x0fff0101, - .int_st = BIT(1), - .ctl0 = 0x00540003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 0, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 7, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 9, 16 }, { 9, 24 }, { 17, 0 }, { 17, 16 }, { 17, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 688000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 9, 16 }, { 9, 24 }, { 17, 0 }, { 17, 16 }, { 17, 24 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 902000000, + .core_sel = 0x0fff0101, + .dvt_fixed = 0x6, + .vmax = 0x60, + .vmin = 0x1a, }, }; static struct svs_bank svs_mt8188_banks[] = { { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_LOW, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, - .mode_support = SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 640000000, - .turn_freq_base = 640000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x38, - .vmin = 0x1c, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x1, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0000, - .int_st = BIT(0), - .ctl0 = 0x00100003, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(0), + .ctl0 = 0x00100003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support = SVSB_MODE_INIT02, + .freq_base = 640000000, + .core_sel = 0x0fff0000, + .dvt_fixed = 0x1, + .vmax = 0x38, + .vmin = 0x1c, }, { - .sw_id = SVSB_SWID_GPU, - .type = SVSB_TYPE_HIGH, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .tzone_name = "gpu1", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 880000000, - .turn_freq_base = 640000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x38, - .vmin = 0x1c, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x4, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0001, - .int_st = BIT(1), - .ctl0 = 0x00100003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 0, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 7, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .type = SVSB_TYPE_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 640000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(1), + .ctl0 = 0x00100003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 880000000, + .core_sel = 0x0fff0001, + .dvt_fixed = 0x4, + .vmax = 0x38, + .vmin = 0x1c, }, }; static struct svs_bank svs_mt8186_banks[] = { { - .sw_id = SVSB_SWID_CPU_BIG, - .type = SVSB_TYPE_LOW, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .cpu_id = 6, - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, - .mode_support = SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 1670000000, - .turn_freq_base = 1670000000, - .volt_step = 6250, - .volt_base = 400000, - .volt_od = 4, - .vmax = 0x59, - .vmin = 0x20, - .age_config = 0x1, - .dc_config = 0x1, - .dvt_fixed = 0x3, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0100, - .int_st = BIT(0), - .ctl0 = 0x00540003, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 3, 16 }, { 3, 24 }, { 3, 0 }, { 14, 16 }, { 14, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CPU_BIG, + .type = SVSB_TYPE_LOW, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .cpu_id = 6, + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 1670000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x1, + .dc_config = 0x1, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(0), + .ctl0 = 0x00540003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 3, 16 }, { 3, 24 }, { 3, 0 }, { 14, 16 }, { 14, 24 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, + .volt_od = 4, + .mode_support = SVSB_MODE_INIT02, + .freq_base = 1670000000, + .core_sel = 0x0fff0100, + .dvt_fixed = 0x3, + .vmax = 0x59, + .vmin = 0x20, }, { - .sw_id = SVSB_SWID_CPU_BIG, - .type = SVSB_TYPE_HIGH, - .set_freq_pct = svs_set_bank_freq_pct_v3, - .get_volts = svs_get_bank_volts_v3, - .cpu_id = 6, - .tzone_name = "cpu_big0", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 2050000000, - .turn_freq_base = 1670000000, - .volt_step = 6250, - .volt_base = 400000, - .volt_od = 4, - .vmax = 0x73, - .vmin = 0x20, - .age_config = 0x1, - .dc_config = 0x1, - .dvt_fixed = 0x6, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0101, - .int_st = BIT(1), - .ctl0 = 0x00540003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 8, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 8, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 2, 16 }, { 2, 24 }, { 2, 0 }, { 13, 0 }, { 13, 8 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CPU_BIG, + .type = SVSB_TYPE_HIGH, + .set_freq_pct = svs_set_bank_freq_pct_v3, + .get_volts = svs_get_bank_volts_v3, + .cpu_id = 6, + .tzone_name = "cpu-big", + .opp_count = MAX_OPP_ENTRIES, + .turn_freq_base = 1670000000, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x1, + .dc_config = 0x1, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 2, 16 }, { 2, 24 }, { 2, 0 }, { 13, 0 }, { 13, 8 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .volt_od = 4, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 2050000000, + .core_sel = 0x0fff0101, + .dvt_fixed = 0x6, + .vmax = 0x73, + .vmin = 0x20, }, { - .sw_id = SVSB_SWID_CPU_LITTLE, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .cpu_id = 0, - .tzone_name = "cpu_zone0", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 2000000000, - .volt_step = 6250, - .volt_base = 400000, - .volt_od = 3, - .vmax = 0x65, - .vmin = 0x20, - .age_config = 0x1, - .dc_config = 0x1, - .dvt_fixed = 0x6, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0102, - .int_st = BIT(2), - .ctl0 = 0x3210000f, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 8, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 8, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CPU_LITTLE, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .cpu_id = 0, + .tzone_name = "cpu-little", + .opp_count = MAX_OPP_ENTRIES, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x1, + .dc_config = 0x1, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(2), + .ctl0 = 0x3210000f, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 16 }, { 4, 24 }, { 4, 0 }, { 14, 0 }, { 14, 8 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .volt_od = 3, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 2000000000, + .core_sel = 0x0fff0102, + .dvt_fixed = 0x6, + .vmax = 0x65, + .vmin = 0x20, }, { - .sw_id = SVSB_SWID_CCI, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .tzone_name = "cpu_zone0", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 1400000000, - .volt_step = 6250, - .volt_base = 400000, - .volt_od = 3, - .vmax = 0x65, - .vmin = 0x20, - .age_config = 0x1, - .dc_config = 0x1, - .dvt_fixed = 0x6, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0103, - .int_st = BIT(3), - .ctl0 = 0x3210000f, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 8, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 8, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CCI, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .tzone_name = "cci", + .opp_count = MAX_OPP_ENTRIES, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x1, + .dc_config = 0x1, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(3), + .ctl0 = 0x3210000f, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 8, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 5, 16 }, { 5, 24 }, { 5, 0 }, { 15, 16 }, { 15, 24 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .volt_od = 3, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 1400000000, + .core_sel = 0x0fff0103, + .dvt_fixed = 0x6, + .vmax = 0x65, + .vmin = 0x20, }, { - .sw_id = SVSB_SWID_GPU, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .tzone_name = "mfg", - .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | - SVSB_MON_VOLT_IGNORE, - .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 850000000, - .volt_step = 6250, - .volt_base = 400000, - .vmax = 0x58, - .vmin = 0x20, - .age_config = 0x555555, - .dc_config = 0x1, - .dvt_fixed = 0x4, - .vco = 0x10, - .chk_shift = 0x87, - .core_sel = 0x0fff0104, - .int_st = BIT(4), - .ctl0 = 0x00100003, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 8, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 7, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 6, 16 }, { 6, 24 }, { 6, 0 }, { 15, 8 }, { 15, 0 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .volt_step = 6250, + .volt_base = 400000, + .age_config = 0x555555, + .dc_config = 0x1, + .vco = 0x10, + .chk_shift = 0x87, + .int_st = BIT(4), + .ctl0 = 0x00100003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 8, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 6, 16 }, { 6, 24 }, { 6, 0 }, { 15, 8 }, { 15, 0 } + } + }, + .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT | SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 850000000, + .core_sel = 0x0fff0104, + .dvt_fixed = 0x4, + .vmax = 0x58, + .vmin = 0x20, }, }; static struct svs_bank svs_mt8183_banks[] = { { - .sw_id = SVSB_SWID_CPU_LITTLE, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .cpu_id = 0, - .buck_name = "proc", - .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 1989000000, - .vboot = 0x30, - .volt_step = 6250, - .volt_base = 500000, - .vmax = 0x64, - .vmin = 0x18, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x7, - .vco = 0x10, - .chk_shift = 0x77, - .core_sel = 0x8fff0000, - .int_st = BIT(0), - .ctl0 = 0x00010001, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 16, 0 }, { 16, 8 }, { 17, 16 }, { 16, 16 }, { 16, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CPU_LITTLE, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .cpu_id = 0, + .buck_name = "proc", + .opp_count = MAX_OPP_ENTRIES, + .vboot = 0x30, + .volt_step = 6250, + .volt_base = 500000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x77, + .int_st = BIT(0), + .ctl0 = 0x00010001, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 16, 0 }, { 16, 8 }, { 17, 16 }, { 16, 16 }, { 16, 24 } + } + }, + .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, + .freq_base = 1989000000, + .core_sel = 0x8fff0000, + .dvt_fixed = 0x7, + .vmax = 0x64, + .vmin = 0x18, + }, { - .sw_id = SVSB_SWID_CPU_BIG, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .cpu_id = 4, - .buck_name = "proc", - .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 1989000000, - .vboot = 0x30, - .volt_step = 6250, - .volt_base = 500000, - .vmax = 0x58, - .vmin = 0x10, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x7, - .vco = 0x10, - .chk_shift = 0x77, - .core_sel = 0x8fff0001, - .int_st = BIT(1), - .ctl0 = 0x00000001, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 18, 0 }, { 18, 8 }, { 17, 0 }, { 18, 16 }, { 18, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CPU_BIG, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .cpu_id = 4, + .buck_name = "proc", + .opp_count = MAX_OPP_ENTRIES, + .vboot = 0x30, + .volt_step = 6250, + .volt_base = 500000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x77, + .int_st = BIT(1), + .ctl0 = 0x00000001, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 18, 0 }, { 18, 8 }, { 17, 0 }, { 18, 16 }, { 18, 24 } + } + }, + .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, + .freq_base = 1989000000, + .core_sel = 0x8fff0001, + .dvt_fixed = 0x7, + .vmax = 0x58, + .vmin = 0x10, + }, { - .sw_id = SVSB_SWID_CCI, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .buck_name = "proc", - .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 1196000000, - .vboot = 0x30, - .volt_step = 6250, - .volt_base = 500000, - .vmax = 0x64, - .vmin = 0x18, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x7, - .vco = 0x10, - .chk_shift = 0x77, - .core_sel = 0x8fff0002, - .int_st = BIT(2), - .ctl0 = 0x00100003, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 4, 0 }, { 4, 8 }, { 5, 16 }, { 4, 16 }, { 4, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_CCI, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .buck_name = "proc", + .opp_count = MAX_OPP_ENTRIES, + .vboot = 0x30, + .volt_step = 6250, + .volt_base = 500000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x77, + .int_st = BIT(2), + .ctl0 = 0x00100003, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 4, 0 }, { 4, 8 }, { 5, 16 }, { 4, 16 }, { 4, 24 } + } + }, + .volt_flags = SVSB_INIT01_VOLT_INC_ONLY, + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02, + .freq_base = 1196000000, + .core_sel = 0x8fff0002, + .dvt_fixed = 0x7, + .vmax = 0x64, + .vmin = 0x18, }, { - .sw_id = SVSB_SWID_GPU, - .set_freq_pct = svs_set_bank_freq_pct_v2, - .get_volts = svs_get_bank_volts_v2, - .buck_name = "mali", - .tzone_name = "tzts2", - .volt_flags = SVSB_INIT01_PD_REQ | - SVSB_INIT01_VOLT_INC_ONLY, - .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | - SVSB_MODE_MON, - .opp_count = MAX_OPP_ENTRIES, - .freq_base = 900000000, - .vboot = 0x30, - .volt_step = 6250, - .volt_base = 500000, - .vmax = 0x40, - .vmin = 0x14, - .age_config = 0x555555, - .dc_config = 0x555555, - .dvt_fixed = 0x3, - .vco = 0x10, - .chk_shift = 0x77, - .core_sel = 0x8fff0003, - .int_st = BIT(3), - .ctl0 = 0x00050001, - .tzone_htemp = 85000, - .tzone_htemp_voffset = 0, - .tzone_ltemp = 25000, - .tzone_ltemp_voffset = 3, - .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { - { 6, 0 }, { 6, 8 }, { 5, 0 }, { 6, 16 }, { 6, 24 } - } + .pdata = (const struct svs_bank_pdata) { + .sw_id = SVSB_SWID_GPU, + .set_freq_pct = svs_set_bank_freq_pct_v2, + .get_volts = svs_get_bank_volts_v2, + .buck_name = "mali", + .tzone_name = "gpu", + .opp_count = MAX_OPP_ENTRIES, + .vboot = 0x30, + .volt_step = 6250, + .volt_base = 500000, + .age_config = 0x555555, + .dc_config = 0x555555, + .vco = 0x10, + .chk_shift = 0x77, + .int_st = BIT(3), + .ctl0 = 0x00050001, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 3, + .dev_fuse_map = (const struct svs_fusemap[BDEV_MAX]) { + { 6, 0 }, { 6, 8 }, { 5, 0 }, { 6, 16 }, { 6, 24 } + } + }, + .volt_flags = SVSB_INIT01_PD_REQ | SVSB_INIT01_VOLT_INC_ONLY, + .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 | SVSB_MODE_MON, + .freq_base = 900000000, + .core_sel = 0x8fff0003, + .dvt_fixed = 0x3, + .vmax = 0x40, + .vmin = 0x14, }, }; @@ -2874,5 +2931,6 @@ static struct platform_driver svs_driver = { module_platform_driver(svs_driver); MODULE_AUTHOR("Roger Lu "); +MODULE_AUTHOR("AngeloGioacchino Del Regno "); MODULE_DESCRIPTION("MediaTek SVS driver"); MODULE_LICENSE("GPL"); From patchwork Tue Nov 21 11:56:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167693 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565376vqb; Tue, 21 Nov 2023 03:59:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IHf/KT4jv7w0SsOH5t705OWmC39HLLaFDgDvj/M/XKSCAMO7WJcr8t0HBmbqAJoChf2EhlX X-Received: by 2002:a05:6a20:c584:b0:188:67d:e6f6 with SMTP id gn4-20020a056a20c58400b00188067de6f6mr6561727pzb.55.1700567998095; Tue, 21 Nov 2023 03:59:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700567998; cv=none; d=google.com; s=arc-20160816; b=piN6kmTVYsJf73l9051e6l/O2ET5e723YXGxJdnRxbwOrRTLi64IlgRAD41BZIdETR 5lIrz9h4/N0iL+ewpQftCmX20nVbPu9B8Ma8BEpQqPBQ0MGZ43EDLEb2wSuFxcim+7o1 roWCpQwg1HIDKMTxfhCFLLzfCRO6rnicx/NO3VAkGnd5F8my1SPdTi9mwwIhTMH/Gl3X CCGjIPpYwqvQzPknup/0TUJ6vpBiEw8tHkOIXbgOaqrKbL15wUubpRZOXVJ9Lr1Yb3AE Af4j4EjMIrJ6n3NvYTxcwE8H15Zl8y1fiDfPlP57U2TRT92LrHNdkF3tc1XVLV9sB6I3 XTZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g/wsfGTD4qIPzV9aYVLPlzsDTVh1NFbKfRsNkAhi+fc=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=sUz4c49LRzlM1LNO87m7jTww+wQVygYzEpGoOSVU2IBQxGUIbz2BSZYsc9kgE3k3S7 9TFC/yF4QA0ADVErrr16M3L6mI7HHFD7IpBeQfac4Yvl88gxPgWzItokYUWyA4KGosQu a+RfbecV4uCm0EbGg4PvmffJ13yWtfVSsdXKym/yq4AfgvGnnZ+gnsK+t1p9yUM4lClh tyJW61mhkwoRSLL1I8NcQBw8C0BQ5Nj5dHNmjuadXUn8OnPYA11N17lz9rHht6oDWAMp 5IQlLBOnEYfdVHo/fpaXvO7wK9KSzOfUpIyWzHoX4Jz9nQTd37woaaT1hFE7SMcazJvH 0pLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=aPvhaS6w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id z9-20020a17090a540900b0028511909e15si6482132pjh.136.2023.11.21.03.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 03:59:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=aPvhaS6w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D2CF081068D2; Tue, 21 Nov 2023 03:58:02 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234628AbjKUL5z (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234630AbjKUL44 (ORCPT ); Tue, 21 Nov 2023 06:56:56 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9467818A; Tue, 21 Nov 2023 03:56:52 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A1D1A6607314; Tue, 21 Nov 2023 11:56:50 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567811; bh=7Is9gmN9hkuGxy+sJrNkxtzwuNgilsJCxJ9IKhqUks4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aPvhaS6wJe5G/gRUKtyQrhc2GTcWtRZlIA8mgqEXXZAPvvjDoIc3ZNlC0hBzCAfyY EMu18y6aUc5PkXxV4VICK/5rK2tZ7PadPSbOKoVNSHNseLAqFSSA8zPAAPiEbakDMt oJDkksK8RBdTQkcbCgEwElmtV2Xi50QCTTrW8Tu4K9en4SREPxctigi8YdaqrxDXNL o4pbEVdlGobEK+6OvAsgNeDpu68ut7OWoesinj1OWUZIgo28sNLwoKTWQZuIBTi389 kZtsUM4qesLgaoaucYPiW7WoHXOgy9IfgT1/52r4PCIRkCIKyFJukPo///OzSRdEVk 0KuI5pfpVSSYQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 19/20] arm64: dts: mediatek: mt8192: Add Smart Voltage Scaling node Date: Tue, 21 Nov 2023 12:56:23 +0100 Message-ID: <20231121115624.56855-20-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:58:03 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174789423323832 X-GMAIL-MSGID: 1783174789423323832 Add the MediaTek SVS node: this will lower the voltage of various components of the SoC based on chip quality (read from fuses) in order to save power and generate less heat. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 238f6eb25832..6dd32dbfb832 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -809,6 +809,18 @@ lvts_ap: thermal-sensor@1100b000 { #thermal-sensor-cells = <1>; }; + svs: svs@1100bc00 { + compatible = "mediatek,mt8192-svs"; + reg = <0 0x1100bc00 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, <&lvts_e_data1>; + nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; + resets = <&infracfg MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST>; + reset-names = "svs_rst"; + }; + pwm0: pwm@1100e000 { compatible = "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; From patchwork Tue Nov 21 11:56:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 167694 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2b07:b0:403:3b70:6f57 with SMTP id io7csp565463vqb; Tue, 21 Nov 2023 04:00:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IHFwuH/qIvAgBwjpTU1PpCGN7UdEuhfimMOw8E56OeNUH7ClbA8CYAhcrn4bwVr67vvlcdj X-Received: by 2002:a17:902:6a87:b0:1cc:4a23:c5fc with SMTP id n7-20020a1709026a8700b001cc4a23c5fcmr8003421plk.2.1700568004075; Tue, 21 Nov 2023 04:00:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700568004; cv=none; d=google.com; s=arc-20160816; b=xgDwhZROHOgJNpmOXEVqNWj1qm4UXE3ska6TWklRMB2qPzMeqtUVkQoQ+AZA9od5cU ZR+BHkv86ZjTbjX8TdmaI/6oZPi/HffrbANUdLcu66a2WJIPOFSvX7jqxo2cc/zPSDIk pwLaNmpEaZ8wucOWlkOfXGRVOZloxstxC9ZcCBwvOcO8uOELOoocobY+ceBf8yq4VZB6 AZN4YXkP2F2A6NhM1u3kbD2OMxVETVP9cSy4wVKlY88JoumKiADnG5J0Ls3FI6vxRRyn kxK0dzlUQFX7xmmrW18fxPxHoaf3/t7JdJyLEv3rpL+vQ4Hg41+QvTqRqO/RYzLJWGXn iHAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2nSvjwhp8KEX+f10c8PjMOZ1/nuFqQp7c5iuH1zb1GM=; fh=m5p6pcg3y47Sg5VKYWXj0f0nOzgFq4l5+GGYwGce+t4=; b=ewR/mjvOLjTRcjI8QNoIB1GXRNJizQI3pRPNcacm+Q17xuxfbZbI4o6Q8yT4cWrdzl w63oAJgUZuABkN/EVS/Z7j0XuCfPXb0bRQPnCFZd11UUDIKtbpx5jAwnbWxQzcy5GHHA ZEkA1plz5xgjDpAKj0/kcMjN92fUlWk2CFChq/LOH3SY1OIujEuQPONGeL4n54Zpvweg PI8vSiBIEiAUKc4PXSexFMoxlwdXcETVaLWA5SDR3lN68Eeqs+0+4cQ/+fhCaKSDX2Uc zWBvuzNMV8F6psi9DWPYzQyKJv7Ad4D5ouVNCaasL+XeKbNz6i1lDGmuowBLGtoOs043 Tz1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=AzcJTJtc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id j11-20020a170902da8b00b001cf747e89c1si195430plx.145.2023.11.21.04.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 04:00:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=AzcJTJtc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D9F6A81121CA; Tue, 21 Nov 2023 03:58:12 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234661AbjKUL56 (ORCPT + 99 others); Tue, 21 Nov 2023 06:57:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234646AbjKUL45 (ORCPT ); Tue, 21 Nov 2023 06:56:57 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B05D7BA; Tue, 21 Nov 2023 03:56:53 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A94466607286; Tue, 21 Nov 2023 11:56:51 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567812; bh=6uV/aa1GXqZk9w0ZoiU/aw6OTSIwDj0KZLX0pQNrucc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AzcJTJtcns2hZVQxPv//hCU1Ktg1kQPx1j+4phznifkdcfkG6kMM+QLmJDK1YlFxP RSq201iTG5sE8ggnON3rAC6anpXaj8FKY2VYWKYwQEr789kooV+0FamtKG9wfY41F9 NVni+Ire/E2C1Xaw60EzwIdhA4cABDHzsvUN2Dq85o+edij3aud1JL4lXXJTGAVVAS 3er6SsEHOFfC1hNpZkPix07W7GIDAZ0ulKN6wWP96LOARRWiJmLhY1eK7eqf/QIe76 miwiqWJceqJvECbus/En8QaCH5FKdYyMsjzEss9o4Bu6WbDdqkusT+D9YBFZ6k2e33 M1ScoW6Kkwdaw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 20/20] arm64: dts: mediatek: mt8195: Add SVS node and reduce LVTS_AP iospace Date: Tue, 21 Nov 2023 12:56:24 +0100 Message-ID: <20231121115624.56855-21-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 21 Nov 2023 03:58:13 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783174795139664863 X-GMAIL-MSGID: 1783174795139664863 Add the MediaTek SVS node: this will lower the voltage of various components of the SoC based on chip quality (read from fuses) in order to save power and generate less heat. Also, reduce the LVTS_AP iospace to 0xc00, because that's exactly where SVS starts. - LVTS_AP start: 0x1100b000 length: 0xc00 - SVS start: 0x1100bc00 length: 0x400 Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 54c674c45b49..54debd4cf8e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1115,7 +1115,7 @@ spi0: spi@1100a000 { lvts_ap: thermal-sensor@1100b000 { compatible = "mediatek,mt8195-lvts-ap"; - reg = <0 0x1100b000 0 0x1000>; + reg = <0 0x1100b000 0 0xc00>; interrupts = ; clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; @@ -1124,6 +1124,18 @@ lvts_ap: thermal-sensor@1100b000 { #thermal-sensor-cells = <1>; }; + svs: svs@1100bc00 { + compatible = "mediatek,mt8195-svs"; + reg = <0 0x1100bc00 0 0x400>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calib_data &lvts_efuse_data1>; + nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; + resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>; + reset-names = "svs_rst"; + }; + disp_pwm0: pwm@1100e000 { compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; @@ -1682,6 +1694,9 @@ lvts_efuse_data1: lvts1-calib@1bc { lvts_efuse_data2: lvts2-calib@1d0 { reg = <0x1d0 0x38>; }; + svs_calib_data: svs-calib@580 { + reg = <0x580 0x64>; + }; }; u3phy2: t-phy@11c40000 {