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Mon, 20 Nov 2023 14:06:38 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 20 Nov 2023 14:06:38 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 1/6] s390: Position independent verification of relative addressing Date: Mon, 20 Nov 2023 15:06:30 +0100 Message-Id: <20231120140635.3642601-2-jremus@linux.ibm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120140635.3642601-1-jremus@linux.ibm.com> References: <20231120140635.3642601-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: wwW-FWmlu1e98A3vfMbpK6X4MQklu8SG X-Proofpoint-GUID: wwW-FWmlu1e98A3vfMbpK6X4MQklu8SG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-20_13,2023-11-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=638 spamscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311200098 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783092222497597542 X-GMAIL-MSGID: 1783092222497597542 Opcode test cases for z/Architecture instructions that use relative addressing contained hardcoded offsets in the test verification patterns. Inserting or reordering of instructions into those test cases therefore required updating of those hardcoded offsets. Use regular expressions with backreferences to verify results of test cases containing instructions with relative addressing. This makes the verification position independent. gas/ * testsuite/gas/s390/esa-g5.d: Make opcode test verification pattern position independent where possible. * testsuite/gas/s390/esa-z900.d: Likewise. * testsuite/gas/s390/zarch-z900.d: Likewise. * testsuite/gas/s390/zarch-z10.d: Likewise. * testsuite/gas/s390/zarch-z196.d: Likewise. * testsuite/gas/s390/zarch-zEC12.d: Likewise. Signed-off-by: Jens Remus Reviewed-by: Andreas Krebbel --- gas/testsuite/gas/s390/esa-g5.d | 104 +++++------ gas/testsuite/gas/s390/esa-z900.d | 96 +++++----- gas/testsuite/gas/s390/zarch-z10.d | 254 +++++++++++++-------------- gas/testsuite/gas/s390/zarch-z196.d | 2 +- gas/testsuite/gas/s390/zarch-z900.d | 12 +- gas/testsuite/gas/s390/zarch-zEC12.d | 6 +- 6 files changed, 237 insertions(+), 237 deletions(-) diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d index 67a971bef15..7422e88b127 100644 --- a/gas/testsuite/gas/s390/esa-g5.d +++ b/gas/testsuite/gas/s390/esa-g5.d @@ -77,15 +77,15 @@ Disassembly of section .text: .*: 47 25 af ff [ ]*bh 4095\(%r5,%r10\) .*: 07 29 [ ]*bhr %r9 .*: 07 f9 [ ]*br %r9 -.*: a7 95 00 00 [ ]*bras %r9,e2 -.*: a7 65 00 00 [ ]*bras %r6,e6 -.*: a7 64 00 00 [ ]*jlh ea -.*: a7 66 00 00 [ ]*brct %r6,ee -.*: a7 66 00 00 [ ]*brct %r6,f2 -.*: 84 69 00 00 [ ]*brxh %r6,%r9,f6 -.*: 84 69 00 00 [ ]*brxh %r6,%r9,fa -.*: 85 69 00 00 [ ]*brxle %r6,%r9,fe -.*: 85 69 00 00 [ ]*brxle %r6,%r9,102 + *([\da-f]+): a7 95 00 00 [ ]*bras %r9,\1 + *([\da-f]+): a7 65 00 00 [ ]*bras %r6,\1 + *([\da-f]+): a7 64 00 00 [ ]*jlh \1 + *([\da-f]+): a7 66 00 00 [ ]*brct %r6,\1 + *([\da-f]+): a7 66 00 00 [ ]*brct %r6,\1 + *([\da-f]+): 84 69 00 00 [ ]*brxh %r6,%r9,\1 + *([\da-f]+): 84 69 00 00 [ ]*brxh %r6,%r9,\1 + *([\da-f]+): 85 69 00 00 [ ]*brxle %r6,%r9,\1 + *([\da-f]+): 85 69 00 00 [ ]*brxle %r6,%r9,\1 .*: b2 5a 00 69 [ ]*bsa %r6,%r9 .*: b2 58 00 69 [ ]*bsg %r6,%r9 .*: 0b 69 [ ]*bsm %r6,%r9 @@ -184,49 +184,49 @@ Disassembly of section .text: .*: b2 21 00 69 [ ]*ipte %r6,%r9 .*: b2 29 00 69 [ ]*iske %r6,%r9 .*: b2 23 00 69 [ ]*ivsk %r6,%r9 -.*: a7 f4 00 00 [ ]*j 288 -.*: a7 84 00 00 [ ]*je 28c -.*: a7 24 00 00 [ ]*jh 290 -.*: a7 a4 00 00 [ ]*jhe 294 -.*: a7 44 00 00 [ ]*jl 298 -.*: a7 c4 00 00 [ ]*jle 29c -.*: a7 64 00 00 [ ]*jlh 2a0 -.*: a7 44 00 00 [ ]*jl 2a4 -.*: a7 74 00 00 [ ]*jne 2a8 -.*: a7 d4 00 00 [ ]*jnh 2ac -.*: a7 54 00 00 [ ]*jnhe 2b0 -.*: a7 b4 00 00 [ ]*jnl 2b4 -.*: a7 34 00 00 [ ]*jnle 2b8 -.*: a7 94 00 00 [ ]*jnlh 2bc -.*: a7 b4 00 00 [ ]*jnl 2c0 -.*: a7 e4 00 00 [ ]*jno 2c4 -.*: a7 d4 00 00 [ ]*jnh 2c8 -.*: a7 74 00 00 [ ]*jne 2cc -.*: a7 14 00 00 [ ]*jo 2d0 -.*: a7 24 00 00 [ ]*jh 2d4 -.*: a7 84 00 00 [ ]*je 2d8 -.*: a7 04 00 00 [ ]*jnop 2dc -.*: a7 14 00 00 [ ]*jo 2e0 -.*: a7 24 00 00 [ ]*jh 2e4 -.*: a7 24 00 00 [ ]*jh 2e8 -.*: a7 34 00 00 [ ]*jnle 2ec -.*: a7 44 00 00 [ ]*jl 2f0 -.*: a7 44 00 00 [ ]*jl 2f4 -.*: a7 54 00 00 [ ]*jnhe 2f8 -.*: a7 64 00 00 [ ]*jlh 2fc -.*: a7 74 00 00 [ ]*jne 300 -.*: a7 74 00 00 [ ]*jne 304 -.*: a7 84 00 00 [ ]*je 308 -.*: a7 84 00 00 [ ]*je 30c -.*: a7 94 00 00 [ ]*jnlh 310 -.*: a7 a4 00 00 [ ]*jhe 314 -.*: a7 b4 00 00 [ ]*jnl 318 -.*: a7 b4 00 00 [ ]*jnl 31c -.*: a7 c4 00 00 [ ]*jle 320 -.*: a7 d4 00 00 [ ]*jnh 324 -.*: a7 d4 00 00 [ ]*jnh 328 -.*: a7 e4 00 00 [ ]*jno 32c -.*: a7 f4 00 00 [ ]*j 330 + *([\da-f]+): a7 f4 00 00 [ ]*j \1 + *([\da-f]+): a7 84 00 00 [ ]*je \1 + *([\da-f]+): a7 24 00 00 [ ]*jh \1 + *([\da-f]+): a7 a4 00 00 [ ]*jhe \1 + *([\da-f]+): a7 44 00 00 [ ]*jl \1 + *([\da-f]+): a7 c4 00 00 [ ]*jle \1 + *([\da-f]+): a7 64 00 00 [ ]*jlh \1 + *([\da-f]+): a7 44 00 00 [ ]*jl \1 + *([\da-f]+): a7 74 00 00 [ ]*jne \1 + *([\da-f]+): a7 d4 00 00 [ ]*jnh \1 + *([\da-f]+): a7 54 00 00 [ ]*jnhe \1 + *([\da-f]+): a7 b4 00 00 [ ]*jnl \1 + *([\da-f]+): a7 34 00 00 [ ]*jnle \1 + *([\da-f]+): a7 94 00 00 [ ]*jnlh \1 + *([\da-f]+): a7 b4 00 00 [ ]*jnl \1 + *([\da-f]+): a7 e4 00 00 [ ]*jno \1 + *([\da-f]+): a7 d4 00 00 [ ]*jnh \1 + *([\da-f]+): a7 74 00 00 [ ]*jne \1 + *([\da-f]+): a7 14 00 00 [ ]*jo \1 + *([\da-f]+): a7 24 00 00 [ ]*jh \1 + *([\da-f]+): a7 84 00 00 [ ]*je \1 + *([\da-f]+): a7 04 00 00 [ ]*jnop \1 + *([\da-f]+): a7 14 00 00 [ ]*jo \1 + *([\da-f]+): a7 24 00 00 [ ]*jh \1 + *([\da-f]+): a7 24 00 00 [ ]*jh \1 + *([\da-f]+): a7 34 00 00 [ ]*jnle \1 + *([\da-f]+): a7 44 00 00 [ ]*jl \1 + *([\da-f]+): a7 44 00 00 [ ]*jl \1 + *([\da-f]+): a7 54 00 00 [ ]*jnhe \1 + *([\da-f]+): a7 64 00 00 [ ]*jlh \1 + *([\da-f]+): a7 74 00 00 [ ]*jne \1 + *([\da-f]+): a7 74 00 00 [ ]*jne \1 + *([\da-f]+): a7 84 00 00 [ ]*je \1 + *([\da-f]+): a7 84 00 00 [ ]*je \1 + *([\da-f]+): a7 94 00 00 [ ]*jnlh \1 + *([\da-f]+): a7 a4 00 00 [ ]*jhe \1 + *([\da-f]+): a7 b4 00 00 [ ]*jnl \1 + *([\da-f]+): a7 b4 00 00 [ ]*jnl \1 + *([\da-f]+): a7 c4 00 00 [ ]*jle \1 + *([\da-f]+): a7 d4 00 00 [ ]*jnh \1 + *([\da-f]+): a7 d4 00 00 [ ]*jnh \1 + *([\da-f]+): a7 e4 00 00 [ ]*jno \1 + *([\da-f]+): a7 f4 00 00 [ ]*j \1 .*: ed 65 af ff 00 18 [ ]*kdb %f6,4095\(%r5,%r10\) .*: b3 18 00 69 [ ]*kdbr %f6,%f9 .*: ed 65 af ff 00 08 [ ]*keb %f6,4095\(%r5,%r10\) diff --git a/gas/testsuite/gas/s390/esa-z900.d b/gas/testsuite/gas/s390/esa-z900.d index 86db0641e95..75e3a385815 100644 --- a/gas/testsuite/gas/s390/esa-z900.d +++ b/gas/testsuite/gas/s390/esa-z900.d @@ -7,53 +7,53 @@ Disassembly of section .text: .* : .*: c0 f4 00 00 00 00 [ ]*jg 0 -.*: c0 04 00 00 00 00 [ ]*jgnop 6 -.*: c0 14 00 00 00 00 [ ]*jgo c -.*: c0 24 00 00 00 00 [ ]*jgh 12 -.*: c0 24 00 00 00 00 [ ]*jgh 18 -.*: c0 34 00 00 00 00 [ ]*jgnle 1e -.*: c0 44 00 00 00 00 [ ]*jgl 24 -.*: c0 44 00 00 00 00 [ ]*jgl 2a -.*: c0 54 00 00 00 00 [ ]*jgnhe 30 -.*: c0 64 00 00 00 00 [ ]*jglh 36 -.*: c0 74 00 00 00 00 [ ]*jgne 3c -.*: c0 74 00 00 00 00 [ ]*jgne 42 -.*: c0 84 00 00 00 00 [ ]*jge 48 -.*: c0 84 00 00 00 00 [ ]*jge 4e -.*: c0 94 00 00 00 00 [ ]*jgnlh 54 -.*: c0 a4 00 00 00 00 [ ]*jghe 5a -.*: c0 b4 00 00 00 00 [ ]*jgnl 60 -.*: c0 b4 00 00 00 00 [ ]*jgnl 66 -.*: c0 c4 00 00 00 00 [ ]*jgle 6c -.*: c0 d4 00 00 00 00 [ ]*jgnh 72 -.*: c0 d4 00 00 00 00 [ ]*jgnh 78 -.*: c0 e4 00 00 00 00 [ ]*jgno 7e -.*: c0 f4 00 00 00 00 [ ]*jg 84 -.*: c0 14 00 00 00 00 [ ]*jgo 8a -.*: c0 24 00 00 00 00 [ ]*jgh 90 -.*: c0 24 00 00 00 00 [ ]*jgh 96 -.*: c0 34 00 00 00 00 [ ]*jgnle 9c -.*: c0 44 00 00 00 00 [ ]*jgl a2 -.*: c0 44 00 00 00 00 [ ]*jgl a8 -.*: c0 54 00 00 00 00 [ ]*jgnhe ae -.*: c0 64 00 00 00 00 [ ]*jglh b4 -.*: c0 74 00 00 00 00 [ ]*jgne ba -.*: c0 74 00 00 00 00 [ ]*jgne c0 -.*: c0 84 00 00 00 00 [ ]*jge c6 -.*: c0 84 00 00 00 00 [ ]*jge cc -.*: c0 94 00 00 00 00 [ ]*jgnlh d2 -.*: c0 a4 00 00 00 00 [ ]*jghe d8 -.*: c0 b4 00 00 00 00 [ ]*jgnl de -.*: c0 b4 00 00 00 00 [ ]*jgnl e4 -.*: c0 c4 00 00 00 00 [ ]*jgle ea -.*: c0 d4 00 00 00 00 [ ]*jgnh f0 -.*: c0 d4 00 00 00 00 [ ]*jgnh f6 -.*: c0 e4 00 00 00 00 [ ]*jgno fc -.*: c0 f4 00 00 00 00 [ ]*jg 102 -.*: c0 65 00 00 00 00 [ ]*brasl %r6,108 -.*: c0 65 00 00 00 00 [ ]*brasl %r6,10e -.*: c0 65 80 00 00 00 [ ]*brasl %r6,114 -.*: c0 65 80 00 00 00 [ ]*brasl %r6,11a + *([\da-f]+): c0 04 00 00 00 00 [ ]*jgnop \1 + *([\da-f]+): c0 14 00 00 00 00 [ ]*jgo \1 + *([\da-f]+): c0 24 00 00 00 00 [ ]*jgh \1 + *([\da-f]+): c0 24 00 00 00 00 [ ]*jgh \1 + *([\da-f]+): c0 34 00 00 00 00 [ ]*jgnle \1 + *([\da-f]+): c0 44 00 00 00 00 [ ]*jgl \1 + *([\da-f]+): c0 44 00 00 00 00 [ ]*jgl \1 + *([\da-f]+): c0 54 00 00 00 00 [ ]*jgnhe \1 + *([\da-f]+): c0 64 00 00 00 00 [ ]*jglh \1 + *([\da-f]+): c0 74 00 00 00 00 [ ]*jgne \1 + *([\da-f]+): c0 74 00 00 00 00 [ ]*jgne \1 + *([\da-f]+): c0 84 00 00 00 00 [ ]*jge \1 + *([\da-f]+): c0 84 00 00 00 00 [ ]*jge \1 + *([\da-f]+): c0 94 00 00 00 00 [ ]*jgnlh \1 + *([\da-f]+): c0 a4 00 00 00 00 [ ]*jghe \1 + *([\da-f]+): c0 b4 00 00 00 00 [ ]*jgnl \1 + *([\da-f]+): c0 b4 00 00 00 00 [ ]*jgnl \1 + *([\da-f]+): c0 c4 00 00 00 00 [ ]*jgle \1 + *([\da-f]+): c0 d4 00 00 00 00 [ ]*jgnh \1 + *([\da-f]+): c0 d4 00 00 00 00 [ ]*jgnh \1 + *([\da-f]+): c0 e4 00 00 00 00 [ ]*jgno \1 + *([\da-f]+): c0 f4 00 00 00 00 [ ]*jg \1 + *([\da-f]+): c0 14 00 00 00 00 [ ]*jgo \1 + *([\da-f]+): c0 24 00 00 00 00 [ ]*jgh \1 + *([\da-f]+): c0 24 00 00 00 00 [ ]*jgh \1 + *([\da-f]+): c0 34 00 00 00 00 [ ]*jgnle \1 + *([\da-f]+): c0 44 00 00 00 00 [ ]*jgl \1 + *([\da-f]+): c0 44 00 00 00 00 [ ]*jgl \1 + *([\da-f]+): c0 54 00 00 00 00 [ ]*jgnhe \1 + *([\da-f]+): c0 64 00 00 00 00 [ ]*jglh \1 + *([\da-f]+): c0 74 00 00 00 00 [ ]*jgne \1 + *([\da-f]+): c0 74 00 00 00 00 [ ]*jgne \1 + *([\da-f]+): c0 84 00 00 00 00 [ ]*jge \1 + *([\da-f]+): c0 84 00 00 00 00 [ ]*jge \1 + *([\da-f]+): c0 94 00 00 00 00 [ ]*jgnlh \1 + *([\da-f]+): c0 a4 00 00 00 00 [ ]*jghe \1 + *([\da-f]+): c0 b4 00 00 00 00 [ ]*jgnl \1 + *([\da-f]+): c0 b4 00 00 00 00 [ ]*jgnl \1 + *([\da-f]+): c0 c4 00 00 00 00 [ ]*jgle \1 + *([\da-f]+): c0 d4 00 00 00 00 [ ]*jgnh \1 + *([\da-f]+): c0 d4 00 00 00 00 [ ]*jgnh \1 + *([\da-f]+): c0 e4 00 00 00 00 [ ]*jgno \1 + *([\da-f]+): c0 f4 00 00 00 00 [ ]*jg \1 + *([\da-f]+): c0 65 00 00 00 00 [ ]*brasl %r6,\1 + *([\da-f]+): c0 65 00 00 00 00 [ ]*brasl %r6,\1 + *([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,\1 + *([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,\1 .*: c0 65 7f ff ff ff [ ]*brasl %r6,11e .*: c0 65 7f ff ff ff [ ]*brasl %r6,124 .*: 01 0b [ ]*tam @@ -66,7 +66,7 @@ Disassembly of section .text: .*: b9 97 00 69 [ ]*dlr %r6,%r9 .*: b9 98 00 69 [ ]*alcr %r6,%r9 .*: b9 99 00 69 [ ]*slbr %r6,%r9 -.*: c0 60 00 00 00 00 [ ]*larl %r6,14e + *([\da-f]+): c0 60 00 00 00 00 [ ]*larl %r6,\1 .*: e3 65 af ff 00 1e [ ]*lrv %r6,4095\(%r5,%r10\) .*: e3 65 af ff 00 1f [ ]*lrvh %r6,4095\(%r5,%r10\) .*: e3 65 af ff 00 3e [ ]*strv %r6,4095\(%r5,%r10\) diff --git a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d index 183e98ee741..2c7c485a1a1 100644 --- a/gas/testsuite/gas/s390/zarch-z10.d +++ b/gas/testsuite/gas/s390/zarch-z10.d @@ -10,9 +10,9 @@ Disassembly of section .text: .*: eb d6 65 b3 01 7a [ ]*agsi 5555\(%r6\),-42 .*: eb d6 65 b3 01 6e [ ]*alsi 5555\(%r6\),-42 .*: eb d6 65 b3 01 7e [ ]*algsi 5555\(%r6\),-42 -.*: c6 6d 00 00 00 00 [ ]*crl %r6,18 -.*: c6 68 00 00 00 00 [ ]*cgrl %r6,1e -.*: c6 6c 00 00 00 00 [ ]*cgfrl %r6,24 + *([\da-f]+): c6 6d 00 00 00 00 [ ]*crl %r6,\1 + *([\da-f]+): c6 68 00 00 00 00 [ ]*cgrl %r6,\1 + *([\da-f]+): c6 6c 00 00 00 00 [ ]*cgfrl %r6,\1 .*: ec 67 84 57 a0 f6 [ ]*crbnl %r6,%r7,1111\(%r8\) .*: ec 67 84 57 20 f6 [ ]*crbh %r6,%r7,1111\(%r8\) .*: ec 67 84 57 20 f6 [ ]*crbh %r6,%r7,1111\(%r8\) @@ -39,32 +39,32 @@ Disassembly of section .text: .*: ec 67 84 57 a0 e4 [ ]*cgrbnl %r6,%r7,1111\(%r8\) .*: ec 67 84 57 c0 e4 [ ]*cgrbnh %r6,%r7,1111\(%r8\) .*: ec 67 84 57 c0 e4 [ ]*cgrbnh %r6,%r7,1111\(%r8\) -.*: ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,c6 -.*: ec 67 00 00 20 76 [ ]*crjh %r6,%r7,cc -.*: ec 67 00 00 20 76 [ ]*crjh %r6,%r7,d2 -.*: ec 67 00 00 40 76 [ ]*crjl %r6,%r7,d8 -.*: ec 67 00 00 40 76 [ ]*crjl %r6,%r7,de -.*: ec 67 00 00 60 76 [ ]*crjne %r6,%r7,e4 -.*: ec 67 00 00 60 76 [ ]*crjne %r6,%r7,ea -.*: ec 67 00 00 80 76 [ ]*crje %r6,%r7,f0 -.*: ec 67 00 00 80 76 [ ]*crje %r6,%r7,f6 -.*: ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,fc -.*: ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,102 -.*: ec 67 00 00 c0 76 [ ]*crjnh %r6,%r7,108 -.*: ec 67 00 00 c0 76 [ ]*crjnh %r6,%r7,10e -.*: ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,114 -.*: ec 67 00 00 20 64 [ ]*cgrjh %r6,%r7,11a -.*: ec 67 00 00 20 64 [ ]*cgrjh %r6,%r7,120 -.*: ec 67 00 00 40 64 [ ]*cgrjl %r6,%r7,126 -.*: ec 67 00 00 40 64 [ ]*cgrjl %r6,%r7,12c -.*: ec 67 00 00 60 64 [ ]*cgrjne %r6,%r7,132 -.*: ec 67 00 00 60 64 [ ]*cgrjne %r6,%r7,138 -.*: ec 67 00 00 80 64 [ ]*cgrje %r6,%r7,13e -.*: ec 67 00 00 80 64 [ ]*cgrje %r6,%r7,144 -.*: ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,14a -.*: ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,150 -.*: ec 67 00 00 c0 64 [ ]*cgrjnh %r6,%r7,156 -.*: ec 67 00 00 c0 64 [ ]*cgrjnh %r6,%r7,15c + *([\da-f]+): ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 20 76 [ ]*crjh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 20 76 [ ]*crjh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 40 76 [ ]*crjl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 40 76 [ ]*crjl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 60 76 [ ]*crjne %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 60 76 [ ]*crjne %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 80 76 [ ]*crje %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 80 76 [ ]*crje %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 a0 76 [ ]*crjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 c0 76 [ ]*crjnh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 c0 76 [ ]*crjnh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 20 64 [ ]*cgrjh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 20 64 [ ]*cgrjh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 40 64 [ ]*cgrjl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 40 64 [ ]*cgrjl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 60 64 [ ]*cgrjne %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 60 64 [ ]*cgrjne %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 80 64 [ ]*cgrje %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 80 64 [ ]*cgrje %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 a0 64 [ ]*cgrjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 c0 64 [ ]*cgrjnh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 c0 64 [ ]*cgrjnh %r6,%r7,\1 .*: ec 6a 74 57 d6 fe [ ]*cibnl %r6,-42,1111\(%r7\) .*: ec 62 74 57 d6 fe [ ]*cibh %r6,-42,1111\(%r7\) .*: ec 62 74 57 d6 fe [ ]*cibh %r6,-42,1111\(%r7\) @@ -91,32 +91,32 @@ Disassembly of section .text: .*: ec 6a 74 57 d6 fc [ ]*cgibnl %r6,-42,1111\(%r7\) .*: ec 6c 74 57 d6 fc [ ]*cgibnh %r6,-42,1111\(%r7\) .*: ec 6c 74 57 d6 fc [ ]*cgibnh %r6,-42,1111\(%r7\) -.*: ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,1fe -.*: ec 62 00 00 d6 7e [ ]*cijh %r6,-42,204 -.*: ec 62 00 00 d6 7e [ ]*cijh %r6,-42,20a -.*: ec 64 00 00 d6 7e [ ]*cijl %r6,-42,210 -.*: ec 64 00 00 d6 7e [ ]*cijl %r6,-42,216 -.*: ec 66 00 00 d6 7e [ ]*cijne %r6,-42,21c -.*: ec 66 00 00 d6 7e [ ]*cijne %r6,-42,222 -.*: ec 68 00 00 d6 7e [ ]*cije %r6,-42,228 -.*: ec 68 00 00 d6 7e [ ]*cije %r6,-42,22e -.*: ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,234 -.*: ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,23a -.*: ec 6c 00 00 d6 7e [ ]*cijnh %r6,-42,240 -.*: ec 6c 00 00 d6 7e [ ]*cijnh %r6,-42,246 -.*: ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,24c -.*: ec 62 00 00 d6 7c [ ]*cgijh %r6,-42,252 -.*: ec 62 00 00 d6 7c [ ]*cgijh %r6,-42,258 -.*: ec 64 00 00 d6 7c [ ]*cgijl %r6,-42,25e -.*: ec 64 00 00 d6 7c [ ]*cgijl %r6,-42,264 -.*: ec 66 00 00 d6 7c [ ]*cgijne %r6,-42,26a -.*: ec 66 00 00 d6 7c [ ]*cgijne %r6,-42,270 -.*: ec 68 00 00 d6 7c [ ]*cgije %r6,-42,276 -.*: ec 68 00 00 d6 7c [ ]*cgije %r6,-42,27c -.*: ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,282 -.*: ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,288 -.*: ec 6c 00 00 d6 7c [ ]*cgijnh %r6,-42,28e -.*: ec 6c 00 00 d6 7c [ ]*cgijnh %r6,-42,294 + *([\da-f]+): ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,\1 + *([\da-f]+): ec 62 00 00 d6 7e [ ]*cijh %r6,-42,\1 + *([\da-f]+): ec 62 00 00 d6 7e [ ]*cijh %r6,-42,\1 + *([\da-f]+): ec 64 00 00 d6 7e [ ]*cijl %r6,-42,\1 + *([\da-f]+): ec 64 00 00 d6 7e [ ]*cijl %r6,-42,\1 + *([\da-f]+): ec 66 00 00 d6 7e [ ]*cijne %r6,-42,\1 + *([\da-f]+): ec 66 00 00 d6 7e [ ]*cijne %r6,-42,\1 + *([\da-f]+): ec 68 00 00 d6 7e [ ]*cije %r6,-42,\1 + *([\da-f]+): ec 68 00 00 d6 7e [ ]*cije %r6,-42,\1 + *([\da-f]+): ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,\1 + *([\da-f]+): ec 6a 00 00 d6 7e [ ]*cijnl %r6,-42,\1 + *([\da-f]+): ec 6c 00 00 d6 7e [ ]*cijnh %r6,-42,\1 + *([\da-f]+): ec 6c 00 00 d6 7e [ ]*cijnh %r6,-42,\1 + *([\da-f]+): ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,\1 + *([\da-f]+): ec 62 00 00 d6 7c [ ]*cgijh %r6,-42,\1 + *([\da-f]+): ec 62 00 00 d6 7c [ ]*cgijh %r6,-42,\1 + *([\da-f]+): ec 64 00 00 d6 7c [ ]*cgijl %r6,-42,\1 + *([\da-f]+): ec 64 00 00 d6 7c [ ]*cgijl %r6,-42,\1 + *([\da-f]+): ec 66 00 00 d6 7c [ ]*cgijne %r6,-42,\1 + *([\da-f]+): ec 66 00 00 d6 7c [ ]*cgijne %r6,-42,\1 + *([\da-f]+): ec 68 00 00 d6 7c [ ]*cgije %r6,-42,\1 + *([\da-f]+): ec 68 00 00 d6 7c [ ]*cgije %r6,-42,\1 + *([\da-f]+): ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,\1 + *([\da-f]+): ec 6a 00 00 d6 7c [ ]*cgijnl %r6,-42,\1 + *([\da-f]+): ec 6c 00 00 d6 7c [ ]*cgijnh %r6,-42,\1 + *([\da-f]+): ec 6c 00 00 d6 7c [ ]*cgijnh %r6,-42,\1 .*: b9 72 a0 67 [ ]*crtnl %r6,%r7 .*: b9 72 20 67 [ ]*crth %r6,%r7 .*: b9 72 20 67 [ ]*crth %r6,%r7 @@ -173,16 +173,16 @@ Disassembly of section .text: .*: e5 54 64 57 8a d0 [ ]*chhsi 1111\(%r6\),-30000 .*: e5 5c 64 57 8a d0 [ ]*chsi 1111\(%r6\),-30000 .*: e5 58 64 57 8a d0 [ ]*cghsi 1111\(%r6\),-30000 -.*: c6 65 00 00 00 00 [ ]*chrl %r6,3b6 -.*: c6 64 00 00 00 00 [ ]*cghrl %r6,3bc + *([\da-f]+): c6 65 00 00 00 00 [ ]*chrl %r6,\1 + *([\da-f]+): c6 64 00 00 00 00 [ ]*cghrl %r6,\1 .*: e5 55 64 57 9c 40 [ ]*clhhsi 1111\(%r6\),40000 .*: e5 5d 64 57 9c 40 [ ]*clfhsi 1111\(%r6\),40000 .*: e5 59 64 57 9c 40 [ ]*clghsi 1111\(%r6\),40000 -.*: c6 6f 00 00 00 00 [ ]*clrl %r6,3d4 -.*: c6 6a 00 00 00 00 [ ]*clgrl %r6,3da -.*: c6 6e 00 00 00 00 [ ]*clgfrl %r6,3e0 -.*: c6 67 00 00 00 00 [ ]*clhrl %r6,3e6 -.*: c6 66 00 00 00 00 [ ]*clghrl %r6,3ec + *([\da-f]+): c6 6f 00 00 00 00 [ ]*clrl %r6,\1 + *([\da-f]+): c6 6a 00 00 00 00 [ ]*clgrl %r6,\1 + *([\da-f]+): c6 6e 00 00 00 00 [ ]*clgfrl %r6,\1 + *([\da-f]+): c6 67 00 00 00 00 [ ]*clhrl %r6,\1 + *([\da-f]+): c6 66 00 00 00 00 [ ]*clghrl %r6,\1 .*: ec 67 84 57 a0 f7 [ ]*clrbnl %r6,%r7,1111\(%r8\) .*: ec 67 84 57 20 f7 [ ]*clrbh %r6,%r7,1111\(%r8\) .*: ec 67 84 57 20 f7 [ ]*clrbh %r6,%r7,1111\(%r8\) @@ -209,32 +209,32 @@ Disassembly of section .text: .*: ec 67 84 57 a0 e5 [ ]*clgrbnl %r6,%r7,1111\(%r8\) .*: ec 67 84 57 c0 e5 [ ]*clgrbnh %r6,%r7,1111\(%r8\) .*: ec 67 84 57 c0 e5 [ ]*clgrbnh %r6,%r7,1111\(%r8\) -.*: ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,48e -.*: ec 67 00 00 20 77 [ ]*clrjh %r6,%r7,494 -.*: ec 67 00 00 20 77 [ ]*clrjh %r6,%r7,49a -.*: ec 67 00 00 40 77 [ ]*clrjl %r6,%r7,4a0 -.*: ec 67 00 00 40 77 [ ]*clrjl %r6,%r7,4a6 -.*: ec 67 00 00 60 77 [ ]*clrjne %r6,%r7,4ac -.*: ec 67 00 00 60 77 [ ]*clrjne %r6,%r7,4b2 -.*: ec 67 00 00 80 77 [ ]*clrje %r6,%r7,4b8 -.*: ec 67 00 00 80 77 [ ]*clrje %r6,%r7,4be -.*: ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,4c4 -.*: ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,4ca -.*: ec 67 00 00 c0 77 [ ]*clrjnh %r6,%r7,4d0 -.*: ec 67 00 00 c0 77 [ ]*clrjnh %r6,%r7,4d6 -.*: ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,4dc -.*: ec 67 00 00 20 65 [ ]*clgrjh %r6,%r7,4e2 -.*: ec 67 00 00 20 65 [ ]*clgrjh %r6,%r7,4e8 -.*: ec 67 00 00 40 65 [ ]*clgrjl %r6,%r7,4ee -.*: ec 67 00 00 40 65 [ ]*clgrjl %r6,%r7,4f4 -.*: ec 67 00 00 60 65 [ ]*clgrjne %r6,%r7,4fa -.*: ec 67 00 00 60 65 [ ]*clgrjne %r6,%r7,500 -.*: ec 67 00 00 80 65 [ ]*clgrje %r6,%r7,506 -.*: ec 67 00 00 80 65 [ ]*clgrje %r6,%r7,50c -.*: ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,512 -.*: ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,518 -.*: ec 67 00 00 c0 65 [ ]*clgrjnh %r6,%r7,51e -.*: ec 67 00 00 c0 65 [ ]*clgrjnh %r6,%r7,524 + *([\da-f]+): ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 20 77 [ ]*clrjh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 20 77 [ ]*clrjh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 40 77 [ ]*clrjl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 40 77 [ ]*clrjl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 60 77 [ ]*clrjne %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 60 77 [ ]*clrjne %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 80 77 [ ]*clrje %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 80 77 [ ]*clrje %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 a0 77 [ ]*clrjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 c0 77 [ ]*clrjnh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 c0 77 [ ]*clrjnh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 20 65 [ ]*clgrjh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 20 65 [ ]*clgrjh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 40 65 [ ]*clgrjl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 40 65 [ ]*clgrjl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 60 65 [ ]*clgrjne %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 60 65 [ ]*clgrjne %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 80 65 [ ]*clgrje %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 80 65 [ ]*clgrje %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 a0 65 [ ]*clgrjnl %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 c0 65 [ ]*clgrjnh %r6,%r7,\1 + *([\da-f]+): ec 67 00 00 c0 65 [ ]*clgrjnh %r6,%r7,\1 .*: ec 6a 74 57 c8 ff [ ]*clibnl %r6,200,1111\(%r7\) .*: ec 62 74 57 c8 ff [ ]*clibh %r6,200,1111\(%r7\) .*: ec 62 74 57 c8 ff [ ]*clibh %r6,200,1111\(%r7\) @@ -261,32 +261,32 @@ Disassembly of section .text: .*: ec 6a 74 57 c8 fd [ ]*clgibnl %r6,200,1111\(%r7\) .*: ec 6c 74 57 c8 fd [ ]*clgibnh %r6,200,1111\(%r7\) .*: ec 6c 74 57 c8 fd [ ]*clgibnh %r6,200,1111\(%r7\) -.*: ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,5c6 -.*: ec 62 00 00 c8 7f [ ]*clijh %r6,200,5cc -.*: ec 62 00 00 c8 7f [ ]*clijh %r6,200,5d2 -.*: ec 64 00 00 c8 7f [ ]*clijl %r6,200,5d8 -.*: ec 64 00 00 c8 7f [ ]*clijl %r6,200,5de -.*: ec 66 00 00 c8 7f [ ]*clijne %r6,200,5e4 -.*: ec 66 00 00 c8 7f [ ]*clijne %r6,200,5ea -.*: ec 68 00 00 c8 7f [ ]*clije %r6,200,5f0 -.*: ec 68 00 00 c8 7f [ ]*clije %r6,200,5f6 -.*: ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,5fc -.*: ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,602 -.*: ec 6c 00 00 c8 7f [ ]*clijnh %r6,200,608 -.*: ec 6c 00 00 c8 7f [ ]*clijnh %r6,200,60e -.*: ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,614 -.*: ec 62 00 00 c8 7d [ ]*clgijh %r6,200,61a -.*: ec 62 00 00 c8 7d [ ]*clgijh %r6,200,620 -.*: ec 64 00 00 c8 7d [ ]*clgijl %r6,200,626 -.*: ec 64 00 00 c8 7d [ ]*clgijl %r6,200,62c -.*: ec 66 00 00 c8 7d [ ]*clgijne %r6,200,632 -.*: ec 66 00 00 c8 7d [ ]*clgijne %r6,200,638 -.*: ec 68 00 00 c8 7d [ ]*clgije %r6,200,63e -.*: ec 68 00 00 c8 7d [ ]*clgije %r6,200,644 -.*: ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,64a -.*: ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,650 -.*: ec 6c 00 00 c8 7d [ ]*clgijnh %r6,200,656 -.*: ec 6c 00 00 c8 7d [ ]*clgijnh %r6,200,65c + *([\da-f]+): ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,\1 + *([\da-f]+): ec 62 00 00 c8 7f [ ]*clijh %r6,200,\1 + *([\da-f]+): ec 62 00 00 c8 7f [ ]*clijh %r6,200,\1 + *([\da-f]+): ec 64 00 00 c8 7f [ ]*clijl %r6,200,\1 + *([\da-f]+): ec 64 00 00 c8 7f [ ]*clijl %r6,200,\1 + *([\da-f]+): ec 66 00 00 c8 7f [ ]*clijne %r6,200,\1 + *([\da-f]+): ec 66 00 00 c8 7f [ ]*clijne %r6,200,\1 + *([\da-f]+): ec 68 00 00 c8 7f [ ]*clije %r6,200,\1 + *([\da-f]+): ec 68 00 00 c8 7f [ ]*clije %r6,200,\1 + *([\da-f]+): ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,\1 + *([\da-f]+): ec 6a 00 00 c8 7f [ ]*clijnl %r6,200,\1 + *([\da-f]+): ec 6c 00 00 c8 7f [ ]*clijnh %r6,200,\1 + *([\da-f]+): ec 6c 00 00 c8 7f [ ]*clijnh %r6,200,\1 + *([\da-f]+): ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,\1 + *([\da-f]+): ec 62 00 00 c8 7d [ ]*clgijh %r6,200,\1 + *([\da-f]+): ec 62 00 00 c8 7d [ ]*clgijh %r6,200,\1 + *([\da-f]+): ec 64 00 00 c8 7d [ ]*clgijl %r6,200,\1 + *([\da-f]+): ec 64 00 00 c8 7d [ ]*clgijl %r6,200,\1 + *([\da-f]+): ec 66 00 00 c8 7d [ ]*clgijne %r6,200,\1 + *([\da-f]+): ec 66 00 00 c8 7d [ ]*clgijne %r6,200,\1 + *([\da-f]+): ec 68 00 00 c8 7d [ ]*clgije %r6,200,\1 + *([\da-f]+): ec 68 00 00 c8 7d [ ]*clgije %r6,200,\1 + *([\da-f]+): ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,\1 + *([\da-f]+): ec 6a 00 00 c8 7d [ ]*clgijnl %r6,200,\1 + *([\da-f]+): ec 6c 00 00 c8 7d [ ]*clgijnh %r6,200,\1 + *([\da-f]+): ec 6c 00 00 c8 7d [ ]*clgijnh %r6,200,\1 .*: b9 73 a0 67 [ ]*clrtnl %r6,%r7 .*: b9 73 20 67 [ ]*clrth %r6,%r7 .*: b9 73 20 67 [ ]*clrth %r6,%r7 @@ -340,16 +340,16 @@ Disassembly of section .text: .*: ec 60 75 30 c0 71 [ ]*clgitnh %r6,30000 .*: ec 60 75 30 c0 71 [ ]*clgitnh %r6,30000 .*: eb 67 84 57 00 4c [ ]*ecag %r6,%r7,1111\(%r8\) -.*: c4 6d 00 00 00 00 [ ]*lrl %r6,76c -.*: c4 68 00 00 00 00 [ ]*lgrl %r6,772 -.*: c4 6c 00 00 00 00 [ ]*lgfrl %r6,778 + *([\da-f]+): c4 6d 00 00 00 00 [ ]*lrl %r6,\1 + *([\da-f]+): c4 68 00 00 00 00 [ ]*lgrl %r6,\1 + *([\da-f]+): c4 6c 00 00 00 00 [ ]*lgfrl %r6,\1 .*: e3 67 85 b3 01 75 [ ]*laey %r6,5555\(%r7,%r8\) .*: e3 67 85 b3 01 32 [ ]*ltgf %r6,5555\(%r7,%r8\) -.*: c4 65 00 00 00 00 [ ]*lhrl %r6,78a -.*: c4 64 00 00 00 00 [ ]*lghrl %r6,790 -.*: c4 6e 00 00 00 00 [ ]*llgfrl %r6,796 -.*: c4 62 00 00 00 00 [ ]*llhrl %r6,79c -.*: c4 66 00 00 00 00 [ ]*llghrl %r6,7a2 + *([\da-f]+): c4 65 00 00 00 00 [ ]*lhrl %r6,\1 + *([\da-f]+): c4 64 00 00 00 00 [ ]*lghrl %r6,\1 + *([\da-f]+): c4 6e 00 00 00 00 [ ]*llgfrl %r6,\1 + *([\da-f]+): c4 62 00 00 00 00 [ ]*llhrl %r6,\1 + *([\da-f]+): c4 66 00 00 00 00 [ ]*llghrl %r6,\1 .*: e5 44 64 57 8a d0 [ ]*mvhhi 1111\(%r6\),-30000 .*: e5 4c 64 57 8a d0 [ ]*mvhi 1111\(%r6\),-30000 .*: e5 48 64 57 8a d0 [ ]*mvghi 1111\(%r6\),-30000 @@ -358,17 +358,17 @@ Disassembly of section .text: .*: c2 61 ff fe 79 60 [ ]*msfi %r6,-100000 .*: c2 60 ff fe 79 60 [ ]*msgfi %r6,-100000 .*: e3 a6 75 b3 01 36 [ ]*pfd 10,5555\(%r6,%r7\) -.*: c6 a2 00 00 00 00 [ ]*pfdrl 10,7d8 + *([\da-f]+): c6 a2 00 00 00 00 [ ]*pfdrl 10,\1 .*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230 .*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230 .*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230 .*: ec 67 d2 14 e6 55 [ ]*risbg %r6,%r7,210,20,230 .*: ec 67 d2 bc e6 55 [ ]*risbgz %r6,%r7,210,60,230 .*: ec 67 d2 94 e6 55 [ ]*risbgz %r6,%r7,210,20,230 -.*: c4 6f 00 00 00 00 [ ]*strl %r6,802 -.*: c4 6b 00 00 00 00 [ ]*stgrl %r6,808 -.*: c4 67 00 00 00 00 [ ]*sthrl %r6,80e -.*: c6 60 00 00 00 00 [ ]*exrl %r6,814 + *([\da-f]+): c4 6f 00 00 00 00 [ ]*strl %r6,\1 + *([\da-f]+): c4 6b 00 00 00 00 [ ]*stgrl %r6,\1 + *([\da-f]+): c4 67 00 00 00 00 [ ]*sthrl %r6,\1 + *([\da-f]+): c6 60 00 00 00 00 [ ]*exrl %r6,\1 .*: af ee 6d 05 [ ]*mc 3333\(%r6\),238 .*: b9 a2 00 60 [ ]*ptf %r6 .*: b9 af 00 67 [ ]*pfmf %r6,%r7 diff --git a/gas/testsuite/gas/s390/zarch-z196.d b/gas/testsuite/gas/s390/zarch-z196.d index 3889d32e02f..0f8bfeafa25 100644 --- a/gas/testsuite/gas/s390/zarch-z196.d +++ b/gas/testsuite/gas/s390/zarch-z196.d @@ -13,7 +13,7 @@ Disassembly of section .text: .*: b9 da 80 67 [ ]*alhhlr %r6,%r7,%r8 .*: cc 6a 00 00 fd e8 [ ]*alsih %r6,65000 .*: cc 6b 00 00 fd e8 [ ]*alsihn %r6,65000 -.*: cc 66 00 00 00 00 [ ]*brcth %r6,22 + *([\da-f]+): cc 66 00 00 00 00 [ ]*brcth %r6,\1 .*: b9 cd 00 67 [ ]*chhr %r6,%r7 .*: b9 dd 00 67 [ ]*chlr %r6,%r7 .*: e3 67 85 b3 01 cd [ ]*chf %r6,5555\(%r7,%r8\) diff --git a/gas/testsuite/gas/s390/zarch-z900.d b/gas/testsuite/gas/s390/zarch-z900.d index 8d292dfc11b..2848dc1eb7c 100644 --- a/gas/testsuite/gas/s390/zarch-z900.d +++ b/gas/testsuite/gas/s390/zarch-z900.d @@ -19,12 +19,12 @@ Disassembly of section .text: .*: b9 0a 00 96 [ ]*algr %r9,%r6 .*: e3 95 af ff 00 46 [ ]*bctg %r9,4095\(%r5,%r10\) .*: b9 46 00 96 [ ]*bctgr %r9,%r6 -.*: a7 97 00 00 [ ]*brctg %r9,40 \ -.*: a7 67 00 00 [ ]*brctg %r6,44 -.*: ec 96 00 00 00 44 [ ]*brxhg %r9,%r6,48 -.*: ec 69 00 00 00 44 [ ]*brxhg %r6,%r9,4e -.*: ec 96 00 00 00 45 [ ]*brxlg %r9,%r6,54 -.*: ec 69 00 00 00 45 [ ]*brxlg %r6,%r9,5a + *([\da-f]+): a7 97 00 00 [ ]*brctg %r9,\1 + *([\da-f]+): a7 67 00 00 [ ]*brctg %r6,\1 + *([\da-f]+): ec 96 00 00 00 44 [ ]*brxhg %r9,%r6,\1 + *([\da-f]+): ec 69 00 00 00 44 [ ]*brxhg %r6,%r9,\1 + *([\da-f]+): ec 96 00 00 00 45 [ ]*brxlg %r9,%r6,\1 + *([\da-f]+): ec 69 00 00 00 45 [ ]*brxlg %r6,%r9,\1 .*: eb 96 5f ff 00 44 [ ]*bxhg %r9,%r6,4095\(%r5\) .*: eb 96 5f ff 00 45 [ ]*bxleg %r9,%r6,4095\(%r5\) .*: b3 a5 00 96 [ ]*cdgbr %f9,%r6 diff --git a/gas/testsuite/gas/s390/zarch-zEC12.d b/gas/testsuite/gas/s390/zarch-zEC12.d index e25ac134e1f..96bf59b9fb0 100644 --- a/gas/testsuite/gas/s390/zarch-zEC12.d +++ b/gas/testsuite/gas/s390/zarch-zEC12.d @@ -57,12 +57,12 @@ Disassembly of section .text: .*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9 .*: b9 8f 61 59 [ ]*crdte %r5,%r6,%r9,1 .*: c5 a0 0c 00 00 0c [ ]*bprp 10,136 ,136 -.*: c5 a0 00 00 00 00 [ ]*bprp 10,124 ,124 + *([\da-f]+): c5 a0 00 00 00 00 [ ]*bprp 10,\1 ,\1 [ ]*125: R_390_PLT12DBL bar\+0x1 [ ]*127: R_390_PLT24DBL bar\+0x3 -.*: c7 a0 00 00 00 00 [ ]*bpp 10,12a ,0 + *([\da-f]+): c7 a0 00 00 00 00 [ ]*bpp 10,\1 ,0 [ ]*12e: R_390_PLT16DBL bar\+0x4 -.*: c7 a0 00 00 00 00 [ ]*bpp 10,130 ,0 + *([\da-f]+): c7 a0 00 00 00 00 [ ]*bpp 10,\1 ,0 [ ]*134: R_390_PC16DBL baz\+0x4 From patchwork Mon Nov 20 14:06:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 167161 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9910:0:b0:403:3b70:6f57 with SMTP id i16csp2223742vqn; Mon, 20 Nov 2023 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Mon, 20 Nov 2023 14:06:39 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 20 Nov 2023 14:06:39 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 2/6] s390: Add brasl edge test cases from ESA to z/Architecture Date: Mon, 20 Nov 2023 15:06:31 +0100 Message-Id: <20231120140635.3642601-3-jremus@linux.ibm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120140635.3642601-1-jremus@linux.ibm.com> References: <20231120140635.3642601-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: AFOoab5FqPUE21fq5tgSe_pmrGNtTpLI X-Proofpoint-ORIG-GUID: AFOoab5FqPUE21fq5tgSe_pmrGNtTpLI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-20_13,2023-11-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 phishscore=0 bulkscore=0 suspectscore=0 mlxscore=0 priorityscore=1501 mlxlogscore=879 lowpriorityscore=0 clxscore=1015 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311200098 X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783092251055456102 X-GMAIL-MSGID: 1783092251055456102 The ESA opcode test cases for IBM z900 contain a few edge cases. They exercise the brasl mnemonic with its largest allowed negative and positive offsets. Linux on zSeries in ESA mode executes in 31-bit addressing mode. Therefore the ESA test cases are assembled with -m31. In 31-bit addressing mode the address computation using those large offsets wraps, which is correctly reflected in the disassembly. Linux on Z in z/Architecture mode executes in 64-bit addressing mode. Therefore the z/Architecture (zarch) test cases are assembled with -m64. In 64-bit addressing mode the address computation using those large offsets does not necessarily wrap. gas/ * testsuite/gas/s390/zarch-z900.s: Add brasl tests from ESA that exercise edge cases. * testsuite/gas/s390/zarch-z900.d: Likewise. Signed-off-by: Jens Remus Reviewed-by: Andreas Krebbel --- gas/testsuite/gas/s390/zarch-z900.d | 6 ++++++ gas/testsuite/gas/s390/zarch-z900.s | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/gas/testsuite/gas/s390/zarch-z900.d b/gas/testsuite/gas/s390/zarch-z900.d index 2848dc1eb7c..93aee212785 100644 --- a/gas/testsuite/gas/s390/zarch-z900.d +++ b/gas/testsuite/gas/s390/zarch-z900.d @@ -149,4 +149,10 @@ Disassembly of section .text: .*: eb 96 5f ff 00 0f [ ]*tracg %r9,%r6,4095\(%r5\) .*: e3 95 af ff 00 82 [ ]*xg %r9,4095\(%r5,%r10\) .*: b9 82 00 96 [ ]*xgr %r9,%r6 + *([\da-f]+): c0 65 00 00 00 00 [ ]*brasl %r6,\1 + *([\da-f]+): c0 65 00 00 00 00 [ ]*brasl %r6,\1 + *([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,ffffffff0+\1 + *([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,ffffffff0+\1 +.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002d0 +.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002d6 .*: 07 07 [ ]*nopr %r7 diff --git a/gas/testsuite/gas/s390/zarch-z900.s b/gas/testsuite/gas/s390/zarch-z900.s index 96d27e7b7e2..22fa1da5a30 100644 --- a/gas/testsuite/gas/s390/zarch-z900.s +++ b/gas/testsuite/gas/s390/zarch-z900.s @@ -143,3 +143,9 @@ foo: tracg %r9,%r6,4095(%r5) xg %r9,4095(%r5,%r10) xgr %r9,%r6 + brasl %r6,. + jasl %r6,. + brasl %r6,.-0x100000000 + jasl %r6,.-0x100000000 + brasl %r6,.+0xfffffffe + jasl %r6,.+0xfffffffe From patchwork Mon Nov 20 14:06:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 167162 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9910:0:b0:403:3b70:6f57 with SMTP id i16csp2224607vqn; Mon, 20 Nov 2023 06:09:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IHU1ntFLn3PUwS3ivI5mhCuGYjpVBYp4mcTp8okSA/rFSfNoAi3WHY5wYct7eueLEtm8YRm X-Received: by 2002:a05:620a:8008:b0:774:3497:a7a3 with SMTP id ee8-20020a05620a800800b007743497a7a3mr8216233qkb.17.1700489343887; Mon, 20 Nov 2023 06:09:03 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1700489343; cv=pass; d=google.com; s=arc-20160816; b=X1X9FqFeutrDsATMTg7g6OvrTruTROD/84AJofcqxsXDlfwc0B5q/hlQQcEjukSe03 Yc09wXNGp4iJoAocJ9+m9jgyCO6UVolXAF9ZEnrTWjBj5Fc4Y2+2rCNCk15hRr1YAVvh WrDeyqhBvp2okd4gWV0V7AI6TQaPpwYbVkToDco8zwqHc7t7ZkShA6NYkjhlcPE284nc hNn40kLZ/UNC1C3JQ3hVJoouu2g8Anqpo6UazTukFLPnmOTP7DE/Z6SionwV9JRfDkzW yZRxEUG/gd7ZSFUph8DDkb7m7IiJnMTVJ0uFGcqzlF02w3n1lhCPn2dj/I2mdQPxFL1D FHIA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=EgIfsJPwc5iTI7bIiEVmejIjf82TUtp9Z3I0bOaZiAI=; fh=6sWHPsCQUoLz5ZcbqIohOjwdU7jjRT/citiAJwaEf0c=; b=Rx+Kk/ySr5KDi2pGlabbEksSTr0Kdb3nLlHnIPU1MA7I3lgmq+2aOPUXNtO8RzgM2T yKpERKzJbMQYswUUSezSbAkQt4+4pqG+xRqy18R5bbdxVk1cprR7uXM+w6pPADumdR2P GIAWKJlQLogK4j2hVVLf+QVrkj8JNBq1N1nIXR8uYZKlZSFn6fmY2Zc1+M8VQ4Hm9XpC PBm358tw2bggU5lrX4/ZeUfQ/3G4jXibSkErNIeLzD/ysnsT5+3winw8ruDvVCsav730 W+Qd1Cm5v5V5Is0nT6zG0DCXxPdNzIoWjlvp1Oqgl/BY68pbSe9SC8zCi+5DHrmRmeh2 2Y6Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=F1M3MHaC; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. 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Mon, 20 Nov 2023 14:06:39 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 20 Nov 2023 14:06:39 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 3/6] s390: Make operand table indices relative to each other Date: Mon, 20 Nov 2023 15:06:32 +0100 Message-Id: <20231120140635.3642601-4-jremus@linux.ibm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120140635.3642601-1-jremus@linux.ibm.com> References: <20231120140635.3642601-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: G9XS_2-vHXhWsoo9X_xesdiB4BDaVzB_ X-Proofpoint-ORIG-GUID: G9XS_2-vHXhWsoo9X_xesdiB4BDaVzB_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-20_13,2023-11-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 phishscore=0 bulkscore=0 suspectscore=0 mlxscore=0 priorityscore=1501 mlxlogscore=660 lowpriorityscore=0 clxscore=1015 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311200098 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783092313863532346 X-GMAIL-MSGID: 1783092313863532346 This is a purely mechanical change. It allows subsequent insertions into the operands table without having to renumber all operand indices. The only differences in the resulting ELF object are in the .debug_info section. This has been confirmed by diffing the following xxd and readelf output: xxd s390-opc.o readelf -aW -x .text -x .data -x .bss -x .rodata -x .debug_info \ -x .symtab -x .strtab -x .shstrtab --debug-dump s390-opc.o opcodes/ * s390-opc.c: Make operand table indices relative to each other. Signed-off-by: Jens Remus Reviewed-by: Andreas Krebbel --- opcodes/s390-opc.c | 174 ++++++++++++++++++++++++--------------------- 1 file changed, 92 insertions(+), 82 deletions(-) diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 1910431ab89..b52fc8c3b62 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -34,76 +34,82 @@ inserting operands into instructions and vice-versa is kept in this file. */ +/* Build-time checks are preferrable over runtime ones. Use this construct + in preference where possible. */ +#define static_assert(e) ((void)sizeof (struct { int _:1 - 2 * !(e); })) + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + /* The operands table. The fields are bits, shift, insert, extract, flags. */ const struct s390_operand s390_operands[] = { -#define UNUSED 0 +#define UNUSED 0 { 0, 0, 0 }, /* Indicates the end of the operand list */ /* General purpose register operands. */ -#define R_8 1 /* GPR starting at position 8 */ +#define R_8 (UNUSED + 1) /* GPR starting at position 8 */ { 4, 8, S390_OPERAND_GPR }, -#define R_12 2 /* GPR starting at position 12 */ +#define R_12 (R_8 + 1) /* GPR starting at position 12 */ { 4, 12, S390_OPERAND_GPR }, -#define R_16 3 /* GPR starting at position 16 */ +#define R_16 (R_12 + 1) /* GPR starting at position 16 */ { 4, 16, S390_OPERAND_GPR }, -#define R_20 4 /* GPR starting at position 20 */ +#define R_20 (R_16 + 1) /* GPR starting at position 20 */ { 4, 20, S390_OPERAND_GPR }, -#define R_24 5 /* GPR starting at position 24 */ +#define R_24 (R_20 + 1) /* GPR starting at position 24 */ { 4, 24, S390_OPERAND_GPR }, -#define R_28 6 /* GPR starting at position 28 */ +#define R_28 (R_24 + 1) /* GPR starting at position 28 */ { 4, 28, S390_OPERAND_GPR }, -#define R_32 7 /* GPR starting at position 32 */ +#define R_32 (R_28 + 1) /* GPR starting at position 32 */ { 4, 32, S390_OPERAND_GPR }, /* General purpose register pair operands. */ -#define RE_8 8 /* GPR starting at position 8 */ +#define RE_8 (R_32 + 1) /* GPR starting at position 8 */ { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, -#define RE_12 9 /* GPR starting at position 12 */ +#define RE_12 (RE_8 + 1) /* GPR starting at position 12 */ { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, -#define RE_16 10 /* GPR starting at position 16 */ +#define RE_16 (RE_12 + 1) /* GPR starting at position 16 */ { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, -#define RE_20 11 /* GPR starting at position 20 */ +#define RE_20 (RE_16 + 1) /* GPR starting at position 20 */ { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, -#define RE_24 12 /* GPR starting at position 24 */ +#define RE_24 (RE_20 + 1) /* GPR starting at position 24 */ { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, -#define RE_28 13 /* GPR starting at position 28 */ +#define RE_28 (RE_24 + 1) /* GPR starting at position 28 */ { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, -#define RE_32 14 /* GPR starting at position 32 */ +#define RE_32 (RE_28 + 1) /* GPR starting at position 32 */ { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, /* Floating point register operands. */ -#define F_8 15 /* FPR starting at position 8 */ +#define F_8 (RE_32 + 1) /* FPR starting at position 8 */ { 4, 8, S390_OPERAND_FPR }, -#define F_12 16 /* FPR starting at position 12 */ +#define F_12 (F_8 + 1) /* FPR starting at position 12 */ { 4, 12, S390_OPERAND_FPR }, -#define F_16 17 /* FPR starting at position 16 */ +#define F_16 (F_12 + 1) /* FPR starting at position 16 */ { 4, 16, S390_OPERAND_FPR }, -#define F_24 18 /* FPR starting at position 24 */ +#define F_24 (F_16 + 1) /* FPR starting at position 24 */ { 4, 24, S390_OPERAND_FPR }, -#define F_28 19 /* FPR starting at position 28 */ +#define F_28 (F_24 + 1) /* FPR starting at position 28 */ { 4, 28, S390_OPERAND_FPR }, -#define F_32 20 /* FPR starting at position 32 */ +#define F_32 (F_28 + 1) /* FPR starting at position 32 */ { 4, 32, S390_OPERAND_FPR }, /* Floating point register pair operands. */ -#define FE_8 21 /* FPR starting at position 8 */ +#define FE_8 (F_32 + 1) /* FPR starting at position 8 */ { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, -#define FE_12 22 /* FPR starting at position 12 */ +#define FE_12 (FE_8 + 1) /* FPR starting at position 12 */ { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, -#define FE_16 23 /* FPR starting at position 16 */ +#define FE_16 (FE_12 + 1) /* FPR starting at position 16 */ { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, -#define FE_24 24 /* FPR starting at position 24 */ +#define FE_24 (FE_16 + 1) /* FPR starting at position 24 */ { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, -#define FE_28 25 /* FPR starting at position 28 */ +#define FE_28 (FE_24 + 1) /* FPR starting at position 28 */ { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, -#define FE_32 26 /* FPR starting at position 32 */ +#define FE_32 (FE_28 + 1) /* FPR starting at position 32 */ { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, /* Vector register operands. */ @@ -111,145 +117,149 @@ const struct s390_operand s390_operands[] = /* For each of these operands and additional bit in the RXB operand is needed. */ -#define V_8 27 /* Vector reg. starting at position 8 */ +#define V_8 (FE_32 + 1) /* Vector reg. starting at position 8 */ { 4, 8, S390_OPERAND_VR }, -#define V_12 28 /* Vector reg. starting at position 12 */ +#define V_12 (V_8 + 1) /* Vector reg. starting at position 12 */ { 4, 12, S390_OPERAND_VR }, -#define V_CP16_12 29 /* Vector reg. starting at position 12 */ +#define V_CP16_12 (V_12 + 1) /* Vector reg. starting at position 12 */ { 4, 12, S390_OPERAND_VR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ -#define V_16 30 /* Vector reg. starting at position 16 */ +#define V_16 (V_CP16_12+1) /* Vector reg. starting at position 16 */ { 4, 16, S390_OPERAND_VR }, -#define V_32 31 /* Vector reg. starting at position 32 */ +#define V_32 (V_16 + 1) /* Vector reg. starting at position 32 */ { 4, 32, S390_OPERAND_VR }, /* Access register operands. */ -#define A_8 32 /* Access reg. starting at position 8 */ +#define A_8 (V_32 + 1) /* Access reg. starting at position 8 */ { 4, 8, S390_OPERAND_AR }, -#define A_12 33 /* Access reg. starting at position 12 */ +#define A_12 (A_8 + 1) /* Access reg. starting at position 12 */ { 4, 12, S390_OPERAND_AR }, -#define A_24 34 /* Access reg. starting at position 24 */ +#define A_24 (A_12 + 1) /* Access reg. starting at position 24 */ { 4, 24, S390_OPERAND_AR }, -#define A_28 35 /* Access reg. starting at position 28 */ +#define A_28 (A_24 + 1) /* Access reg. starting at position 28 */ { 4, 28, S390_OPERAND_AR }, /* Control register operands. */ -#define C_8 36 /* Control reg. starting at position 8 */ +#define C_8 (A_28 + 1) /* Control reg. starting at position 8 */ { 4, 8, S390_OPERAND_CR }, -#define C_12 37 /* Control reg. starting at position 12 */ +#define C_12 (C_8 + 1) /* Control reg. starting at position 12 */ { 4, 12, S390_OPERAND_CR }, /* Base register operands. */ -#define B_16 38 /* Base register starting at position 16 */ +#define B_16 (C_12 + 1) /* Base register starting at position 16 */ { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR }, -#define B_32 39 /* Base register starting at position 32 */ +#define B_32 (B_16 + 1) /* Base register starting at position 32 */ { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR }, -#define X_12 40 /* Index register starting at position 12 */ +#define X_12 (B_32 + 1) /* Index register starting at position 12 */ { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR }, -#define VX_12 41 /* Vector index register starting at position 12 */ +#define VX_12 (X_12+1) /* Vector index register starting at position 12 */ { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_VR }, /* Address displacement operands. */ -#define D_20 42 /* Displacement starting at position 20 */ +#define D_20 (VX_12 + 1) /* Displacement starting at position 20 */ { 12, 20, S390_OPERAND_DISP }, -#define D_36 43 /* Displacement starting at position 36 */ +#define D_36 (D_20 + 1) /* Displacement starting at position 36 */ { 12, 36, S390_OPERAND_DISP }, -#define D20_20 44 /* 20 bit displacement starting at 20 */ +#define D20_20 (D_36 + 1) /* 20 bit displacement starting at 20 */ { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED }, /* Length operands. */ -#define L4_8 45 /* 4 bit length starting at position 8 */ +#define L4_8 (D20_20 + 1) /* 4 bit length starting at position 8 */ { 4, 8, S390_OPERAND_LENGTH }, -#define L4_12 46 /* 4 bit length starting at position 12 */ +#define L4_12 (L4_8 + 1) /* 4 bit length starting at position 12 */ { 4, 12, S390_OPERAND_LENGTH }, -#define L8_8 47 /* 8 bit length starting at position 8 */ +#define L8_8 (L4_12 + 1) /* 8 bit length starting at position 8 */ { 8, 8, S390_OPERAND_LENGTH }, /* Signed immediate operands. */ -#define I8_8 48 /* 8 bit signed value starting at 8 */ +#define I8_8 (L8_8 + 1) /* 8 bit signed value starting at 8 */ { 8, 8, S390_OPERAND_SIGNED }, -#define I8_32 49 /* 8 bit signed value starting at 32 */ +#define I8_32 (I8_8 + 1) /* 8 bit signed value starting at 32 */ { 8, 32, S390_OPERAND_SIGNED }, -#define I12_12 50 /* 12 bit signed value starting at 12 */ +#define I12_12 (I8_32 + 1) /* 12 bit signed value starting at 12 */ { 12, 12, S390_OPERAND_SIGNED }, -#define I16_16 51 /* 16 bit signed value starting at 16 */ +#define I16_16 (I12_12 + 1) /* 16 bit signed value starting at 16 */ { 16, 16, S390_OPERAND_SIGNED }, -#define I16_32 52 /* 16 bit signed value starting at 32 */ +#define I16_32 (I16_16 + 1) /* 16 bit signed value starting at 32 */ { 16, 32, S390_OPERAND_SIGNED }, -#define I24_24 53 /* 24 bit signed value starting at 24 */ +#define I24_24 (I16_32 + 1) /* 24 bit signed value starting at 24 */ { 24, 24, S390_OPERAND_SIGNED }, -#define I32_16 54 /* 32 bit signed value starting at 16 */ +#define I32_16 (I24_24 + 1) /* 32 bit signed value starting at 16 */ { 32, 16, S390_OPERAND_SIGNED }, /* Unsigned immediate operands. */ -#define U4_8 55 /* 4 bit unsigned value starting at 8 */ +#define U4_8 (I32_16 + 1) /* 4 bit unsigned value starting at 8 */ { 4, 8, 0 }, -#define U4_12 56 /* 4 bit unsigned value starting at 12 */ +#define U4_12 (U4_8 + 1) /* 4 bit unsigned value starting at 12 */ { 4, 12, 0 }, -#define U4_16 57 /* 4 bit unsigned value starting at 16 */ +#define U4_16 (U4_12 + 1) /* 4 bit unsigned value starting at 16 */ { 4, 16, 0 }, -#define U4_20 58 /* 4 bit unsigned value starting at 20 */ +#define U4_20 (U4_16 + 1) /* 4 bit unsigned value starting at 20 */ { 4, 20, 0 }, -#define U4_24 59 /* 4 bit unsigned value starting at 24 */ +#define U4_24 (U4_20 + 1) /* 4 bit unsigned value starting at 24 */ { 4, 24, 0 }, -#define U4_OR1_24 60 /* 4 bit unsigned value ORed with 1 */ +#define U4_OR1_24 (U4_24 + 1) /* 4 bit unsigned value ORed with 1 */ { 4, 24, S390_OPERAND_OR1 }, /* starting at 24 */ -#define U4_OR2_24 61 /* 4 bit unsigned value ORed with 2 */ +#define U4_OR2_24 (U4_OR1_24+1) /* 4 bit unsigned value ORed with 2 */ { 4, 24, S390_OPERAND_OR2 }, /* starting at 24 */ -#define U4_OR3_24 62 /* 4 bit unsigned value ORed with 3 */ +#define U4_OR3_24 (U4_OR2_24+1) /* 4 bit unsigned value ORed with 3 */ { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, /* starting at 24 */ -#define U4_28 63 /* 4 bit unsigned value starting at 28 */ +#define U4_28 (U4_OR3_24+1) /* 4 bit unsigned value starting at 28 */ { 4, 28, 0 }, -#define U4_OR8_28 64 /* 4 bit unsigned value ORed with 8 */ +#define U4_OR8_28 (U4_28 + 1) /* 4 bit unsigned value ORed with 8 */ { 4, 28, S390_OPERAND_OR8 }, /* starting at 28 */ -#define U4_32 65 /* 4 bit unsigned value starting at 32 */ +#define U4_32 (U4_OR8_28+1) /* 4 bit unsigned value starting at 32 */ { 4, 32, 0 }, -#define U4_36 66 /* 4 bit unsigned value starting at 36 */ +#define U4_36 (U4_32 + 1) /* 4 bit unsigned value starting at 36 */ { 4, 36, 0 }, -#define U8_8 67 /* 8 bit unsigned value starting at 8 */ +#define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */ { 8, 8, 0 }, -#define U8_16 68 /* 8 bit unsigned value starting at 16 */ +#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */ { 8, 16, 0 }, -#define U6_26 69 /* 6 bit unsigned value starting at 26 */ +#define U6_26 (U8_16 + 1) /* 6 bit unsigned value starting at 26 */ { 6, 26, 0 }, -#define U8_24 70 /* 8 bit unsigned value starting at 24 */ +#define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */ { 8, 24, 0 }, -#define U8_28 71 /* 8 bit unsigned value starting at 28 */ +#define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */ { 8, 28, 0 }, -#define U8_32 72 /* 8 bit unsigned value starting at 32 */ +#define U8_32 (U8_28 + 1) /* 8 bit unsigned value starting at 32 */ { 8, 32, 0 }, -#define U12_16 73 /* 12 bit unsigned value starting at 16 */ +#define U12_16 (U8_32 + 1) /* 12 bit unsigned value starting at 16 */ { 12, 16, 0 }, -#define U16_16 74 /* 16 bit unsigned value starting at 16 */ +#define U16_16 (U12_16 + 1) /* 16 bit unsigned value starting at 16 */ { 16, 16, 0 }, -#define U16_32 75 /* 16 bit unsigned value starting at 32 */ +#define U16_32 (U16_16 + 1) /* 16 bit unsigned value starting at 32 */ { 16, 32, 0 }, -#define U32_16 76 /* 32 bit unsigned value starting at 16 */ +#define U32_16 (U16_32 + 1) /* 32 bit unsigned value starting at 16 */ { 32, 16, 0 }, /* PC-relative address operands. */ -#define J12_12 77 /* 12 bit PC relative offset at 12 */ +#define J12_12 (U32_16 + 1) /* 12 bit PC relative offset at 12 */ { 12, 12, S390_OPERAND_PCREL }, -#define J16_16 78 /* 16 bit PC relative offset at 16 */ +#define J16_16 (J12_12 + 1) /* 16 bit PC relative offset at 16 */ { 16, 16, S390_OPERAND_PCREL }, -#define J16_32 79 /* 16 bit PC relative offset at 32 */ +#define J16_32 (J16_16 + 1) /* 16 bit PC relative offset at 32 */ { 16, 32, S390_OPERAND_PCREL }, -#define J24_24 80 /* 24 bit PC relative offset at 24 */ +#define J24_24 (J16_32 + 1) /* 24 bit PC relative offset at 24 */ { 24, 24, S390_OPERAND_PCREL }, -#define J32_16 81 /* 32 bit PC relative offset at 16 */ +#define J32_16 (J24_24 + 1) /* 32 bit PC relative offset at 16 */ { 32, 16, S390_OPERAND_PCREL }, }; +static inline void unused_s390_operands_static_asserts(void) +{ + static_assert(ARRAY_SIZE(s390_operands) - 1 == J32_16); +} /* Macros used to form opcodes. */ From patchwork Mon Nov 20 14:06:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 167163 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9910:0:b0:403:3b70:6f57 with SMTP id i16csp2226581vqn; Mon, 20 Nov 2023 06:11:28 -0800 (PST) X-Google-Smtp-Source: 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Mon, 20 Nov 2023 14:06:39 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 20 Nov 2023 14:06:39 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 4/6] s390: Align optional operand definition to specs Date: Mon, 20 Nov 2023 15:06:33 +0100 Message-Id: <20231120140635.3642601-5-jremus@linux.ibm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120140635.3642601-1-jremus@linux.ibm.com> References: <20231120140635.3642601-1-jremus@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: KL01zQoytrQJJucivJVw-cg7kTNb_8e8 X-Proofpoint-ORIG-GUID: KL01zQoytrQJJucivJVw-cg7kTNb_8e8 X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-20_13,2023-11-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 impostorscore=0 mlxlogscore=237 suspectscore=0 priorityscore=1501 spamscore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311200098 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783092465588220744 X-GMAIL-MSGID: 1783092465588220744 The IBM z/Architecture Principle of Operation [1] specifies the last operand(s) of some (extended) mnemonics to be optional. Align the mnemonic definitions in the opcode table according to specification. This changes the last operand of the following (extended) mnemonics to be optional: risbg, risbgz, risbgn, risbgnz, risbhg, risblg, rnsbg, rosbg, rxsbg Note that efpc and sfpc actually have only one operand, but had erroneously been defined to have two. For backwards compatibility the wrong RR register format must be retained. Since the superfluous second operand is defined as optional the instruction can still be coded as specified. [1]: IBM z/Architecture Principles of Operation, https://www.ibm.com/support/pages/zarchitecture-principles-operation opcodes/ * s390-opc.txt: Align optional operand definition to specification. testsuite/ * zarch-z10.s: Add test cases for risbg, risbgz, rnsbg, rosbg, and rxsbg. * zarch-z10.d: Likewise. * zarch-z196.s: Add test cases for risbhg and risblg. * zarch-z196.d: Likewise. * zarch-zEC12.s: Add test cases for risbgn and risbgnz. * zarch-zEC12.d: Likewise. Signed-off-by: Jens Remus Reviewed-by: Andreas Krebbel --- gas/testsuite/gas/s390/zarch-z10.d | 6 ++++++ gas/testsuite/gas/s390/zarch-z10.s | 6 ++++++ gas/testsuite/gas/s390/zarch-z196.d | 2 ++ gas/testsuite/gas/s390/zarch-z196.s | 2 ++ gas/testsuite/gas/s390/zarch-zEC12.d | 18 ++++++++---------- gas/testsuite/gas/s390/zarch-zEC12.s | 3 +++ opcodes/s390-opc.txt | 20 +++++++++++--------- 7 files changed, 38 insertions(+), 19 deletions(-) diff --git a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d index 2c7c485a1a1..4aca8372363 100644 --- a/gas/testsuite/gas/s390/zarch-z10.d +++ b/gas/testsuite/gas/s390/zarch-z10.d @@ -360,11 +360,17 @@ Disassembly of section .text: .*: e3 a6 75 b3 01 36 [ ]*pfd 10,5555\(%r6,%r7\) *([\da-f]+): c6 a2 00 00 00 00 [ ]*pfdrl 10,\1 .*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230 +.*: ec 67 d2 dc 00 54 [ ]*rnsbg %r6,%r7,210,220 .*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230 +.*: ec 67 d2 dc 00 57 [ ]*rxsbg %r6,%r7,210,220 .*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230 +.*: ec 67 d2 dc 00 56 [ ]*rosbg %r6,%r7,210,220 .*: ec 67 d2 14 e6 55 [ ]*risbg %r6,%r7,210,20,230 +.*: ec 67 d2 14 00 55 [ ]*risbg %r6,%r7,210,20 .*: ec 67 d2 bc e6 55 [ ]*risbgz %r6,%r7,210,60,230 +.*: ec 67 d2 bc 00 55 [ ]*risbgz %r6,%r7,210,60 .*: ec 67 d2 94 e6 55 [ ]*risbgz %r6,%r7,210,20,230 +.*: ec 67 d2 94 00 55 [ ]*risbgz %r6,%r7,210,20 *([\da-f]+): c4 6f 00 00 00 00 [ ]*strl %r6,\1 *([\da-f]+): c4 6b 00 00 00 00 [ ]*stgrl %r6,\1 *([\da-f]+): c4 67 00 00 00 00 [ ]*sthrl %r6,\1 diff --git a/gas/testsuite/gas/s390/zarch-z10.s b/gas/testsuite/gas/s390/zarch-z10.s index 5cfc533d4d1..3ed61a4f0fd 100644 --- a/gas/testsuite/gas/s390/zarch-z10.s +++ b/gas/testsuite/gas/s390/zarch-z10.s @@ -354,11 +354,17 @@ foo: pfd 10,5555(%r6,%r7) pfdrl 10,. rnsbg %r6,%r7,210,220,230 + rnsbg %r6,%r7,210,220 rxsbg %r6,%r7,210,220,230 + rxsbg %r6,%r7,210,220 rosbg %r6,%r7,210,220,230 + rosbg %r6,%r7,210,220 risbg %r6,%r7,210,20,230 + risbg %r6,%r7,210,20 risbg %r6,%r7,210,188,230 + risbg %r6,%r7,210,188 risbgz %r6,%r7,210,20,230 + risbgz %r6,%r7,210,20 strl %r6,. stgrl %r6,. sthrl %r6,. diff --git a/gas/testsuite/gas/s390/zarch-z196.d b/gas/testsuite/gas/s390/zarch-z196.d index 0f8bfeafa25..b9db65f43ee 100644 --- a/gas/testsuite/gas/s390/zarch-z196.d +++ b/gas/testsuite/gas/s390/zarch-z196.d @@ -29,7 +29,9 @@ Disassembly of section .text: .*: e3 67 8a 4d fe c2 [ ]*llch %r6,-5555\(%r7,%r8\) .*: e3 67 8a 4d fe c6 [ ]*llhh %r6,-5555\(%r7,%r8\) .*: ec 67 0c 0d 0e 5d [ ]*risbhg %r6,%r7,12,13,14 +.*: ec 67 0c 0d 00 5d [ ]*risbhg %r6,%r7,12,13 .*: ec 67 0c 0d 0e 51 [ ]*risblg %r6,%r7,12,13,14 +.*: ec 67 0c 0d 00 51 [ ]*risblg %r6,%r7,12,13 .*: e3 67 8a 4d fe c3 [ ]*stch %r6,-5555\(%r7,%r8\) .*: e3 67 8a 4d fe c7 [ ]*sthh %r6,-5555\(%r7,%r8\) .*: e3 67 8a 4d fe cb [ ]*stfh %r6,-5555\(%r7,%r8\) diff --git a/gas/testsuite/gas/s390/zarch-z196.s b/gas/testsuite/gas/s390/zarch-z196.s index 31be5a62dba..213c2a1e676 100644 --- a/gas/testsuite/gas/s390/zarch-z196.s +++ b/gas/testsuite/gas/s390/zarch-z196.s @@ -23,7 +23,9 @@ foo: llch %r6,-5555(%r7,%r8) llhh %r6,-5555(%r7,%r8) risbhg %r6,%r7,12,13,14 + risbhg %r6,%r7,12,13 risblg %r6,%r7,12,13,14 + risblg %r6,%r7,12,13 stch %r6,-5555(%r7,%r8) sthh %r6,-5555(%r7,%r8) stfh %r6,-5555(%r7,%r8) diff --git a/gas/testsuite/gas/s390/zarch-zEC12.d b/gas/testsuite/gas/s390/zarch-zEC12.d index 96bf59b9fb0..57d7becdcdf 100644 --- a/gas/testsuite/gas/s390/zarch-zEC12.d +++ b/gas/testsuite/gas/s390/zarch-zEC12.d @@ -47,8 +47,11 @@ Disassembly of section .text: .*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\) .*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\) .*: ec 67 0c 0d 0e 59 [ ]*risbgn %r6,%r7,12,13,14 +.*: ec 67 0c 0d 00 59 [ ]*risbgn %r6,%r7,12,13 .*: ec 67 0c bc 0e 59 [ ]*risbgnz %r6,%r7,12,60,14 +.*: ec 67 0c bc 00 59 [ ]*risbgnz %r6,%r7,12,60 .*: ec 67 0c 94 0e 59 [ ]*risbgnz %r6,%r7,12,20,14 +.*: ec 67 0c 94 00 59 [ ]*risbgnz %r6,%r7,12,20 .*: ed 0f 8f a0 6d aa [ ]*cdzt %f6,4000\(16,%r8\),13 .*: ed 21 8f a0 4d ab [ ]*cxzt %f4,4000\(34,%r8\),13 .*: ed 0f 8f a0 6d a8 [ ]*czdt %f6,4000\(16,%r8\),13 @@ -56,16 +59,11 @@ Disassembly of section .text: .*: b2 e8 c0 56 [ ]*ppa %r5,%r6,12 .*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9 .*: b9 8f 61 59 [ ]*crdte %r5,%r6,%r9,1 -.*: c5 a0 0c 00 00 0c [ ]*bprp 10,136 ,136 +.*: c5 a0 0c 00 00 0c [ ]*bprp 10,148 ,148 *([\da-f]+): c5 a0 00 00 00 00 [ ]*bprp 10,\1 ,\1 -[ ]*125: R_390_PLT12DBL bar\+0x1 -[ ]*127: R_390_PLT24DBL bar\+0x3 +[ ]*137: R_390_PLT12DBL bar\+0x1 +[ ]*139: R_390_PLT24DBL bar\+0x3 *([\da-f]+): c7 a0 00 00 00 00 [ ]*bpp 10,\1 ,0 -[ ]*12e: R_390_PLT16DBL bar\+0x4 +[ ]*140: R_390_PLT16DBL bar\+0x4 *([\da-f]+): c7 a0 00 00 00 00 [ ]*bpp 10,\1 ,0 -[ ]*134: R_390_PC16DBL baz\+0x4 - - -0000000000000136 : - -.*: 07 07 [ ]*nopr %r7 +[ ]*146: R_390_PC16DBL baz\+0x4 diff --git a/gas/testsuite/gas/s390/zarch-zEC12.s b/gas/testsuite/gas/s390/zarch-zEC12.s index 03b577e4830..3a30e8d72bf 100644 --- a/gas/testsuite/gas/s390/zarch-zEC12.s +++ b/gas/testsuite/gas/s390/zarch-zEC12.s @@ -44,8 +44,11 @@ foo: clgtnh %r6,-5555(%r7) risbgn %r6,%r7,12,13,14 + risbgn %r6,%r7,12,13 risbgn %r6,%r7,12,188,14 + risbgn %r6,%r7,12,188 risbgnz %r6,%r7,12,20,14 + risbgnz %r6,%r7,12,20 cdzt %f6,4000(16,%r8),13 cxzt %f4,4000(34,%r8),13 diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index b7efa813e47..9aeb2cc7ad1 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -305,6 +305,7 @@ b30d debr RRE_FF "divide short bfp" g5 esa,zarch ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch +# efpc and sfpc have only one operand; retain RR register format for compatibility b38c efpc RRE_RR "extract fpc" g5 esa,zarch optparm b342 ltxbr RRE_FEFE "load and test extended bfp" g5 esa,zarch b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch @@ -348,6 +349,7 @@ b31f msdbr RRF_F0FF "multiply and subtract long bfp" g5 esa,zarch ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch +# efpc and sfpc have only one operand; retain RR register format for compatibility b384 sfpc RRE_RR "set fpc" g5 esa,zarch optparm b299 srnm S_RD "set rounding mode" g5 esa,zarch b316 sqxbr RRE_FEFE "square root extended bfp" g5 esa,zarch @@ -966,11 +968,11 @@ c201 msfi RIL_RI "multiply single immediate (32)" z10 zarch c200 msgfi RIL_RI "multiply single immediate (64)" z10 zarch e30000000036 pfd RXY_URRD "prefetch data" z10 zarch c602 pfdrl RIL_UP "prefetch data relative long" z10 zarch -ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch -ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch -ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch -ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch -ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch +ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch optparm +ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch optparm +ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch optparm +ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch optparm +ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch optparm c40f strl RIL_RP "store relative long (32)" z10 zarch c40b stgrl RIL_RP "store relative long (64)" z10 zarch c407 sthrl RIL_RP "store halfword relative long" z10 zarch @@ -1014,8 +1016,8 @@ e300000000c4 lhh RXY_RRRD "load halfword high" z196 zarch e300000000ca lfh RXY_RRRD "load high" z196 zarch e300000000c2 llch RXY_RRRD "load logical character high" z196 zarch e300000000c6 llhh RXY_RRRD "load logical halfword high" z196 zarch -ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch -ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch +ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch optparm +ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch optparm e300000000c3 stch RXY_RRRD "store character high" z196 zarch e300000000c7 sthh RXY_RRRD "store halfword high" z196 zarch e300000000cb stfh RXY_RRRD "store high" z196 zarch @@ -1153,8 +1155,8 @@ eb0000000023 clt RSY_RURD "compare logical and trap 32 bit reg-mem" zEC12 zarch eb0000000023 clt$12 RSY_R0RD "compare logical and trap 32 bit reg-mem" zEC12 zarch eb000000002b clgt RSY_RURD "compare logical and trap 64 bit reg-mem" zEC12 zarch eb000000002b clgt$12 RSY_R0RD "compare logical and trap 64 bit reg-mem" zEC12 zarch -ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch -ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch +ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch optparm +ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch optparm ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch From patchwork Mon Nov 20 14:06:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 167159 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9910:0:b0:403:3b70:6f57 with SMTP id i16csp2223074vqn; Mon, 20 Nov 2023 06:07:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IENeff8VXWO7vfIrp4MdfQZ56G6Q0xWFuLygQz+EgK18ljz+l4s7lHu7mm92twrc1Q0UvG7 X-Received: by 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Mon, 20 Nov 2023 14:06:39 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 20 Nov 2023 14:06:39 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 5/6] s390: Add missing extended mnemonics Date: Mon, 20 Nov 2023 15:06:34 +0100 Message-Id: <20231120140635.3642601-6-jremus@linux.ibm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120140635.3642601-1-jremus@linux.ibm.com> References: <20231120140635.3642601-1-jremus@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: WMlsaff2gw86_DNVjBO431gbrG2CJvo7 X-Proofpoint-GUID: WMlsaff2gw86_DNVjBO431gbrG2CJvo7 X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-20_13,2023-11-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 mlxlogscore=652 impostorscore=0 bulkscore=0 mlxscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311200097 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783092173450111134 X-GMAIL-MSGID: 1783092199738370628 Add extended mnemonics specified in the z/Architecture Principles of Operation [1] and z/Architecture Reference Summary [2], that were previously missing from the opcode table. The following added extended mnemonics are synonyms to a base mnemonic and therefore disassemble into their base mnemonic: jc, jcth, lfi, llgfi, llghi The following added extended mnemonics are more specific than their base mnemonic and therefore disassemble into the added extended mnemonic: risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt The following added extended mnemonics are more specific than their base mnemonic, but disassemble into their base mnemonic due to design constraints: notr, notgr The missing extended mnemonic jl* conditional jump long flavors cannot be added, as they would clash with the existing non-standard extended mnemonic j* conditional jump flavors jle and jlh. The missing extended mnemonic jlc jump long conditional is not added, as the related jl* flavors cannot be added. Note that these missing jl* conditional jump long flavors are already defined as non-standard jg* flavors instead. While the related missing extended mnemonic jlc could be added as non-standard jgc instead it is forgone in favor of not adding further non-standard mnemonics. The missing extended mnemonics sllhh, sllhl, slllh, srlhh, srlhl, and srllh cannot be implemented using the current design, as they require computed operands. For that reason the following missing extended mnemonics are not added as well, as they fall into the same category of instructions that operate on high and low words of registers. They should better be added together, not to confuse the user, which of those instructions are currently implemented or not. lhhr, lhlr, llhfr, llchhr, llchlr, llclhr, llhhhr, llhhlr, llhlhr, nhhr, nhlr, nlhr, ohhr, ohlr, olhr, xhhr, xhlr, xlhr [1] IBM z/Architecture Principles of Operation, SA22-7832-13, https://www.ibm.com/support/pages/zarchitecture-principles-operation [2] IBM z/Architecture Reference Summary, SA22-7871-11, https://www.ibm.com/support/pages/zarchitecture-reference-summary opcodes/ * s390-opc.c: Define operand formats R_CP16_28, U6_18, and U5_27. Define instruction formats RIE_RRUUU3, RIE_RRUUU4, and RRF_R0RR4. * s390-opc.txt: Add extended mnemonics jc, jcth, lfi, llgfi, llghi, notgr, notr, risbhgz, risblgz, rnsbgt, rosbgt, and rxsbgt. gas/ * config/tc-s390.c: Add support to insert operand for format R_CP16_28, reusing existing logic for format V_CP16_12. * testsuite/gas/s390/esa-g5.s: Add test for extended mnemonic jc. * testsuite/gas/s390/esa-g5.d: Likewise. * testsuite/gas/s390/zarch-z900.s: Add test for extended mnemonic llghi. * testsuite/gas/s390/zarch-z900.d: Likewise. * testsuite/gas/s390/zarch-z9-109.s: Add tests for extended mnemonics lfi and llgfi. * testsuite/gas/s390/zarch-z9-109.d: Likewise. * testsuite/gas/s390/zarch-z10.s: Add tests for extended mnemonics rnsbgt, rosbgt, and rxsbgt. * testsuite/gas/s390/zarch-z10.d: Likewise. * testsuite/gas/s390/zarch-z196.s: Add tests for extended mnemonics jcth, risbhgz, and risblgz. * testsuite/gas/s390/zarch-z196.d: Likewise. * testsuite/gas/s390/zarch-arch13.s: Add tests for extended mnemonics notr and notgr. * testsuite/gas/s390/zarch-arch13.d: Likewise. Signed-off-by: Jens Remus Reviewed-by: Andreas Krebbel --- gas/config/tc-s390.c | 12 ++++++++---- gas/testsuite/gas/s390/esa-g5.d | 1 + gas/testsuite/gas/s390/esa-g5.s | 1 + gas/testsuite/gas/s390/zarch-arch13.d | 4 ++++ gas/testsuite/gas/s390/zarch-arch13.s | 4 ++++ gas/testsuite/gas/s390/zarch-z10.d | 12 ++++++++++++ gas/testsuite/gas/s390/zarch-z10.s | 12 ++++++++++++ gas/testsuite/gas/s390/zarch-z196.d | 10 +++++++++- gas/testsuite/gas/s390/zarch-z196.s | 9 +++++++++ gas/testsuite/gas/s390/zarch-z9-109.d | 2 ++ gas/testsuite/gas/s390/zarch-z9-109.s | 2 ++ gas/testsuite/gas/s390/zarch-z900.d | 5 +++-- gas/testsuite/gas/s390/zarch-z900.s | 1 + opcodes/s390-opc.c | 22 +++++++++++++++++----- opcodes/s390-opc.txt | 14 ++++++++++++++ 15 files changed, 99 insertions(+), 12 deletions(-) diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 765a9a2e6bd..d601618d9dc 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -699,13 +699,17 @@ s390_insert_operand (unsigned char *insn, if (operand->flags & S390_OPERAND_OR8) uval |= 8; - /* Duplicate the operand at bit pos 12 to 16. */ + /* Duplicate the GPR/VR operand at bit pos 12 to 16. */ if (operand->flags & S390_OPERAND_CP16) { - /* Copy VR operand at bit pos 12 to bit pos 16. */ + /* Copy GPR/VR operand at bit pos 12 to bit pos 16. */ insn[2] |= uval << 4; - /* Copy the flag in the RXB field. */ - insn[4] |= (insn[4] & 4) >> 1; + + if (operand->flags & S390_OPERAND_VR) + { + /* Copy the VR flag in the RXB field. */ + insn[4] |= (insn[4] & 4) >> 1; + } } /* Insert fragments of the operand byte for byte. */ diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d index 7422e88b127..d276af1a70d 100644 --- a/gas/testsuite/gas/s390/esa-g5.d +++ b/gas/testsuite/gas/s390/esa-g5.d @@ -80,6 +80,7 @@ Disassembly of section .text: *([\da-f]+): a7 95 00 00 [ ]*bras %r9,\1 *([\da-f]+): a7 65 00 00 [ ]*bras %r6,\1 *([\da-f]+): a7 64 00 00 [ ]*jlh \1 + *([\da-f]+): a7 64 00 00 [ ]*jlh \1 *([\da-f]+): a7 66 00 00 [ ]*brct %r6,\1 *([\da-f]+): a7 66 00 00 [ ]*brct %r6,\1 *([\da-f]+): 84 69 00 00 [ ]*brxh %r6,%r9,\1 diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s index ee3d6319b19..2901a866ec9 100644 --- a/gas/testsuite/gas/s390/esa-g5.s +++ b/gas/testsuite/gas/s390/esa-g5.s @@ -74,6 +74,7 @@ foo: bras %r9,. jas %r6,. brc 6,. + jc 6,. brct 6,. jct %r6,. brxh %r6,%r9,. diff --git a/gas/testsuite/gas/s390/zarch-arch13.d b/gas/testsuite/gas/s390/zarch-arch13.d index fecbeb548c0..3ebdd9c17f3 100644 --- a/gas/testsuite/gas/s390/zarch-arch13.d +++ b/gas/testsuite/gas/s390/zarch-arch13.d @@ -12,7 +12,11 @@ Disassembly of section .text: .*: b9 74 b0 69 [ ]*nnrk %r6,%r9,%r11 .*: b9 64 b0 69 [ ]*nngrk %r6,%r9,%r11 .*: b9 76 b0 69 [ ]*nork %r6,%r9,%r11 +.*: b9 76 70 67 [ ]*nork %r6,%r7,%r7 +.*: b9 76 70 67 [ ]*nork %r6,%r7,%r7 .*: b9 66 b0 69 [ ]*nogrk %r6,%r9,%r11 +.*: b9 66 70 67 [ ]*nogrk %r6,%r7,%r7 +.*: b9 66 70 67 [ ]*nogrk %r6,%r7,%r7 .*: b9 77 b0 69 [ ]*nxrk %r6,%r9,%r11 .*: b9 67 b0 69 [ ]*nxgrk %r6,%r9,%r11 .*: b9 75 b0 69 [ ]*ocrk %r6,%r9,%r11 diff --git a/gas/testsuite/gas/s390/zarch-arch13.s b/gas/testsuite/gas/s390/zarch-arch13.s index 9563a1b4698..a830b20b3a5 100644 --- a/gas/testsuite/gas/s390/zarch-arch13.s +++ b/gas/testsuite/gas/s390/zarch-arch13.s @@ -6,7 +6,11 @@ foo: nnrk %r6,%r9,%r11 nngrk %r6,%r9,%r11 nork %r6,%r9,%r11 + nork %r6,%r7,%r7 + notr %r6,%r7 nogrk %r6,%r9,%r11 + nogrk %r6,%r7,%r7 + notgr %r6,%r7 nxrk %r6,%r9,%r11 nxgrk %r6,%r9,%r11 ocrk %r6,%r9,%r11 diff --git a/gas/testsuite/gas/s390/zarch-z10.d b/gas/testsuite/gas/s390/zarch-z10.d index 4aca8372363..4a051533f93 100644 --- a/gas/testsuite/gas/s390/zarch-z10.d +++ b/gas/testsuite/gas/s390/zarch-z10.d @@ -361,10 +361,22 @@ Disassembly of section .text: *([\da-f]+): c6 a2 00 00 00 00 [ ]*pfdrl 10,\1 .*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230 .*: ec 67 d2 dc 00 54 [ ]*rnsbg %r6,%r7,210,220 +.*: ec 67 92 dc e6 54 [ ]*rnsbgt %r6,%r7,18,220,230 +.*: ec 67 92 dc 00 54 [ ]*rnsbgt %r6,%r7,18,220 +.*: ec 67 92 1c 26 54 [ ]*rnsbgt %r6,%r7,18,28,38 +.*: ec 67 92 1c 00 54 [ ]*rnsbgt %r6,%r7,18,28 .*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230 .*: ec 67 d2 dc 00 57 [ ]*rxsbg %r6,%r7,210,220 +.*: ec 67 92 dc e6 57 [ ]*rxsbgt %r6,%r7,18,220,230 +.*: ec 67 92 dc 00 57 [ ]*rxsbgt %r6,%r7,18,220 +.*: ec 67 92 1c 26 57 [ ]*rxsbgt %r6,%r7,18,28,38 +.*: ec 67 92 1c 00 57 [ ]*rxsbgt %r6,%r7,18,28 .*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230 .*: ec 67 d2 dc 00 56 [ ]*rosbg %r6,%r7,210,220 +.*: ec 67 92 dc e6 56 [ ]*rosbgt %r6,%r7,18,220,230 +.*: ec 67 92 dc 00 56 [ ]*rosbgt %r6,%r7,18,220 +.*: ec 67 92 1c 26 56 [ ]*rosbgt %r6,%r7,18,28,38 +.*: ec 67 92 1c 00 56 [ ]*rosbgt %r6,%r7,18,28 .*: ec 67 d2 14 e6 55 [ ]*risbg %r6,%r7,210,20,230 .*: ec 67 d2 14 00 55 [ ]*risbg %r6,%r7,210,20 .*: ec 67 d2 bc e6 55 [ ]*risbgz %r6,%r7,210,60,230 diff --git a/gas/testsuite/gas/s390/zarch-z10.s b/gas/testsuite/gas/s390/zarch-z10.s index 3ed61a4f0fd..45bb8944793 100644 --- a/gas/testsuite/gas/s390/zarch-z10.s +++ b/gas/testsuite/gas/s390/zarch-z10.s @@ -355,10 +355,22 @@ foo: pfdrl 10,. rnsbg %r6,%r7,210,220,230 rnsbg %r6,%r7,210,220 + rnsbg %r6,%r7,146,220,230 + rnsbg %r6,%r7,146,220 + rnsbgt %r6,%r7,18,28,38 + rnsbgt %r6,%r7,18,28 rxsbg %r6,%r7,210,220,230 rxsbg %r6,%r7,210,220 + rxsbg %r6,%r7,146,220,230 + rxsbg %r6,%r7,146,220 + rxsbgt %r6,%r7,18,28,38 + rxsbgt %r6,%r7,18,28 rosbg %r6,%r7,210,220,230 rosbg %r6,%r7,210,220 + rosbg %r6,%r7,146,220,230 + rosbg %r6,%r7,146,220 + rosbgt %r6,%r7,18,28,38 + rosbgt %r6,%r7,18,28 risbg %r6,%r7,210,20,230 risbg %r6,%r7,210,20 risbg %r6,%r7,210,188,230 diff --git a/gas/testsuite/gas/s390/zarch-z196.d b/gas/testsuite/gas/s390/zarch-z196.d index b9db65f43ee..ac2478d6219 100644 --- a/gas/testsuite/gas/s390/zarch-z196.d +++ b/gas/testsuite/gas/s390/zarch-z196.d @@ -14,6 +14,7 @@ Disassembly of section .text: .*: cc 6a 00 00 fd e8 [ ]*alsih %r6,65000 .*: cc 6b 00 00 fd e8 [ ]*alsihn %r6,65000 *([\da-f]+): cc 66 00 00 00 00 [ ]*brcth %r6,\1 + *([\da-f]+): cc 66 00 00 00 00 [ ]*brcth %r6,\1 .*: b9 cd 00 67 [ ]*chhr %r6,%r7 .*: b9 dd 00 67 [ ]*chlr %r6,%r7 .*: e3 67 85 b3 01 cd [ ]*chf %r6,5555\(%r7,%r8\) @@ -30,8 +31,16 @@ Disassembly of section .text: .*: e3 67 8a 4d fe c6 [ ]*llhh %r6,-5555\(%r7,%r8\) .*: ec 67 0c 0d 0e 5d [ ]*risbhg %r6,%r7,12,13,14 .*: ec 67 0c 0d 00 5d [ ]*risbhg %r6,%r7,12,13 +.*: ec 67 0c 8d 0e 5d [ ]*risbhgz %r6,%r7,12,13,14 +.*: ec 67 0c 8d 00 5d [ ]*risbhgz %r6,%r7,12,13 +.*: ec 67 0c 8d 0e 5d [ ]*risbhgz %r6,%r7,12,13,14 +.*: ec 67 0c 8d 00 5d [ ]*risbhgz %r6,%r7,12,13 .*: ec 67 0c 0d 0e 51 [ ]*risblg %r6,%r7,12,13,14 .*: ec 67 0c 0d 00 51 [ ]*risblg %r6,%r7,12,13 +.*: ec 67 0c 8d 0e 51 [ ]*risblgz %r6,%r7,12,13,14 +.*: ec 67 0c 8d 00 51 [ ]*risblgz %r6,%r7,12,13 +.*: ec 67 0c 8d 0e 51 [ ]*risblgz %r6,%r7,12,13,14 +.*: ec 67 0c 8d 00 51 [ ]*risblgz %r6,%r7,12,13 .*: e3 67 8a 4d fe c3 [ ]*stch %r6,-5555\(%r7,%r8\) .*: e3 67 8a 4d fe c7 [ ]*sthh %r6,-5555\(%r7,%r8\) .*: e3 67 8a 4d fe cb [ ]*stfh %r6,-5555\(%r7,%r8\) @@ -261,4 +270,3 @@ Disassembly of section .text: .*: b9 2c 00 00 [ ]*pcc .*: b9 2d 60 59 [ ]*kmctr %r5,%r6,%r9 .*: b9 28 00 00 [ ]*pckmo -.*: 07 07 [ ]*nopr %r7 diff --git a/gas/testsuite/gas/s390/zarch-z196.s b/gas/testsuite/gas/s390/zarch-z196.s index 213c2a1e676..bd594259532 100644 --- a/gas/testsuite/gas/s390/zarch-z196.s +++ b/gas/testsuite/gas/s390/zarch-z196.s @@ -8,6 +8,7 @@ foo: alsih %r6,65000 alsihn %r6,65000 brcth %r6,. + jcth %r6,. chhr %r6,%r7 chlr %r6,%r7 chf %r6,5555(%r7,%r8) @@ -24,8 +25,16 @@ foo: llhh %r6,-5555(%r7,%r8) risbhg %r6,%r7,12,13,14 risbhg %r6,%r7,12,13 + risbhg %r6,%r7,12,141,14 + risbhg %r6,%r7,12,141 + risbhgz %r6,%r7,12,13,14 + risbhgz %r6,%r7,12,13 risblg %r6,%r7,12,13,14 risblg %r6,%r7,12,13 + risblg %r6,%r7,12,141,14 + risblg %r6,%r7,12,141 + risblgz %r6,%r7,12,13,14 + risblgz %r6,%r7,12,13 stch %r6,-5555(%r7,%r8) sthh %r6,-5555(%r7,%r8) stfh %r6,-5555(%r7,%r8) diff --git a/gas/testsuite/gas/s390/zarch-z9-109.d b/gas/testsuite/gas/s390/zarch-z9-109.d index 5a9717c24ac..012270e733f 100644 --- a/gas/testsuite/gas/s390/zarch-z9-109.d +++ b/gas/testsuite/gas/s390/zarch-z9-109.d @@ -36,6 +36,7 @@ Disassembly of section .text: .*: b9 85 00 69 [ ]*llghr %r6,%r9 .*: c0 6e ff ff ff ff [ ]*llihf %r6,4294967295 .*: c0 6f ff ff ff ff [ ]*llilf %r6,4294967295 +.*: c0 6f ff ff ff ff [ ]*llilf %r6,4294967295 .*: c0 6c ff ff ff ff [ ]*oihf %r6,4294967295 .*: c0 6d ff ff ff ff [ ]*oilf %r6,4294967295 .*: c2 65 ff ff ff ff [ ]*slfi %r6,4294967295 @@ -70,4 +71,5 @@ Disassembly of section .text: .*: ed 95 af ff 60 38 [ ]*mayl %f6,%f9,4095\(%r5,%r10\) .*: b9 be 00 67 [ ]*srstu %r6,%r7 .*: d0 16 5f ff ad 05 [ ]*trtr 4095\(23,%r5\),3333\(%r10\) +.*: c0 69 ff ff ff ff [ ]*iilf %r6,4294967295 .*: 07 07 [ ]*nopr %r7 diff --git a/gas/testsuite/gas/s390/zarch-z9-109.s b/gas/testsuite/gas/s390/zarch-z9-109.s index 10d77ac673e..22dca84fd32 100644 --- a/gas/testsuite/gas/s390/zarch-z9-109.s +++ b/gas/testsuite/gas/s390/zarch-z9-109.s @@ -30,6 +30,7 @@ foo: llghr %r6,%r9 llihf %r6,4294967295 llilf %r6,4294967295 + llgfi %r6,4294967295 oihf %r6,4294967295 oilf %r6,4294967295 slfi %r6,4294967295 @@ -64,3 +65,4 @@ foo: mayl %f6,%f9,4095(%r5,%r10) srstu %r6,%r7 trtr 4095(23,%r5),3333(%r10) + lfi %r6,4294967295 diff --git a/gas/testsuite/gas/s390/zarch-z900.d b/gas/testsuite/gas/s390/zarch-z900.d index 93aee212785..88751711c1b 100644 --- a/gas/testsuite/gas/s390/zarch-z900.d +++ b/gas/testsuite/gas/s390/zarch-z900.d @@ -85,6 +85,7 @@ Disassembly of section .text: .*: a5 9d ff ff [ ]*llihl %r9,65535 .*: a5 9e ff ff [ ]*llilh %r9,65535 .*: a5 9f ff ff [ ]*llill %r9,65535 +.*: a5 9f ff ff [ ]*llill %r9,65535 .*: ef 96 5f ff af ff [ ]*lmd %r9,%r6,4095\(%r5\),4095\(%r10\) .*: eb 96 5f ff 00 04 [ ]*lmg %r9,%r6,4095\(%r5\) .*: eb 96 5f ff 00 96 [ ]*lmh %r9,%r6,4095\(%r5\) @@ -153,6 +154,6 @@ Disassembly of section .text: *([\da-f]+): c0 65 00 00 00 00 [ ]*brasl %r6,\1 *([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,ffffffff0+\1 *([\da-f]+): c0 65 80 00 00 00 [ ]*brasl %r6,ffffffff0+\1 -.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002d0 -.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002d6 +.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002d4 +.*: c0 65 7f ff ff ff [ ]*brasl %r6,1000002da .*: 07 07 [ ]*nopr %r7 diff --git a/gas/testsuite/gas/s390/zarch-z900.s b/gas/testsuite/gas/s390/zarch-z900.s index 22fa1da5a30..8890fbb78a0 100644 --- a/gas/testsuite/gas/s390/zarch-z900.s +++ b/gas/testsuite/gas/s390/zarch-z900.s @@ -79,6 +79,7 @@ foo: llihl %r9,65535 llilh %r9,65535 llill %r9,65535 + llghi %r9,65535 lmd %r9,%r6,4095(%r5),4095(%r10) lmg %r9,%r6,4095(%r5) lmh %r9,%r6,4095(%r5) diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index b52fc8c3b62..0427bd8b2e0 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -62,7 +62,9 @@ const struct s390_operand s390_operands[] = { 4, 24, S390_OPERAND_GPR }, #define R_28 (R_24 + 1) /* GPR starting at position 28 */ { 4, 28, S390_OPERAND_GPR }, -#define R_32 (R_28 + 1) /* GPR starting at position 32 */ +#define R_CP16_28 (R_28 + 1) /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ +#define R_32 (R_CP16_28+1) /* GPR starting at position 32 */ { 4, 32, S390_OPERAND_GPR }, /* General purpose register pair operands. */ @@ -222,9 +224,13 @@ const struct s390_operand s390_operands[] = { 4, 36, 0 }, #define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */ { 8, 8, 0 }, -#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */ +#define U6_18 (U8_8 + 1) /* 6 bit unsigned value starting at 18 */ + { 6, 18, 0 }, +#define U8_16 (U6_18 + 1) /* 8 bit unsigned value starting at 16 */ { 8, 16, 0 }, -#define U6_26 (U8_16 + 1) /* 6 bit unsigned value starting at 26 */ +#define U5_27 (U8_16 + 1) /* 5 bit unsigned value starting at 27 */ + { 5, 27, 0 }, +#define U6_26 (U5_27 + 1) /* 6 bit unsigned value starting at 26 */ { 6, 26, 0 }, #define U8_24 (U6_26 + 1) /* 8 bit unsigned value starting at 24 */ { 8, 24, 0 }, @@ -289,7 +295,7 @@ static inline void unused_s390_operands_static_asserts(void) p - pc relative r - general purpose register re - gpr extended operand, a valid general purpose register pair - u - unsigned integer, 4, 8, 16 or 32 bit + u - unsigned integer, 4, 6, 8, 16 or 32 bit m - mode field, 4 bit 0 - operand skipped. The order of the letters reflects the layout of the format in @@ -325,7 +331,9 @@ static inline void unused_s390_operands_static_asserts(void) #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ #define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */ #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ -#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */ +#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. risbgz */ +#define INSTR_RIE_RRUUU3 6, { R_8,R_12,U8_16,U5_27,U8_32,0 } /* e.g. risbhg */ +#define INSTR_RIE_RRUUU4 6, { R_8,R_12,U6_18,U8_24,U8_32,0 } /* e.g. rnsbgt */ #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ @@ -374,6 +382,7 @@ static inline void unused_s390_operands_static_asserts(void) #define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ #define INSTR_RRF_R0RER 4, { RE_24,R_28,R_16,0,0,0 } /* e.g. mgrk */ #define INSTR_RRF_R0RR3 4, { R_24,R_28,R_16,0,0,0 } /* e.g. selrz */ +#define INSTR_RRF_R0RR4 4, { R_24,R_CP16_28,0,0,0,0 } /* e.g. notr */ #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */ #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ @@ -550,6 +559,8 @@ static inline void unused_s390_operands_static_asserts(void) #define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff } +#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0xe0, 0x00, 0xff } +#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0xc0, 0x00, 0x00, 0xff } #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } @@ -598,6 +609,7 @@ static inline void unused_s390_operands_static_asserts(void) #define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_R0RER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_R0RR3 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR4 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index 9aeb2cc7ad1..674c0cf1987 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -272,6 +272,7 @@ a701 tml RI_RU "test under mask low" g5 esa,zarch 4700 nop RX_0RRD "no operation" g5 esa,zarch optparm 4700 b*8 RX_0RRD "conditional branch" g5 esa,zarch 47f0 b RX_0RRD "unconditional branch" g5 esa,zarch +a704 jc RI_UP "conditional jump" g5 esa,zarch a704 jnop RI_0P "nop jump" g5 esa,zarch a704 j*8 RI_0P "conditional jump" g5 esa,zarch a704 br*8 RI_0P "conditional jump" g5 esa,zarch @@ -473,8 +474,10 @@ eb0000000080 icmh RSE_RURD "insert characters under mask high" z900 zarch a702 tmhh RI_RU "test under mask high high" z900 zarch a703 tmhl RI_RU "test under mask high low" z900 zarch c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch +# jlc omitted due to missing jl* (see jl*8) and not added as non-standard jgc c004 jgnop RIL_0P "nop jump long" z900 esa,zarch c004 jg*8 RIL_0P "conditional jump long" z900 esa,zarch +# jl*8 omitted due to clash with non-standard j*8 flavors jle and jlh; exists as non-standard jg*8 instead c004 br*8l RIL_0P "conditional jump long" z900 esa,zarch c0f4 jg RIL_0P "unconditional jump long" z900 esa,zarch c0f4 brul RIL_0P "unconditional jump long" z900 esa,zarch @@ -523,6 +526,7 @@ a50c llihh RI_RU "load logical immediate high high" z900 zarch a50d llihl RI_RU "load logical immediate high low" z900 zarch a50e llilh RI_RU "load logical immediate low high" z900 zarch a50f llill RI_RU "load logical immediate low low" z900 zarch +a50f llghi RI_RU "load logical immediate" z900 zarch b2b1 stfl S_RD "store facility list" z900 esa,zarch b2b2 lpswe S_RD "load psw extended" z900 zarch b90d dsgr RRE_RER "divide single 64" z900 zarch @@ -750,6 +754,7 @@ c006 xihf RIL_RU "exclusive or immediate high" z9-109 zarch c007 xilf RIL_RU "exclusive or immediate low" z9-109 zarch c008 iihf RIL_RU "insert immediate high" z9-109 zarch c009 iilf RIL_RU "insert immediate low" z9-109 zarch +c009 lfi RIL_RU "insert immediate 32" z9-109 zarch # z9-109 misc instruction b983 flogr RRE_RER "find leftmost one" z9-109 zarch e30000000012 lt RXY_RRRD "load and test 32" z9-109 zarch @@ -767,6 +772,7 @@ b995 llhr RRE_RR "load logical halfword 32" z9-109 zarch b985 llghr RRE_RR "load logical halfword 64" z9-109 zarch c00e llihf RIL_RU "load logical immediate high" z9-109 zarch c00f llilf RIL_RU "load logical immediate low" z9-109 zarch +c00f llgfi RIL_RU "load logical immediate" z9-109 zarch c00c oihf RIL_RU "or immediate high" z9-109 zarch c00d oilf RIL_RU "or immediate low" z9-109 zarch c205 slfi RIL_RU "subtract logical immediate 32" z9-109 zarch @@ -969,8 +975,11 @@ c200 msgfi RIL_RI "multiply single immediate (64)" z10 zarch e30000000036 pfd RXY_URRD "prefetch data" z10 zarch c602 pfdrl RIL_UP "prefetch data relative long" z10 zarch ec0000000054 rnsbg RIE_RRUUU "rotate then and selected bits" z10 zarch optparm +ec0080000054 rnsbgt RIE_RRUUU4 "rotate then and selected bits and test results" z10 zarch optparm ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch optparm +ec0080000057 rxsbgt RIE_RRUUU4 "rotate then exclusive or selected bits and test results" z10 zarch optparm ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch optparm +ec0080000056 rosbgt RIE_RRUUU4 "rotate then or selected bits and test results" z10 zarch optparm ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch optparm ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch optparm c40f strl RIL_RP "store relative long (32)" z10 zarch @@ -1003,6 +1012,7 @@ b9da alhhlr RRF_R0RR2 "add logical high low" z196 zarch cc0a alsih RIL_RI "add logical with signed immediate high with cc" z196 zarch cc0b alsihn RIL_RI "add logical with signed immediate high no cc" z196 zarch cc06 brcth RIL_RP "branch relative on count high" z196 zarch +cc06 jcth RIL_RP "jump on count high" z196 zarch b9cd chhr RRE_RR "compare high high" z196 zarch b9dd chlr RRE_RR "compare high low" z196 zarch e300000000cd chf RXY_RRRD "compare high" z196 zarch @@ -1017,7 +1027,9 @@ e300000000ca lfh RXY_RRRD "load high" z196 zarch e300000000c2 llch RXY_RRRD "load logical character high" z196 zarch e300000000c6 llhh RXY_RRRD "load logical halfword high" z196 zarch ec000000005d risbhg RIE_RRUUU "rotate then insert selected bits high" z196 zarch optparm +ec000080005d risbhgz RIE_RRUUU3 "rotate then insert selected bits high and zero remaining bits" z196 zarch optparm ec0000000051 risblg RIE_RRUUU "rotate then insert selected bits low" z196 zarch optparm +ec0000800051 risblgz RIE_RRUUU3 "rotate then insert selected bits low and zero remaining bits" z196 zarch optparm e300000000c3 stch RXY_RRRD "store character high" z196 zarch e300000000c7 sthh RXY_RRRD "store halfword high" z196 zarch e300000000cb stfh RXY_RRRD "store high" z196 zarch @@ -1913,7 +1925,9 @@ e50a mvcrl SSE_RDRD "move right to left" arch13 zarch b974 nnrk RRF_R0RR2 "nand 32 bit" arch13 zarch b964 nngrk RRF_R0RR2 "nand 64 bit" arch13 zarch b976 nork RRF_R0RR2 "nor 32 bit" arch13 zarch +b976 notr RRF_R0RR4 "not 32 bit" arch13 zarch b966 nogrk RRF_R0RR2 "nor 64 bit" arch13 zarch +b966 notgr RRF_R0RR4 "not 64 bit" arch13 zarch b977 nxrk RRF_R0RR2 "not exclusive or 32 bit" arch13 zarch b967 nxgrk RRF_R0RR2 "not exclusive or 64 bit" arch13 zarch b975 ocrk RRF_R0RR2 "or with complement 32 bit" arch13 zarch From patchwork Mon Nov 20 14:06:35 2023 Content-Type: text/plain; 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Mon, 20 Nov 2023 14:06:40 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 20 Nov 2023 14:06:39 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 6/6] s390: Correct prno instruction name Date: Mon, 20 Nov 2023 15:06:35 +0100 Message-Id: <20231120140635.3642601-7-jremus@linux.ibm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120140635.3642601-1-jremus@linux.ibm.com> References: <20231120140635.3642601-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 8trrv7AmCCUG7GkJQBYx6LjR4TewQ8Qr X-Proofpoint-GUID: 8trrv7AmCCUG7GkJQBYx6LjR4TewQ8Qr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-20_13,2023-11-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 priorityscore=1501 mlxscore=0 adultscore=0 malwarescore=0 phishscore=0 impostorscore=0 spamscore=0 mlxlogscore=564 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311200099 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783092466313823239 X-GMAIL-MSGID: 1783092466313823239 IBM z13 (arch11) introduced ppno (Perform Pseudorandom Number Operation). IBM z14 (arch12) introduced prno (Perform Random Number Operation) and deprecated ppno. opcodes/ * s390-opc.txt: Correct prno instruction name. Signed-off-by: Jens Remus Reviewed-by: Andreas Krebbel --- opcodes/s390-opc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index 674c0cf1987..853758b96aa 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -1910,7 +1910,7 @@ e30000000049 stgsc RXY_RRRD "store guarded storage controls" arch12 zarch b929 kma RRF_R0RR "cipher message with galois counter mode" arch12 zarch -b93c prno RRE_RR "perform pseudorandom number operation" arch12 zarch +b93c prno RRE_RR "perform random number operation" arch12 zarch b9a1 tpei RRE_RR "test pending external interruption" arch12 zarch b9ac irbm RRE_RR "insert reference bits multiple" arch12 zarch