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(unknown [IPv6:240e:358:11b1:2500:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 21ADE66B3B; Sun, 19 Nov 2023 19:47:44 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v3 1/5] LoongArch: Fix usage of LSX and LASX frint/ftint instructions [PR112578] Date: Mon, 20 Nov 2023 08:47:24 +0800 Message-ID: <20231120004728.205167-2-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231120004728.205167-1-xry111@xry111.site> References: <20231120004728.205167-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=2.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783041952747240645 X-GMAIL-MSGID: 1783041952747240645 The usage LSX and LASX frint/ftint instructions had some problems: 1. These instructions raises FE_INEXACT, which is not allowed with -fno-fp-int-builtin-inexact for most C2x section F.10.6 functions (the only exceptions are rint, lrint, and llrint). 2. The "frint" instruction without explicit rounding mode is used for roundM2, this is incorrect because roundM2 is defined "rounding operand 1 to the *nearest* integer, rounding away from zero in the event of a tie". We actually don't have such an instruction. Our frintrne instruction is roundevenM2 (unfortunately, this is not documented). 3. These define_insn's are written in a way not so easy to hack. So I removed these instructions and created a "simd.md" file, then added them and the corresponding expanders there. The advantage of the simd.md file is we don't need to duplicate the RTL template twice (in lsx.md and lasx.md). gcc/ChangeLog: PR target/112578 * config/loongarch/lsx.md (UNSPEC_LSX_VFTINT_S, UNSPEC_LSX_VFTINTRNE, UNSPEC_LSX_VFTINTRP, UNSPEC_LSX_VFTINTRM, UNSPEC_LSX_VFRINTRNE_S, UNSPEC_LSX_VFRINTRNE_D, UNSPEC_LSX_VFRINTRZ_S, UNSPEC_LSX_VFRINTRZ_D, UNSPEC_LSX_VFRINTRP_S, UNSPEC_LSX_VFRINTRP_D, UNSPEC_LSX_VFRINTRM_S, UNSPEC_LSX_VFRINTRM_D): Remove. (ILSX, FLSX): Move into ... (VIMODE): Move into ... (FRINT_S, FRINT_D): Remove. (frint_pattern_s, frint_pattern_d, frint_suffix): Remove. (lsx_vfrint_, lsx_vftint_s__, lsx_vftintrne_w_s, lsx_vftintrne_l_d, lsx_vftintrp_w_s, lsx_vftintrp_l_d, lsx_vftintrm_w_s, lsx_vftintrm_l_d, lsx_vfrintrne_s, lsx_vfrintrne_d, lsx_vfrintrz_s, lsx_vfrintrz_d, lsx_vfrintrp_s, lsx_vfrintrp_d, lsx_vfrintrm_s, lsx_vfrintrm_d, v4sf2, v2df2, round2, fix_trunc2): Remove. * config/loongarch/lasx.md: Likewise. * config/loongarch/simd.md: New file. (ILSX, ILASX, FLSX, FLASX, VIMODE): ... here. (IVEC, FVEC): New mode iterators. (VIMODE): ... here. Extend it to work for all LSX/LASX vector modes. (x, wu, simd_isa, WVEC, vimode, simdfmt, simdifmt_for_f, elebits): New mode attributes. (UNSPEC_SIMD_FRINTRP, UNSPEC_SIMD_FRINTRZ, UNSPEC_SIMD_FRINT, UNSPEC_SIMD_FRINTRM, UNSPEC_SIMD_FRINTRNE): New unspecs. (SIMD_FRINT): New int iterator. (simd_frint_rounding, simd_frint_pattern): New int attributes. (_vfrint_): New define_insn template for frint instructions. (_vftint__): Likewise, but for ftint instructions. (2): New define_expand with flag_fp_int_builtin_inexact checked. (l2): Likewise. (ftrunc2): New define_expand. It does not require flag_fp_int_builtin_inexact. (fix_trunc2): New define_insn_and_split. It does not require flag_fp_int_builtin_inexact. (include): Add lsx.md and lasx.md. * config/loongarch/loongarch.md (include): Include simd.md, instead of including lsx.md and lasx.md directly. * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vftint_w_s, CODE_FOR_lsx_vftint_l_d, CODE_FOR_lasx_xvftint_w_s, CODE_FOR_lasx_xvftint_l_d): Remove. gcc/testsuite/ChangeLog: PR target/112578 * gcc.target/loongarch/vect-frint.c: New test. * gcc.target/loongarch/vect-frint-no-inexact.c: New test. * gcc.target/loongarch/vect-ftint.c: New test. * gcc.target/loongarch/vect-ftint-no-inexact.c: New test. --- gcc/config/loongarch/lasx.md | 239 ----------------- gcc/config/loongarch/loongarch-builtins.cc | 4 - gcc/config/loongarch/loongarch.md | 7 +- gcc/config/loongarch/lsx.md | 243 ------------------ gcc/config/loongarch/simd.md | 194 ++++++++++++++ .../loongarch/vect-frint-no-inexact.c | 48 ++++ .../gcc.target/loongarch/vect-frint.c | 85 ++++++ .../loongarch/vect-ftint-no-inexact.c | 44 ++++ .../gcc.target/loongarch/vect-ftint.c | 83 ++++++ 9 files changed, 456 insertions(+), 491 deletions(-) create mode 100644 gcc/config/loongarch/simd.md create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-frint-no-inexact.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-frint.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-ftint-no-inexact.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-ftint.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 2e11f061202..d4a56c307c4 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -53,7 +53,6 @@ (define_c_enum "unspec" [ UNSPEC_LASX_XVFCMP_SULT UNSPEC_LASX_XVFCMP_SUN UNSPEC_LASX_XVFCMP_SUNE - UNSPEC_LASX_XVFTINT_S UNSPEC_LASX_XVFTINT_U UNSPEC_LASX_XVCLO UNSPEC_LASX_XVSAT_S @@ -92,12 +91,6 @@ (define_c_enum "unspec" [ UNSPEC_LASX_XVEXTRINS UNSPEC_LASX_XVMSKLTZ UNSPEC_LASX_XVSIGNCOV - UNSPEC_LASX_XVFTINTRNE_W_S - UNSPEC_LASX_XVFTINTRNE_L_D - UNSPEC_LASX_XVFTINTRP_W_S - UNSPEC_LASX_XVFTINTRP_L_D - UNSPEC_LASX_XVFTINTRM_W_S - UNSPEC_LASX_XVFTINTRM_L_D UNSPEC_LASX_XVFTINT_W_D UNSPEC_LASX_XVFFINT_S_L UNSPEC_LASX_XVFTINTRZ_W_D @@ -116,14 +109,6 @@ (define_c_enum "unspec" [ UNSPEC_LASX_XVFTINTRML_L_S UNSPEC_LASX_XVFTINTRNEL_L_S UNSPEC_LASX_XVFTINTRNEH_L_S - UNSPEC_LASX_XVFRINTRNE_S - UNSPEC_LASX_XVFRINTRNE_D - UNSPEC_LASX_XVFRINTRZ_S - UNSPEC_LASX_XVFRINTRZ_D - UNSPEC_LASX_XVFRINTRP_S - UNSPEC_LASX_XVFRINTRP_D - UNSPEC_LASX_XVFRINTRM_S - UNSPEC_LASX_XVFRINTRM_D UNSPEC_LASX_XVREPLVE0_Q UNSPEC_LASX_XVPERM_W UNSPEC_LASX_XVPERMI_Q @@ -206,9 +191,6 @@ (define_mode_iterator LASX_WD [V4DI V4DF V8SI V8SF]) ;; Only used for copy256_{u,s}.w. (define_mode_iterator LASX_W [V8SI V8SF]) -;; Only integer modes in LASX. -(define_mode_iterator ILASX [V4DI V8SI V16HI V32QI]) - ;; As ILASX but excludes V32QI. (define_mode_iterator ILASX_DWH [V4DI V8SI V16HI]) @@ -224,9 +206,6 @@ (define_mode_iterator ILASX_DW [V4DI V8SI]) ;; Only integer modes smaller than a word. (define_mode_iterator ILASX_HB [V16HI V32QI]) -;; Only floating-point modes in LASX. -(define_mode_iterator FLASX [V4DF V8SF]) - ;; Only used for immediate set shuffle elements instruction. (define_mode_iterator LASX_WHB_W [V8SI V16HI V32QI V8SF]) @@ -500,37 +479,6 @@ (define_mode_attr lasxfmt_wd (V16HI "w") (V32QI "w")]) -(define_int_iterator FRINT256_S [UNSPEC_LASX_XVFRINTRP_S - UNSPEC_LASX_XVFRINTRZ_S - UNSPEC_LASX_XVFRINT - UNSPEC_LASX_XVFRINTRM_S]) - -(define_int_iterator FRINT256_D [UNSPEC_LASX_XVFRINTRP_D - UNSPEC_LASX_XVFRINTRZ_D - UNSPEC_LASX_XVFRINT - UNSPEC_LASX_XVFRINTRM_D]) - -(define_int_attr frint256_pattern_s - [(UNSPEC_LASX_XVFRINTRP_S "ceil") - (UNSPEC_LASX_XVFRINTRZ_S "btrunc") - (UNSPEC_LASX_XVFRINT "rint") - (UNSPEC_LASX_XVFRINTRM_S "floor")]) - -(define_int_attr frint256_pattern_d - [(UNSPEC_LASX_XVFRINTRP_D "ceil") - (UNSPEC_LASX_XVFRINTRZ_D "btrunc") - (UNSPEC_LASX_XVFRINT "rint") - (UNSPEC_LASX_XVFRINTRM_D "floor")]) - -(define_int_attr frint256_suffix - [(UNSPEC_LASX_XVFRINTRP_S "rp") - (UNSPEC_LASX_XVFRINTRP_D "rp") - (UNSPEC_LASX_XVFRINTRZ_S "rz") - (UNSPEC_LASX_XVFRINTRZ_D "rz") - (UNSPEC_LASX_XVFRINT "") - (UNSPEC_LASX_XVFRINTRM_S "rm") - (UNSPEC_LASX_XVFRINTRM_D "rm")]) - (define_expand "vec_init" [(match_operand:LASX 0 "register_operand") (match_operand:LASX 1 "")] @@ -1688,15 +1636,6 @@ (define_insn "lasx_xvfrecip_" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) -(define_insn "lasx_xvfrint_" - [(set (match_operand:FLASX 0 "register_operand" "=f") - (unspec:FLASX [(match_operand:FLASX 1 "register_operand" "f")] - UNSPEC_LASX_XVFRINT))] - "ISA_HAS_LASX" - "xvfrint.\t%u0,%u1" - [(set_attr "type" "simd_fcvt") - (set_attr "mode" "")]) - (define_insn "lasx_xvfrsqrt_" [(set (match_operand:FLASX 0 "register_operand" "=f") (unspec:FLASX [(match_operand:FLASX 1 "register_operand" "f")] @@ -1706,16 +1645,6 @@ (define_insn "lasx_xvfrsqrt_" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) -(define_insn "lasx_xvftint_s__" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FLASX 1 "register_operand" "f")] - UNSPEC_LASX_XVFTINT_S))] - "ISA_HAS_LASX" - "xvftint..\t%u0,%u1" - [(set_attr "type" "simd_fcvt") - (set_attr "cnv_mode" "") - (set_attr "mode" "")]) - (define_insn "lasx_xvftint_u__" [(set (match_operand: 0 "register_operand" "=f") (unspec: [(match_operand:FLASX 1 "register_operand" "f")] @@ -1726,18 +1655,6 @@ (define_insn "lasx_xvftint_u__" (set_attr "cnv_mode" "") (set_attr "mode" "")]) - - -(define_insn "fix_trunc2" - [(set (match_operand: 0 "register_operand" "=f") - (fix: (match_operand:FLASX 1 "register_operand" "f")))] - "ISA_HAS_LASX" - "xvftintrz..\t%u0,%u1" - [(set_attr "type" "simd_fcvt") - (set_attr "cnv_mode" "") - (set_attr "mode" "")]) - - (define_insn "fixuns_trunc2" [(set (match_operand: 0 "register_operand" "=f") (unsigned_fix: (match_operand:FLASX 1 "register_operand" "f")))] @@ -3245,60 +3162,6 @@ (define_insn "xvfnmadd4_nmadd4" [(set_attr "type" "simd_fmadd") (set_attr "mode" "")]) -(define_insn "lasx_xvftintrne_w_s" - [(set (match_operand:V8SI 0 "register_operand" "=f") - (unspec:V8SI [(match_operand:V8SF 1 "register_operand" "f")] - UNSPEC_LASX_XVFTINTRNE_W_S))] - "ISA_HAS_LASX" - "xvftintrne.w.s\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V8SF")]) - -(define_insn "lasx_xvftintrne_l_d" - [(set (match_operand:V4DI 0 "register_operand" "=f") - (unspec:V4DI [(match_operand:V4DF 1 "register_operand" "f")] - UNSPEC_LASX_XVFTINTRNE_L_D))] - "ISA_HAS_LASX" - "xvftintrne.l.d\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4DF")]) - -(define_insn "lasx_xvftintrp_w_s" - [(set (match_operand:V8SI 0 "register_operand" "=f") - (unspec:V8SI [(match_operand:V8SF 1 "register_operand" "f")] - UNSPEC_LASX_XVFTINTRP_W_S))] - "ISA_HAS_LASX" - "xvftintrp.w.s\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V8SF")]) - -(define_insn "lasx_xvftintrp_l_d" - [(set (match_operand:V4DI 0 "register_operand" "=f") - (unspec:V4DI [(match_operand:V4DF 1 "register_operand" "f")] - UNSPEC_LASX_XVFTINTRP_L_D))] - "ISA_HAS_LASX" - "xvftintrp.l.d\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4DF")]) - -(define_insn "lasx_xvftintrm_w_s" - [(set (match_operand:V8SI 0 "register_operand" "=f") - (unspec:V8SI [(match_operand:V8SF 1 "register_operand" "f")] - UNSPEC_LASX_XVFTINTRM_W_S))] - "ISA_HAS_LASX" - "xvftintrm.w.s\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V8SF")]) - -(define_insn "lasx_xvftintrm_l_d" - [(set (match_operand:V4DI 0 "register_operand" "=f") - (unspec:V4DI [(match_operand:V4DF 1 "register_operand" "f")] - UNSPEC_LASX_XVFTINTRM_L_D))] - "ISA_HAS_LASX" - "xvftintrm.l.d\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4DF")]) - (define_insn "lasx_xvftint_w_d" [(set (match_operand:V8SI 0 "register_operand" "=f") (unspec:V8SI [(match_operand:V4DF 1 "register_operand" "f") @@ -3467,108 +3330,6 @@ (define_insn "lasx_xvftintrnel_l_s" [(set_attr "type" "simd_shift") (set_attr "mode" "V8SF")]) -(define_insn "lasx_xvfrintrne_s" - [(set (match_operand:V8SF 0 "register_operand" "=f") - (unspec:V8SF [(match_operand:V8SF 1 "register_operand" "f")] - UNSPEC_LASX_XVFRINTRNE_S))] - "ISA_HAS_LASX" - "xvfrintrne.s\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V8SF")]) - -(define_insn "lasx_xvfrintrne_d" - [(set (match_operand:V4DF 0 "register_operand" "=f") - (unspec:V4DF [(match_operand:V4DF 1 "register_operand" "f")] - UNSPEC_LASX_XVFRINTRNE_D))] - "ISA_HAS_LASX" - "xvfrintrne.d\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4DF")]) - -(define_insn "lasx_xvfrintrz_s" - [(set (match_operand:V8SF 0 "register_operand" "=f") - (unspec:V8SF [(match_operand:V8SF 1 "register_operand" "f")] - UNSPEC_LASX_XVFRINTRZ_S))] - "ISA_HAS_LASX" - "xvfrintrz.s\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V8SF")]) - -(define_insn "lasx_xvfrintrz_d" - [(set (match_operand:V4DF 0 "register_operand" "=f") - (unspec:V4DF [(match_operand:V4DF 1 "register_operand" "f")] - UNSPEC_LASX_XVFRINTRZ_D))] - "ISA_HAS_LASX" - "xvfrintrz.d\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4DF")]) - -(define_insn "lasx_xvfrintrp_s" - [(set (match_operand:V8SF 0 "register_operand" "=f") - (unspec:V8SF [(match_operand:V8SF 1 "register_operand" "f")] - UNSPEC_LASX_XVFRINTRP_S))] - "ISA_HAS_LASX" - "xvfrintrp.s\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V8SF")]) - -(define_insn "lasx_xvfrintrp_d" - [(set (match_operand:V4DF 0 "register_operand" "=f") - (unspec:V4DF [(match_operand:V4DF 1 "register_operand" "f")] - UNSPEC_LASX_XVFRINTRP_D))] - "ISA_HAS_LASX" - "xvfrintrp.d\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4DF")]) - -(define_insn "lasx_xvfrintrm_s" - [(set (match_operand:V8SF 0 "register_operand" "=f") - (unspec:V8SF [(match_operand:V8SF 1 "register_operand" "f")] - UNSPEC_LASX_XVFRINTRM_S))] - "ISA_HAS_LASX" - "xvfrintrm.s\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V8SF")]) - -(define_insn "lasx_xvfrintrm_d" - [(set (match_operand:V4DF 0 "register_operand" "=f") - (unspec:V4DF [(match_operand:V4DF 1 "register_operand" "f")] - UNSPEC_LASX_XVFRINTRM_D))] - "ISA_HAS_LASX" - "xvfrintrm.d\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4DF")]) - -;; Vector versions of the floating-point frint patterns. -;; Expands to btrunc, ceil, floor, rint. -(define_insn "v8sf2" - [(set (match_operand:V8SF 0 "register_operand" "=f") - (unspec:V8SF [(match_operand:V8SF 1 "register_operand" "f")] - FRINT256_S))] - "ISA_HAS_LASX" - "xvfrint.s\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V8SF")]) - -(define_insn "v4df2" - [(set (match_operand:V4DF 0 "register_operand" "=f") - (unspec:V4DF [(match_operand:V4DF 1 "register_operand" "f")] - FRINT256_D))] - "ISA_HAS_LASX" - "xvfrint.d\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4DF")]) - -;; Expands to round. -(define_insn "round2" - [(set (match_operand:FLASX 0 "register_operand" "=f") - (unspec:FLASX [(match_operand:FLASX 1 "register_operand" "f")] - UNSPEC_LASX_XVFRINT))] - "ISA_HAS_LASX" - "xvfrint.\t%u0,%u1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "")]) - ;; Offset load and broadcast (define_expand "lasx_xvldrepl_" [(match_operand:LASX 0 "register_operand") diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index db02aacdc3f..cbd833aa283 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -419,8 +419,6 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lsx_vabsd_hu CODE_FOR_lsx_vabsd_u_hu #define CODE_FOR_lsx_vabsd_wu CODE_FOR_lsx_vabsd_u_wu #define CODE_FOR_lsx_vabsd_du CODE_FOR_lsx_vabsd_u_du -#define CODE_FOR_lsx_vftint_w_s CODE_FOR_lsx_vftint_s_w_s -#define CODE_FOR_lsx_vftint_l_d CODE_FOR_lsx_vftint_s_l_d #define CODE_FOR_lsx_vftint_wu_s CODE_FOR_lsx_vftint_u_wu_s #define CODE_FOR_lsx_vftint_lu_d CODE_FOR_lsx_vftint_u_lu_d #define CODE_FOR_lsx_vandn_v CODE_FOR_vandnv16qi3 @@ -725,8 +723,6 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lasx_xvssrlrn_bu_h CODE_FOR_lasx_xvssrlrn_u_bu_h #define CODE_FOR_lasx_xvssrlrn_hu_w CODE_FOR_lasx_xvssrlrn_u_hu_w #define CODE_FOR_lasx_xvssrlrn_wu_d CODE_FOR_lasx_xvssrlrn_u_wu_d -#define CODE_FOR_lasx_xvftint_w_s CODE_FOR_lasx_xvftint_s_w_s -#define CODE_FOR_lasx_xvftint_l_d CODE_FOR_lasx_xvftint_s_l_d #define CODE_FOR_lasx_xvftint_wu_s CODE_FOR_lasx_xvftint_u_wu_s #define CODE_FOR_lasx_xvftint_lu_d CODE_FOR_lasx_xvftint_u_lu_d #define CODE_FOR_lasx_xvsllwil_h_b CODE_FOR_lasx_xvsllwil_s_h_b diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index cd4ed495697..78ed63f2132 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -4026,11 +4026,8 @@ (define_peephole2 (include "generic.md") (include "la464.md") -; The LoongArch SX Instructions. -(include "lsx.md") - -; The LoongArch ASX Instructions. -(include "lasx.md") +; The LoongArch SIMD Instructions. +(include "simd.md") (define_c_enum "unspec" [ UNSPEC_ADDRESS_FIRST diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 5e8d8d74b43..c1c3719e383 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -55,7 +55,6 @@ (define_c_enum "unspec" [ UNSPEC_LSX_VFCMP_SULT UNSPEC_LSX_VFCMP_SUN UNSPEC_LSX_VFCMP_SUNE - UNSPEC_LSX_VFTINT_S UNSPEC_LSX_VFTINT_U UNSPEC_LSX_VSAT_S UNSPEC_LSX_VSAT_U @@ -89,9 +88,6 @@ (define_c_enum "unspec" [ UNSPEC_LSX_VEXTRINS UNSPEC_LSX_VMSKLTZ UNSPEC_LSX_VSIGNCOV - UNSPEC_LSX_VFTINTRNE - UNSPEC_LSX_VFTINTRP - UNSPEC_LSX_VFTINTRM UNSPEC_LSX_VFTINT_W_D UNSPEC_LSX_VFFINT_S_L UNSPEC_LSX_VFTINTRZ_W_D @@ -110,14 +106,6 @@ (define_c_enum "unspec" [ UNSPEC_LSX_VFTINTRNEL_L_S UNSPEC_LSX_VFTINTRNEH_L_S UNSPEC_LSX_VFTINTH_L_H - UNSPEC_LSX_VFRINTRNE_S - UNSPEC_LSX_VFRINTRNE_D - UNSPEC_LSX_VFRINTRZ_S - UNSPEC_LSX_VFRINTRZ_D - UNSPEC_LSX_VFRINTRP_S - UNSPEC_LSX_VFRINTRP_D - UNSPEC_LSX_VFRINTRM_S - UNSPEC_LSX_VFRINTRM_D UNSPEC_LSX_VSSRARN_S UNSPEC_LSX_VSSRARN_U UNSPEC_LSX_VSSRLN_U @@ -221,9 +209,6 @@ (define_mode_iterator LSX_D [V2DI V2DF]) ;; Only used for copy_{u,s}.w and vilvh. (define_mode_iterator LSX_W [V4SI V4SF]) -;; Only integer modes. -(define_mode_iterator ILSX [V2DI V4SI V8HI V16QI]) - ;; As ILSX but excludes V16QI. (define_mode_iterator ILSX_DWH [V2DI V4SI V8HI]) @@ -242,21 +227,9 @@ (define_mode_iterator ILSX_HB [V8HI V16QI]) ;;;; Only integer modes for fixed-point madd_q/maddr_q. ;;(define_mode_iterator ILSX_WH [V4SI V8HI]) -;; Only floating-point modes. -(define_mode_iterator FLSX [V2DF V4SF]) - ;; Only used for immediate set shuffle elements instruction. (define_mode_iterator LSX_WHB_W [V4SI V8HI V16QI V4SF]) -;; The attribute gives the integer vector mode with same size. -(define_mode_attr VIMODE - [(V2DF "V2DI") - (V4SF "V4SI") - (V2DI "V2DI") - (V4SI "V4SI") - (V8HI "V8HI") - (V16QI "V16QI")]) - ;; The attribute gives half modes for vector modes. (define_mode_attr VHMODE [(V8HI "V16QI") @@ -400,38 +373,6 @@ (define_mode_attr bitimm (V4SI "uimm5") (V2DI "uimm6")]) - -(define_int_iterator FRINT_S [UNSPEC_LSX_VFRINTRP_S - UNSPEC_LSX_VFRINTRZ_S - UNSPEC_LSX_VFRINT - UNSPEC_LSX_VFRINTRM_S]) - -(define_int_iterator FRINT_D [UNSPEC_LSX_VFRINTRP_D - UNSPEC_LSX_VFRINTRZ_D - UNSPEC_LSX_VFRINT - UNSPEC_LSX_VFRINTRM_D]) - -(define_int_attr frint_pattern_s - [(UNSPEC_LSX_VFRINTRP_S "ceil") - (UNSPEC_LSX_VFRINTRZ_S "btrunc") - (UNSPEC_LSX_VFRINT "rint") - (UNSPEC_LSX_VFRINTRM_S "floor")]) - -(define_int_attr frint_pattern_d - [(UNSPEC_LSX_VFRINTRP_D "ceil") - (UNSPEC_LSX_VFRINTRZ_D "btrunc") - (UNSPEC_LSX_VFRINT "rint") - (UNSPEC_LSX_VFRINTRM_D "floor")]) - -(define_int_attr frint_suffix - [(UNSPEC_LSX_VFRINTRP_S "rp") - (UNSPEC_LSX_VFRINTRP_D "rp") - (UNSPEC_LSX_VFRINTRZ_S "rz") - (UNSPEC_LSX_VFRINTRZ_D "rz") - (UNSPEC_LSX_VFRINT "") - (UNSPEC_LSX_VFRINTRM_S "rm") - (UNSPEC_LSX_VFRINTRM_D "rm")]) - (define_expand "vec_init" [(match_operand:LSX 0 "register_operand") (match_operand:LSX 1 "")] @@ -1616,15 +1557,6 @@ (define_insn "lsx_vfrecip_" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) -(define_insn "lsx_vfrint_" - [(set (match_operand:FLSX 0 "register_operand" "=f") - (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")] - UNSPEC_LSX_VFRINT))] - "ISA_HAS_LSX" - "vfrint.\t%w0,%w1" - [(set_attr "type" "simd_fcvt") - (set_attr "mode" "")]) - (define_insn "lsx_vfrsqrt_" [(set (match_operand:FLSX 0 "register_operand" "=f") (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")] @@ -1634,16 +1566,6 @@ (define_insn "lsx_vfrsqrt_" [(set_attr "type" "simd_fdiv") (set_attr "mode" "")]) -(define_insn "lsx_vftint_s__" - [(set (match_operand: 0 "register_operand" "=f") - (unspec: [(match_operand:FLSX 1 "register_operand" "f")] - UNSPEC_LSX_VFTINT_S))] - "ISA_HAS_LSX" - "vftint..\t%w0,%w1" - [(set_attr "type" "simd_fcvt") - (set_attr "cnv_mode" "") - (set_attr "mode" "")]) - (define_insn "lsx_vftint_u__" [(set (match_operand: 0 "register_operand" "=f") (unspec: [(match_operand:FLSX 1 "register_operand" "f")] @@ -1654,15 +1576,6 @@ (define_insn "lsx_vftint_u__" (set_attr "cnv_mode" "") (set_attr "mode" "")]) -(define_insn "fix_trunc2" - [(set (match_operand: 0 "register_operand" "=f") - (fix: (match_operand:FLSX 1 "register_operand" "f")))] - "ISA_HAS_LSX" - "vftintrz..\t%w0,%w1" - [(set_attr "type" "simd_fcvt") - (set_attr "cnv_mode" "") - (set_attr "mode" "")]) - (define_insn "fixuns_trunc2" [(set (match_operand: 0 "register_operand" "=f") (unsigned_fix: (match_operand:FLSX 1 "register_operand" "f")))] @@ -2965,60 +2878,6 @@ (define_insn "vfnmadd4_nmadd4" [(set_attr "type" "simd_fmadd") (set_attr "mode" "")]) -(define_insn "lsx_vftintrne_w_s" - [(set (match_operand:V4SI 0 "register_operand" "=f") - (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "f")] - UNSPEC_LSX_VFTINTRNE))] - "ISA_HAS_LSX" - "vftintrne.w.s\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4SF")]) - -(define_insn "lsx_vftintrne_l_d" - [(set (match_operand:V2DI 0 "register_operand" "=f") - (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "f")] - UNSPEC_LSX_VFTINTRNE))] - "ISA_HAS_LSX" - "vftintrne.l.d\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V2DF")]) - -(define_insn "lsx_vftintrp_w_s" - [(set (match_operand:V4SI 0 "register_operand" "=f") - (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "f")] - UNSPEC_LSX_VFTINTRP))] - "ISA_HAS_LSX" - "vftintrp.w.s\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4SF")]) - -(define_insn "lsx_vftintrp_l_d" - [(set (match_operand:V2DI 0 "register_operand" "=f") - (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "f")] - UNSPEC_LSX_VFTINTRP))] - "ISA_HAS_LSX" - "vftintrp.l.d\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V2DF")]) - -(define_insn "lsx_vftintrm_w_s" - [(set (match_operand:V4SI 0 "register_operand" "=f") - (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "f")] - UNSPEC_LSX_VFTINTRM))] - "ISA_HAS_LSX" - "vftintrm.w.s\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4SF")]) - -(define_insn "lsx_vftintrm_l_d" - [(set (match_operand:V2DI 0 "register_operand" "=f") - (unspec:V2DI [(match_operand:V2DF 1 "register_operand" "f")] - UNSPEC_LSX_VFTINTRM))] - "ISA_HAS_LSX" - "vftintrm.l.d\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V2DF")]) - (define_insn "lsx_vftint_w_d" [(set (match_operand:V4SI 0 "register_operand" "=f") (unspec:V4SI [(match_operand:V2DF 1 "register_operand" "f") @@ -3187,108 +3046,6 @@ (define_insn "lsx_vftintrnel_l_s" [(set_attr "type" "simd_shift") (set_attr "mode" "V4SF")]) -(define_insn "lsx_vfrintrne_s" - [(set (match_operand:V4SF 0 "register_operand" "=f") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "f")] - UNSPEC_LSX_VFRINTRNE_S))] - "ISA_HAS_LSX" - "vfrintrne.s\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4SF")]) - -(define_insn "lsx_vfrintrne_d" - [(set (match_operand:V2DF 0 "register_operand" "=f") - (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "f")] - UNSPEC_LSX_VFRINTRNE_D))] - "ISA_HAS_LSX" - "vfrintrne.d\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V2DF")]) - -(define_insn "lsx_vfrintrz_s" - [(set (match_operand:V4SF 0 "register_operand" "=f") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "f")] - UNSPEC_LSX_VFRINTRZ_S))] - "ISA_HAS_LSX" - "vfrintrz.s\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4SF")]) - -(define_insn "lsx_vfrintrz_d" - [(set (match_operand:V2DF 0 "register_operand" "=f") - (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "f")] - UNSPEC_LSX_VFRINTRZ_D))] - "ISA_HAS_LSX" - "vfrintrz.d\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V2DF")]) - -(define_insn "lsx_vfrintrp_s" - [(set (match_operand:V4SF 0 "register_operand" "=f") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "f")] - UNSPEC_LSX_VFRINTRP_S))] - "ISA_HAS_LSX" - "vfrintrp.s\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4SF")]) - -(define_insn "lsx_vfrintrp_d" - [(set (match_operand:V2DF 0 "register_operand" "=f") - (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "f")] - UNSPEC_LSX_VFRINTRP_D))] - "ISA_HAS_LSX" - "vfrintrp.d\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V2DF")]) - -(define_insn "lsx_vfrintrm_s" - [(set (match_operand:V4SF 0 "register_operand" "=f") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "f")] - UNSPEC_LSX_VFRINTRM_S))] - "ISA_HAS_LSX" - "vfrintrm.s\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4SF")]) - -(define_insn "lsx_vfrintrm_d" - [(set (match_operand:V2DF 0 "register_operand" "=f") - (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "f")] - UNSPEC_LSX_VFRINTRM_D))] - "ISA_HAS_LSX" - "vfrintrm.d\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V2DF")]) - -;; Vector versions of the floating-point frint patterns. -;; Expands to btrunc, ceil, floor, rint. -(define_insn "v4sf2" - [(set (match_operand:V4SF 0 "register_operand" "=f") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "f")] - FRINT_S))] - "ISA_HAS_LSX" - "vfrint.s\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V4SF")]) - -(define_insn "v2df2" - [(set (match_operand:V2DF 0 "register_operand" "=f") - (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "f")] - FRINT_D))] - "ISA_HAS_LSX" - "vfrint.d\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "V2DF")]) - -;; Expands to round. -(define_insn "round2" - [(set (match_operand:FLSX 0 "register_operand" "=f") - (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")] - UNSPEC_LSX_VFRINT))] - "ISA_HAS_LSX" - "vfrint.\t%w0,%w1" - [(set_attr "type" "simd_shift") - (set_attr "mode" "")]) - ;; Offset load and broadcast (define_expand "lsx_vldrepl_" [(match_operand:LSX 0 "register_operand") diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md new file mode 100644 index 00000000000..f371e201127 --- /dev/null +++ b/gcc/config/loongarch/simd.md @@ -0,0 +1,194 @@ +;; Integer modes supported by LSX. +(define_mode_iterator ILSX [V2DI V4SI V8HI V16QI]) + +;; Integer modes supported by LASX. +(define_mode_iterator ILASX [V4DI V8SI V16HI V32QI]) + +;; FP modes supported by LSX +(define_mode_iterator FLSX [V2DF V4SF]) + +;; FP modes supported by LASX +(define_mode_iterator FLASX [V4DF V8SF]) + +;; All integer modes available +(define_mode_iterator IVEC [(ILSX "ISA_HAS_LSX") (ILASX "ISA_HAS_LASX")]) + +;; All FP modes available +(define_mode_iterator FVEC [(FLSX "ISA_HAS_LSX") (FLASX "ISA_HAS_LASX")]) + +;; Mnemonic prefix, "x" for LASX modes. +(define_mode_attr x [(V2DI "") (V4SI "") (V8HI "") (V16QI "") + (V2DF "") (V4SF "") + (V4DI "x") (V8SI "x") (V16HI "x") (V32QI "x") + (V4DF "x") (V8SF "x")]) + +;; Modifier for vector register, "w" for LSX modes, "u" for LASX modes. +(define_mode_attr wu [(V2DI "w") (V4SI "w") (V8HI "w") (V16QI "w") + (V2DF "w") (V4SF "w") + (V4DI "u") (V8SI "u") (V16HI "u") (V32QI "u") + (V4DF "u") (V8SF "u")]) + +;; define_insn name prefix, "lsx" or "lasx" +(define_mode_attr simd_isa + [(V2DI "lsx") (V4SI "lsx") (V8HI "lsx") (V16QI "lsx") + (V2DF "lsx") (V4SF "lsx") + (V4DI "lasx") (V8SI "lasx") (V16HI "lasx") (V32QI "lasx") + (V4DF "lasx") (V8SF "lasx")]) + +;; Widen integer modes for intermediate values in RTX pattern. +(define_mode_attr WVEC [(V2DI "V2TI") (V4DI "V4TI") + (V4SI "V4DI") (V8SI "V8DI") + (V8HI "V8SI") (V16HI "V16SI") + (V16QI "V16HI") (V32QI "V32HI")]) + +;; Integer vector modes with the same length and unit size as a mode. +(define_mode_attr VIMODE [(V2DI "V2DI") (V4SI "V4SI") + (V8HI "V8HI") (V16QI "V16QI") + (V2DF "V2DI") (V4SF "V4SI") + (V4DI "V4DI") (V8SI "V8SI") + (V16HI "V16HI") (V32QI "V32QI") + (V4DF "V4DI") (V8SF "V8SI")]) + +;; Lower-case version. +(define_mode_attr vimode [(V2DF "v2di") (V4SF "v4si") + (V4DF "v4di") (V8SF "v8si")]) + +;; Suffix for LSX or LASX instructions. +(define_mode_attr simdfmt [(V2DF "d") (V4DF "d") + (V4SF "s") (V8SF "s") + (V2DI "d") (V4DI "d") + (V4SI "w") (V8SI "w") + (V8HI "h") (V16HI "h") + (V16QI "b") (V32QI "b")]) + +;; Suffix for integer mode in LSX or LASX instructions with FP input but +;; integer output. +(define_mode_attr simdifmt_for_f [(V2DF "l") (V4DF "l") + (V4SF "w") (V8SF "w")]) + +;; Size of vector elements in bits. +(define_mode_attr elmbits [(V2DI "64") (V4DI "64") + (V4SI "32") (V8SI "32") + (V8HI "16") (V16HI "16") + (V16QI "8") (V32QI "8")]) + +;; ======================================================================= +;; For many LASX instructions, the only difference of it from the LSX +;; counterpart is the length of vector operands. Describe these LSX/LASX +;; instruction here so we can avoid duplicating logics. +;; ======================================================================= + +;; +;; FP vector rounding instructions +;; + +(define_c_enum "unspec" + [UNSPEC_SIMD_FRINTRP + UNSPEC_SIMD_FRINTRZ + UNSPEC_SIMD_FRINT + UNSPEC_SIMD_FRINTRM + UNSPEC_SIMD_FRINTRNE]) + +(define_int_iterator SIMD_FRINT + [UNSPEC_SIMD_FRINTRP + UNSPEC_SIMD_FRINTRZ + UNSPEC_SIMD_FRINT + UNSPEC_SIMD_FRINTRM + UNSPEC_SIMD_FRINTRNE]) + +(define_int_attr simd_frint_rounding + [(UNSPEC_SIMD_FRINTRP "rp") + (UNSPEC_SIMD_FRINTRZ "rz") + (UNSPEC_SIMD_FRINT "") + (UNSPEC_SIMD_FRINTRM "rm") + (UNSPEC_SIMD_FRINTRNE "rne")]) + +;; All these, but rint, are controlled by -ffp-int-builtin-inexact. +;; Note: nearbyint is NOT allowed to raise FE_INEXACT even if +;; -ffp-int-builtin-inexact, but rint is ALLOWED to raise it even if +;; -fno-fp-int-builtin-inexact. +(define_int_attr simd_frint_pattern + [(UNSPEC_SIMD_FRINTRP "ceil") + (UNSPEC_SIMD_FRINTRZ "btrunc") + (UNSPEC_SIMD_FRINT "rint") + (UNSPEC_SIMD_FRINTRNE "roundeven") + (UNSPEC_SIMD_FRINTRM "floor")]) + +;; vfrint.{/rp/rz/rm} +(define_insn "_vfrint_" + [(set (match_operand:FVEC 0 "register_operand" "=f") + (unspec:FVEC [(match_operand:FVEC 1 "register_operand" "f")] + SIMD_FRINT))] + "" + "vfrint.\t%0,%1" + [(set_attr "type" "simd_fcvt") + (set_attr "mode" "")]) + +;; Expand the standard-named patterns to vfrint instructions if +;; raising inexact exception is allowed. + +(define_expand "2" + [(set (match_operand:FVEC 0 "register_operand" "=f") + (unspec:FVEC [(match_operand:FVEC 1 "register_operand" "f")] + SIMD_FRINT))] + " == UNSPEC_SIMD_FRINT || + flag_fp_int_builtin_inexact || + !flag_trapping_math") + +;; ftrunc is like btrunc, but it's allowed to raise inexact exception +;; even if -fno-fp-int-builtin-inexact. +(define_expand "ftrunc2" + [(set (match_operand:FVEC 0 "register_operand" "=f") + (unspec:FVEC [(match_operand:FVEC 1 "register_operand" "f")] + UNSPEC_SIMD_FRINTRZ))] + "") + +;; vftint.{/rp/rz/rm} +(define_insn + "_vftint__" + [(set (match_operand: 0 "register_operand" "=f") + (fix: + (unspec:FVEC [(match_operand:FVEC 1 "register_operand" "f")] + SIMD_FRINT)))] + "" + "vftint..\t%0,%1" + [(set_attr "type" "simd_fcvt") + (set_attr "mode" "")]) + +;; Expand the standard-named patterns to vftint instructions if +;; raising inexact exception. + +(define_expand "l2" + [(set (match_operand: 0 "register_operand" "=f") + (fix: + (unspec:FVEC [(match_operand:FVEC 1 "register_operand" "f")] + SIMD_FRINT)))] + " == UNSPEC_SIMD_FRINT || + flag_fp_int_builtin_inexact || + !flag_trapping_math") + +;; fix_trunc is allowed to raise inexact exception even if +;; -fno-fp-int-builtin-inexact. Because the middle end trys to match +;; (FIX x) and it does not know (FIX (UNSPEC_SIMD_FRINTRZ x)), we need +;; to use define_insn_and_split instead of define_expand (expanders are +;; not considered during matching). +(define_insn_and_split "fix_trunc2" + [(set (match_operand: 0 "register_operand" "=f") + (fix: (match_operand:FVEC 1 "register_operand" "f")))] + "" + "#" + "" + [(const_int 0)] + { + emit_insn (gen__vftintrz__ ( + operands[0], operands[1])); + DONE; + } + [(set_attr "type" "simd_fcvt") + (set_attr "mode" "")]) + +; The LoongArch SX Instructions. +(include "lsx.md") + +; The LoongArch ASX Instructions. +(include "lasx.md") diff --git a/gcc/testsuite/gcc.target/loongarch/vect-frint-no-inexact.c b/gcc/testsuite/gcc.target/loongarch/vect-frint-no-inexact.c new file mode 100644 index 00000000000..7bbaf1fba5a --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vect-frint-no-inexact.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabi=lp64d -mdouble-float -fno-math-errno -fno-fp-int-builtin-inexact -mlasx" } */ + +#include "vect-frint.c" + +/* ceil */ +/* { dg-final { scan-assembler "bl\t%plt\\(ceil\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(ceilf\\)" } } */ +/* { dg-final { scan-assembler-not "\tvfrintrp\.s" } } */ +/* { dg-final { scan-assembler-not "\tvfrintrp\.d" } } */ +/* { dg-final { scan-assembler-not "\txvfrintrp\.s" } } */ +/* { dg-final { scan-assembler-not "\txvfrintrp\.d" } } */ + +/* floor */ +/* { dg-final { scan-assembler "bl\t%plt\\(floor\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(floorf\\)" } } */ +/* { dg-final { scan-assembler-not "\tvfrintrm\.s" } } */ +/* { dg-final { scan-assembler-not "\tvfrintrm\.d" } } */ +/* { dg-final { scan-assembler-not "\txvfrintrm\.s" } } */ +/* { dg-final { scan-assembler-not "\txvfrintrm\.d" } } */ + +/* nearbyint + rint: Only rint is allowed */ +/* { dg-final { scan-assembler "bl\t%plt\\(nearbyint\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(nearbyintf\\)" } } */ +/* { dg-final { scan-assembler-times "\tvfrint\.s" 1 } } */ +/* { dg-final { scan-assembler-times "\tvfrint\.d" 1 } } */ +/* { dg-final { scan-assembler-times "\txvfrint\.s" 1 } } */ +/* { dg-final { scan-assembler-times "\txvfrint\.d" 1 } } */ + +/* round: we don't have a corresponding instruction */ +/* { dg-final { scan-assembler "bl\t%plt\\(round\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(roundf\\)" } } */ + +/* roundeven */ +/* { dg-final { scan-assembler "bl\t%plt\\(roundeven\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(roundevenf\\)" } } */ +/* { dg-final { scan-assembler-not "\tvfrintrne\.s" } } */ +/* { dg-final { scan-assembler-not "\tvfrintrne\.d" } } */ +/* { dg-final { scan-assembler-not "\txvfrintrne\.s" } } */ +/* { dg-final { scan-assembler-not "\txvfrintrne\.d" } } */ + +/* trunc */ +/* { dg-final { scan-assembler "bl\t%plt\\(trunc\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(truncf\\)" } } */ +/* { dg-final { scan-assembler-not "\tvfrintrz\.s" } } */ +/* { dg-final { scan-assembler-not "\tvfrintrz\.d" } } */ +/* { dg-final { scan-assembler-not "\txvfrintrz\.s" } } */ +/* { dg-final { scan-assembler-not "\txvfrintrz\.d" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vect-frint.c b/gcc/testsuite/gcc.target/loongarch/vect-frint.c new file mode 100644 index 00000000000..6bf211e7e98 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vect-frint.c @@ -0,0 +1,85 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabi=lp64d -mdouble-float -fno-math-errno -ffp-int-builtin-inexact -mlasx" } */ + +float out_x[8]; +double out_y[4]; + +float x[8]; +double y[4]; + +#define TEST(op, N, func) \ +void \ +test_##op##_##N##_##func () \ +{ \ + for (int i = 0; i < N; i++) \ + out_##op[i] = __builtin_##func (op[i]); \ +} + +TEST(x, 4, ceilf); +TEST(x, 4, floorf); +TEST(x, 4, nearbyintf); +TEST(x, 4, rintf); +TEST(x, 4, roundf); +TEST(x, 4, roundevenf); +TEST(x, 4, truncf); + +TEST(x, 8, ceilf); +TEST(x, 8, floorf); +TEST(x, 8, nearbyintf); +TEST(x, 8, rintf); +TEST(x, 8, roundf); +TEST(x, 8, roundevenf); +TEST(x, 8, truncf); + +TEST(y, 2, ceil); +TEST(y, 2, floor); +TEST(y, 2, nearbyint); +TEST(y, 2, rint); +TEST(y, 2, round); +TEST(y, 2, roundeven); +TEST(y, 2, trunc); + +TEST(y, 4, ceil); +TEST(y, 4, floor); +TEST(y, 4, nearbyint); +TEST(y, 4, rint); +TEST(y, 4, round); +TEST(y, 4, roundeven); +TEST(y, 4, trunc); + +/* ceil */ +/* { dg-final { scan-assembler "\tvfrintrp\.s" } } */ +/* { dg-final { scan-assembler "\tvfrintrp\.d" } } */ +/* { dg-final { scan-assembler "\txvfrintrp\.s" } } */ +/* { dg-final { scan-assembler "\txvfrintrp\.d" } } */ + +/* floor */ +/* { dg-final { scan-assembler "\tvfrintrm\.s" } } */ +/* { dg-final { scan-assembler "\tvfrintrm\.d" } } */ +/* { dg-final { scan-assembler "\txvfrintrm\.s" } } */ +/* { dg-final { scan-assembler "\txvfrintrm\.d" } } */ + +/* rint and nearbyint + nearbyint has been disallowed to raise FE_INEXACT for decades. */ +/* { dg-final { scan-assembler-times "\tvfrint\.s" 1 } } */ +/* { dg-final { scan-assembler-times "\tvfrint\.d" 1 } } */ +/* { dg-final { scan-assembler-times "\txvfrint\.s" 1 } } */ +/* { dg-final { scan-assembler-times "\txvfrint\.d" 1 } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(nearbyint\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(nearbyintf\\)" } } */ + +/* round: we don't have a corresponding instruction */ +/* { dg-final { scan-assembler "bl\t%plt\\(round\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(roundf\\)" } } */ + +/* roundeven */ +/* { dg-final { scan-assembler "\tvfrintrne\.s" } } */ +/* { dg-final { scan-assembler "\tvfrintrne\.d" } } */ +/* { dg-final { scan-assembler "\txvfrintrne\.s" } } */ +/* { dg-final { scan-assembler "\txvfrintrne\.d" } } */ + +/* trunc */ +/* { dg-final { scan-assembler "\tvfrintrz\.s" } } */ +/* { dg-final { scan-assembler "\tvfrintrz\.d" } } */ +/* { dg-final { scan-assembler "\txvfrintrz\.s" } } */ +/* { dg-final { scan-assembler "\txvfrintrz\.d" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vect-ftint-no-inexact.c b/gcc/testsuite/gcc.target/loongarch/vect-ftint-no-inexact.c new file mode 100644 index 00000000000..83d268099ac --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vect-ftint-no-inexact.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabi=lp64d -mdouble-float -fno-math-errno -fno-fp-int-builtin-inexact -mlasx" } */ + +#include "vect-ftint.c" + +/* ceil */ +/* { dg-final { scan-assembler "bl\t%plt\\(ceil\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(ceilf\\)" } } */ +/* { dg-final { scan-assembler-not "\tvftintrp\.w\.s" } } */ +/* { dg-final { scan-assembler-not "\tvftintrp\.l\.d" } } */ +/* { dg-final { scan-assembler-not "\txvftintrp\.w\.s" } } */ +/* { dg-final { scan-assembler-not "\txvftintrp\.l\.d" } } */ + +/* floor */ +/* { dg-final { scan-assembler "bl\t%plt\\(floor\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(floorf\\)" } } */ +/* { dg-final { scan-assembler-not "\tvftintrm\.w\.s" } } */ +/* { dg-final { scan-assembler-not "\tvftintrm\.l\.d" } } */ +/* { dg-final { scan-assembler-not "\txvftintrm\.w\.s" } } */ +/* { dg-final { scan-assembler-not "\txvftintrm\.l\.d" } } */ + +/* nearbyint + rint */ +/* { dg-final { scan-assembler "bl\t%plt\\(floor\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(floorf\\)" } } */ +/* { dg-final { scan-assembler-times "\tvftint\.w\.s" 1 } } */ +/* { dg-final { scan-assembler-times "\tvftint\.l\.d" 1 } } */ +/* { dg-final { scan-assembler-times "\txvftint\.w\.s" 1 } } */ +/* { dg-final { scan-assembler-times "\txvftint\.l\.d" 1 } } */ + +/* round: we don't have a corresponding instruction */ +/* { dg-final { scan-assembler "bl\t%plt\\(lround\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(roundf\\)" } } */ + +/* roundeven */ +/* { dg-final { scan-assembler "bl\t%plt\\(roundeven\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(roundevenf\\)" } } */ +/* { dg-final { scan-assembler-not "\tvftintrne\.w\.s" } } */ +/* { dg-final { scan-assembler-not "\tvftintrne\.l\.d" } } */ +/* { dg-final { scan-assembler-not "\txvftintrne\.w\.s" } } */ +/* { dg-final { scan-assembler-not "\txvftintrne\.l\.d" } } */ + +/* trunc: XFAIL due to PR 107723 */ +/* { dg-final { scan-assembler "bl\t%plt\\(trunc\\)" { xfail *-*-* } } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(truncf\\)" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vect-ftint.c b/gcc/testsuite/gcc.target/loongarch/vect-ftint.c new file mode 100644 index 00000000000..c4962ed1774 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vect-ftint.c @@ -0,0 +1,83 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabi=lp64d -mdouble-float -fno-math-errno -ffp-int-builtin-inexact -mlasx" } */ + +int out_x[8]; +long out_y[4]; + +float x[8]; +double y[4]; + +#define TEST(op, N, func) \ +void \ +test_##op##_##N##_##func () \ +{ \ + for (int i = 0; i < N; i++) \ + out_##op[i] = __builtin_##func (op[i]); \ +} + +TEST(x, 4, ceilf); +TEST(x, 4, floorf); +TEST(x, 4, nearbyintf); +TEST(x, 4, rintf); +TEST(x, 4, roundf); +TEST(x, 4, roundevenf); +TEST(x, 4, truncf); + +TEST(x, 8, ceilf); +TEST(x, 8, floorf); +TEST(x, 8, nearbyintf); +TEST(x, 8, rintf); +TEST(x, 8, roundf); +TEST(x, 8, roundevenf); +TEST(x, 8, truncf); + +TEST(y, 2, ceil); +TEST(y, 2, floor); +TEST(y, 2, nearbyint); +TEST(y, 2, rint); +TEST(y, 2, round); +TEST(y, 2, roundeven); +TEST(y, 2, trunc); + +TEST(y, 4, ceil); +TEST(y, 4, floor); +TEST(y, 4, nearbyint); +TEST(y, 4, rint); +TEST(y, 4, round); +TEST(y, 4, roundeven); +TEST(y, 4, trunc); + +/* ceil */ +/* { dg-final { scan-assembler "\tvftintrp\.w\.s" } } */ +/* { dg-final { scan-assembler "\tvftintrp\.l\.d" } } */ +/* { dg-final { scan-assembler "\txvftintrp\.w\.s" } } */ +/* { dg-final { scan-assembler "\txvftintrp\.l\.d" } } */ + +/* floor */ +/* { dg-final { scan-assembler "\tvftintrm\.w\.s" } } */ +/* { dg-final { scan-assembler "\tvftintrm\.l\.d" } } */ +/* { dg-final { scan-assembler "\txvftintrm\.w\.s" } } */ +/* { dg-final { scan-assembler "\txvftintrm\.l\.d" } } */ + +/* rint and nearbyint + nearbyint has been disallowed to raise FE_INEXACT for decades. */ +/* { dg-final { scan-assembler-times "\tvftint\.w\.s" 1 } } */ +/* { dg-final { scan-assembler-times "\tvftint\.l\.d" 1 } } */ +/* { dg-final { scan-assembler-times "\txvftint\.w\.s" 1 } } */ +/* { dg-final { scan-assembler-times "\txvftint\.l\.d" 1 } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(nearbyint\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(nearbyintf\\)" } } */ + +/* round: we don't have a corresponding instruction */ +/* { dg-final { scan-assembler "bl\t%plt\\(lround\\)" } } */ +/* { dg-final { scan-assembler "bl\t%plt\\(roundf\\)" } } */ + +/* roundeven */ +/* { dg-final { scan-assembler "\tvftintrne\.w\.s" } } */ +/* { dg-final { scan-assembler "\tvftintrne\.l\.d" } } */ +/* { dg-final { scan-assembler "\txvftintrne\.w\.s" } } */ +/* { dg-final { scan-assembler "\txvftintrne\.l\.d" } } */ + +/* trunc */ +/* { dg-final { scan-assembler-not "bl\t%plt\\(trunc\\)" } } */ +/* { dg-final { scan-assembler-not "bl\t%plt\\(truncf\\)" } } */ From patchwork Mon Nov 20 00:47:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 166911 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9910:0:b0:403:3b70:6f57 with SMTP id i16csp1908943vqn; Sun, 19 Nov 2023 16:48:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IFzK5zUAq6KWXKicgchKYu9+/sxLTpeFUW7OnQ6WvAB+jWSx3V769j2hakxBMcLUzb3qpYA X-Received: by 2002:a81:8d11:0:b0:5c9:86c:216c with SMTP id d17-20020a818d11000000b005c9086c216cmr5541591ywg.46.1700441318504; Sun, 19 Nov 2023 16:48:38 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1700441318; cv=pass; d=google.com; s=arc-20160816; b=ELuT6kK6B7kX39p1ssZsg9SwoMZ4vR/NTq3kO4W2FK/GpGwQh/7yfbgX77rAR0+Y4p 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(unknown [IPv6:240e:358:11b1:2500:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id E829266C08; Sun, 19 Nov 2023 19:47:50 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v3 2/5] LoongArch: Use standard pattern name and RTX code for LSX/LASX muh instructions Date: Mon, 20 Nov 2023 08:47:25 +0800 Message-ID: <20231120004728.205167-3-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231120004728.205167-1-xry111@xry111.site> References: <20231120004728.205167-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783041956381773381 X-GMAIL-MSGID: 1783041956381773381 Removes unnecessary UNSPECs and make the muh instructions useful with GNU vectors or auto vectorization. gcc/ChangeLog: * config/loongarch/simd.md (muh): New code attribute mapping any_extend to smul_highpart or umul_highpart. (mul3_highpart): New define_insn. * config/loongarch/lsx.md (UNSPEC_LSX_VMUH_S): Remove. (UNSPEC_LSX_VMUH_U): Remove. (lsx_vmuh_s_): Remove. (lsx_vmuh_u_): Remove. * config/loongarch/lasx.md (UNSPEC_LASX_XVMUH_S): Remove. (UNSPEC_LASX_XVMUH_U): Remove. (lasx_xvmuh_s_): Remove. (lasx_xvmuh_u_): Remove. * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vmuh_b): Redefine to standard pattern name. (CODE_FOR_lsx_vmuh_h): Likewise. (CODE_FOR_lsx_vmuh_w): Likewise. (CODE_FOR_lsx_vmuh_d): Likewise. (CODE_FOR_lsx_vmuh_bu): Likewise. (CODE_FOR_lsx_vmuh_hu): Likewise. (CODE_FOR_lsx_vmuh_wu): Likewise. (CODE_FOR_lsx_vmuh_du): Likewise. (CODE_FOR_lasx_xvmuh_b): Likewise. (CODE_FOR_lasx_xvmuh_h): Likewise. (CODE_FOR_lasx_xvmuh_w): Likewise. (CODE_FOR_lasx_xvmuh_d): Likewise. (CODE_FOR_lasx_xvmuh_bu): Likewise. (CODE_FOR_lasx_xvmuh_hu): Likewise. (CODE_FOR_lasx_xvmuh_wu): Likewise. (CODE_FOR_lasx_xvmuh_du): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vect-muh.c: New test. --- gcc/config/loongarch/lasx.md | 22 ------------ gcc/config/loongarch/loongarch-builtins.cc | 32 ++++++++--------- gcc/config/loongarch/lsx.md | 22 ------------ gcc/config/loongarch/simd.md | 16 +++++++++ gcc/testsuite/gcc.target/loongarch/vect-muh.c | 36 +++++++++++++++++++ 5 files changed, 68 insertions(+), 60 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-muh.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index d4a56c307c4..023a023b44e 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -68,8 +68,6 @@ (define_c_enum "unspec" [ UNSPEC_LASX_BRANCH UNSPEC_LASX_BRANCH_V - UNSPEC_LASX_XVMUH_S - UNSPEC_LASX_XVMUH_U UNSPEC_LASX_MXVEXTW_U UNSPEC_LASX_XVSLLWIL_S UNSPEC_LASX_XVSLLWIL_U @@ -2823,26 +2821,6 @@ (define_insn "neg2" [(set_attr "type" "simd_logic") (set_attr "mode" "")]) -(define_insn "lasx_xvmuh_s_" - [(set (match_operand:ILASX 0 "register_operand" "=f") - (unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f") - (match_operand:ILASX 2 "register_operand" "f")] - UNSPEC_LASX_XVMUH_S))] - "ISA_HAS_LASX" - "xvmuh.\t%u0,%u1,%u2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - -(define_insn "lasx_xvmuh_u_" - [(set (match_operand:ILASX 0 "register_operand" "=f") - (unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f") - (match_operand:ILASX 2 "register_operand" "f")] - UNSPEC_LASX_XVMUH_U))] - "ISA_HAS_LASX" - "xvmuh.\t%u0,%u1,%u2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - (define_insn "lasx_xvsllwil_s__" [(set (match_operand: 0 "register_operand" "=f") (unspec: [(match_operand:ILASX_WHB 1 "register_operand" "f") diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index cbd833aa283..a6fcc1c731e 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -319,6 +319,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lsx_vmod_hu CODE_FOR_umodv8hi3 #define CODE_FOR_lsx_vmod_wu CODE_FOR_umodv4si3 #define CODE_FOR_lsx_vmod_du CODE_FOR_umodv2di3 +#define CODE_FOR_lsx_vmuh_b CODE_FOR_smulv16qi3_highpart +#define CODE_FOR_lsx_vmuh_h CODE_FOR_smulv8hi3_highpart +#define CODE_FOR_lsx_vmuh_w CODE_FOR_smulv4si3_highpart +#define CODE_FOR_lsx_vmuh_d CODE_FOR_smulv2di3_highpart +#define CODE_FOR_lsx_vmuh_bu CODE_FOR_umulv16qi3_highpart +#define CODE_FOR_lsx_vmuh_hu CODE_FOR_umulv8hi3_highpart +#define CODE_FOR_lsx_vmuh_wu CODE_FOR_umulv4si3_highpart +#define CODE_FOR_lsx_vmuh_du CODE_FOR_umulv2di3_highpart #define CODE_FOR_lsx_vmul_b CODE_FOR_mulv16qi3 #define CODE_FOR_lsx_vmul_h CODE_FOR_mulv8hi3 #define CODE_FOR_lsx_vmul_w CODE_FOR_mulv4si3 @@ -439,14 +447,6 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lsx_vfnmsub_s CODE_FOR_vfnmsubv4sf4_nmsub4 #define CODE_FOR_lsx_vfnmsub_d CODE_FOR_vfnmsubv2df4_nmsub4 -#define CODE_FOR_lsx_vmuh_b CODE_FOR_lsx_vmuh_s_b -#define CODE_FOR_lsx_vmuh_h CODE_FOR_lsx_vmuh_s_h -#define CODE_FOR_lsx_vmuh_w CODE_FOR_lsx_vmuh_s_w -#define CODE_FOR_lsx_vmuh_d CODE_FOR_lsx_vmuh_s_d -#define CODE_FOR_lsx_vmuh_bu CODE_FOR_lsx_vmuh_u_bu -#define CODE_FOR_lsx_vmuh_hu CODE_FOR_lsx_vmuh_u_hu -#define CODE_FOR_lsx_vmuh_wu CODE_FOR_lsx_vmuh_u_wu -#define CODE_FOR_lsx_vmuh_du CODE_FOR_lsx_vmuh_u_du #define CODE_FOR_lsx_vsllwil_h_b CODE_FOR_lsx_vsllwil_s_h_b #define CODE_FOR_lsx_vsllwil_w_h CODE_FOR_lsx_vsllwil_s_w_h #define CODE_FOR_lsx_vsllwil_d_w CODE_FOR_lsx_vsllwil_s_d_w @@ -588,6 +588,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lasx_xvmul_h CODE_FOR_mulv16hi3 #define CODE_FOR_lasx_xvmul_w CODE_FOR_mulv8si3 #define CODE_FOR_lasx_xvmul_d CODE_FOR_mulv4di3 +#define CODE_FOR_lasx_xvmuh_b CODE_FOR_smulv32qi3_highpart +#define CODE_FOR_lasx_xvmuh_h CODE_FOR_smulv16hi3_highpart +#define CODE_FOR_lasx_xvmuh_w CODE_FOR_smulv8si3_highpart +#define CODE_FOR_lasx_xvmuh_d CODE_FOR_smulv4di3_highpart +#define CODE_FOR_lasx_xvmuh_bu CODE_FOR_umulv32qi3_highpart +#define CODE_FOR_lasx_xvmuh_hu CODE_FOR_umulv16hi3_highpart +#define CODE_FOR_lasx_xvmuh_wu CODE_FOR_umulv8si3_highpart +#define CODE_FOR_lasx_xvmuh_du CODE_FOR_umulv4di3_highpart #define CODE_FOR_lasx_xvclz_b CODE_FOR_clzv32qi2 #define CODE_FOR_lasx_xvclz_h CODE_FOR_clzv16hi2 #define CODE_FOR_lasx_xvclz_w CODE_FOR_clzv8si2 @@ -697,14 +705,6 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lasx_xvavgr_hu CODE_FOR_lasx_xvavgr_u_hu #define CODE_FOR_lasx_xvavgr_wu CODE_FOR_lasx_xvavgr_u_wu #define CODE_FOR_lasx_xvavgr_du CODE_FOR_lasx_xvavgr_u_du -#define CODE_FOR_lasx_xvmuh_b CODE_FOR_lasx_xvmuh_s_b -#define CODE_FOR_lasx_xvmuh_h CODE_FOR_lasx_xvmuh_s_h -#define CODE_FOR_lasx_xvmuh_w CODE_FOR_lasx_xvmuh_s_w -#define CODE_FOR_lasx_xvmuh_d CODE_FOR_lasx_xvmuh_s_d -#define CODE_FOR_lasx_xvmuh_bu CODE_FOR_lasx_xvmuh_u_bu -#define CODE_FOR_lasx_xvmuh_hu CODE_FOR_lasx_xvmuh_u_hu -#define CODE_FOR_lasx_xvmuh_wu CODE_FOR_lasx_xvmuh_u_wu -#define CODE_FOR_lasx_xvmuh_du CODE_FOR_lasx_xvmuh_u_du #define CODE_FOR_lasx_xvssran_b_h CODE_FOR_lasx_xvssran_s_b_h #define CODE_FOR_lasx_xvssran_h_w CODE_FOR_lasx_xvssran_s_h_w #define CODE_FOR_lasx_xvssran_w_d CODE_FOR_lasx_xvssran_s_w_d diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index c1c3719e383..537afaf9625 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -64,8 +64,6 @@ (define_c_enum "unspec" [ UNSPEC_LSX_VSRLR UNSPEC_LSX_VSRLRI UNSPEC_LSX_VSHUF - UNSPEC_LSX_VMUH_S - UNSPEC_LSX_VMUH_U UNSPEC_LSX_VEXTW_S UNSPEC_LSX_VEXTW_U UNSPEC_LSX_VSLLWIL_S @@ -2506,26 +2504,6 @@ (define_insn "vneg2" [(set_attr "type" "simd_logic") (set_attr "mode" "")]) -(define_insn "lsx_vmuh_s_" - [(set (match_operand:ILSX 0 "register_operand" "=f") - (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f") - (match_operand:ILSX 2 "register_operand" "f")] - UNSPEC_LSX_VMUH_S))] - "ISA_HAS_LSX" - "vmuh.\t%w0,%w1,%w2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - -(define_insn "lsx_vmuh_u_" - [(set (match_operand:ILSX 0 "register_operand" "=f") - (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f") - (match_operand:ILSX 2 "register_operand" "f")] - UNSPEC_LSX_VMUH_U))] - "ISA_HAS_LSX" - "vmuh.\t%w0,%w1,%w2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - (define_insn "lsx_vextw_s_d" [(set (match_operand:V2DI 0 "register_operand" "=f") (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "f")] diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index f371e201127..79324183233 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -187,6 +187,22 @@ (define_insn_and_split "fix_trunc2" [(set_attr "type" "simd_fcvt") (set_attr "mode" "")]) +;; vmuh.{b/h/w/d} + +(define_code_attr muh + [(sign_extend "smul_highpart") + (zero_extend "umul_highpart")]) + +(define_insn "mul3_highpart" + [(set (match_operand:IVEC 0 "register_operand" "=f") + (:IVEC (match_operand:IVEC 1 "register_operand" "f") + (match_operand:IVEC 2 "register_operand" "f"))) + (any_extend (const_int 0))] + "" + "vmuh.\t%0,%1,%2" + [(set_attr "type" "simd_int_arith") + (set_attr "mode" "")]) + ; The LoongArch SX Instructions. (include "lsx.md") diff --git a/gcc/testsuite/gcc.target/loongarch/vect-muh.c b/gcc/testsuite/gcc.target/loongarch/vect-muh.c new file mode 100644 index 00000000000..a788840b23c --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vect-muh.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-mlasx -O3" } */ +/* { dg-final { scan-assembler "\tvmuh\.w\t" } } */ +/* { dg-final { scan-assembler "\tvmuh\.wu\t" } } */ +/* { dg-final { scan-assembler "\txvmuh\.w\t" } } */ +/* { dg-final { scan-assembler "\txvmuh\.wu\t" } } */ + +int a[8], b[8], c[8]; + +void +test1 (void) +{ + for (int i = 0; i < 4; i++) + c[i] = ((long)a[i] * (long)b[i]) >> 32; +} + +void +test2 (void) +{ + for (int i = 0; i < 4; i++) + c[i] = ((long)(unsigned)a[i] * (long)(unsigned)b[i]) >> 32; +} + +void +test3 (void) +{ + for (int i = 0; i < 8; i++) + c[i] = ((long)a[i] * (long)b[i]) >> 32; +} + +void +test4 (void) +{ + for (int i = 0; i < 8; i++) + c[i] = ((long)(unsigned)a[i] * (long)(unsigned)b[i]) >> 32; +} From patchwork Mon Nov 20 00:47:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 166912 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9910:0:b0:403:3b70:6f57 with SMTP id i16csp1908985vqn; Sun, 19 Nov 2023 16:48:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IH8mD2FviQiJXOfMMwxLQcUP7rmxNH62G8QzNNjj+qr1jHD3rGrDkj29initPsG7F65NTSU X-Received: by 2002:a05:620a:3dd:b0:77b:d625:6019 with SMTP id r29-20020a05620a03dd00b0077bd6256019mr6301447qkm.36.1700441327572; Sun, 19 Nov 2023 16:48:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1700441327; cv=pass; d=google.com; s=arc-20160816; b=y2Rz9UX1NTXU+5R3A10hnoVlJ5RssP88XkMZaiN8EUWS4BXGr8Foex7pivQqWtjd9/ ryuOvrJxvgNhwLAy9anZIrJh3V+csGJxICVq2fVHIWxjaDGnsPDG7iCS7ZQ0zNXHCUcA rv+76hiXZHu2O2hIawAqzqOCnCSim/V5I4iO1L6sqVZuHs5HEpF60T/3n2cyyRSk8nUk kdkARaRoILyfMQxZl928vsZHoEnSDRpcAIQjBZyzP34RQ6YFnps0Xb4GoZ7TXbi/kDjI 1Du913eIC/x8m7XCeZu1+OG+TAtKCZH76FMLi0MYmPLSoWsaQVqJRO8zDnIO0WxCTThi kdwQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=36gxlokB0dZl+oKaeV3k0fvEAhi8YIlvyfQXLXYhO0E=; fh=oUCfM/eMlWtMCtZZKY1bglzxCo7b3kw9D5LTFFWuz38=; b=kB4wjO6Rx6zX5yrAo6jaS94QhEcf9gguHYDsLaQ1H8RS26X1QYOlxzPab5Nxm5kk4C fAio0EYBetB9x2sZjLPUUhGYKrRcrmGmK9frkOIxmdVpsyW8xxDyadM/mJCxRqzM7YTt s+No3mPMDCbTPLWOh7wyPa1IFoVbJNIHvUspotiBGfpFrEy2YJ1kwulQ8xv3XwBuRLit zNp37JUYT8tHt6Q5DIz7cXXJ12In4aggNoM38MEH9Ykt9LoguG3vnGiqisjT+e/IEZ3o /4s85+iJ39D8L/lHCfWxUKuJo2clOTKg9c8KR8hvVPo6m+0PkdfwRLkeS+823/VWoIqO DMQQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@xry111.site header.s=default header.b="Lzy/G5wO"; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=xry111.site Received: from server2.sourceware.org (server2.sourceware.org. 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(unknown [IPv6:240e:358:11b1:2500:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id BAA5266B39; Sun, 19 Nov 2023 19:47:55 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v3 3/5] LoongArch: Use standard pattern name and RTX code for LSX/LASX rotate shift Date: Mon, 20 Nov 2023 08:47:26 +0800 Message-ID: <20231120004728.205167-4-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231120004728.205167-1-xry111@xry111.site> References: <20231120004728.205167-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783041965320572055 X-GMAIL-MSGID: 1783041965320572055 Remove unnecessary UNSPECs and make the [x]vrotr[i] instructions useful with GNU vectors and auto vectorization. gcc/ChangeLog: * config/loongarch/lsx.md (bitimm): Move to ... (UNSPEC_LSX_VROTR): Remove. (lsx_vrotr_): Remove. (lsx_vrotri_): Remove. * config/loongarch/lasx.md (UNSPEC_LASX_XVROTR): Remove. (lsx_vrotr_): Remove. (lsx_vrotri_): Remove. * config/loongarch/simd.md (bitimm): ... here. Expand it to cover LASX modes. (vrotr3): New define_insn. (vrotri3): New define_insn. * config/loongarch/loongarch-builtins.cc: (CODE_FOR_lsx_vrotr_b): Use standard pattern name. (CODE_FOR_lsx_vrotr_h): Likewise. (CODE_FOR_lsx_vrotr_w): Likewise. (CODE_FOR_lsx_vrotr_d): Likewise. (CODE_FOR_lasx_xvrotr_b): Likewise. (CODE_FOR_lasx_xvrotr_h): Likewise. (CODE_FOR_lasx_xvrotr_w): Likewise. (CODE_FOR_lasx_xvrotr_d): Likewise. (CODE_FOR_lsx_vrotri_b): Define to standard pattern name. (CODE_FOR_lsx_vrotri_h): Likewise. (CODE_FOR_lsx_vrotri_w): Likewise. (CODE_FOR_lsx_vrotri_d): Likewise. (CODE_FOR_lasx_xvrotri_b): Likewise. (CODE_FOR_lasx_xvrotri_h): Likewise. (CODE_FOR_lasx_xvrotri_w): Likewise. (CODE_FOR_lasx_xvrotri_d): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vect-rotr.c: New test. --- gcc/config/loongarch/lasx.md | 22 ------------ gcc/config/loongarch/loongarch-builtins.cc | 16 +++++++++ gcc/config/loongarch/lsx.md | 28 --------------- gcc/config/loongarch/simd.md | 29 +++++++++++++++ .../gcc.target/loongarch/vect-rotr.c | 36 +++++++++++++++++++ 5 files changed, 81 insertions(+), 50 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-rotr.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 023a023b44e..116b30c0774 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -138,7 +138,6 @@ (define_c_enum "unspec" [ UNSPEC_LASX_XVHSUBW_Q_D UNSPEC_LASX_XVHADDW_QU_DU UNSPEC_LASX_XVHSUBW_QU_DU - UNSPEC_LASX_XVROTR UNSPEC_LASX_XVADD_Q UNSPEC_LASX_XVSUB_Q UNSPEC_LASX_XVREPLVE @@ -4232,18 +4231,6 @@ (define_insn "lasx_xvhsubw_qu_du" [(set_attr "type" "simd_int_arith") (set_attr "mode" "V4DI")]) -;;XVROTR.B XVROTR.H XVROTR.W XVROTR.D -;;TODO-478 -(define_insn "lasx_xvrotr_" - [(set (match_operand:ILASX 0 "register_operand" "=f") - (unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f") - (match_operand:ILASX 2 "register_operand" "f")] - UNSPEC_LASX_XVROTR))] - "ISA_HAS_LASX" - "xvrotr.\t%u0,%u1,%u2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - ;;XVADD.Q ;;TODO2 (define_insn "lasx_xvadd_q" @@ -4426,15 +4413,6 @@ (define_insn "lasx_xvexth_qu_du" [(set_attr "type" "simd_fcvt") (set_attr "mode" "V4DI")]) -(define_insn "lasx_xvrotri_" - [(set (match_operand:ILASX 0 "register_operand" "=f") - (rotatert:ILASX (match_operand:ILASX 1 "register_operand" "f") - (match_operand 2 "const__operand" "")))] - "ISA_HAS_LASX" - "xvrotri.\t%u0,%u1,%2" - [(set_attr "type" "simd_shf") - (set_attr "mode" "")]) - (define_insn "lasx_xvextl_q_d" [(set (match_operand:V4DI 0 "register_operand" "=f") (unspec:V4DI [(match_operand:V4DI 1 "register_operand" "f")] diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index a6fcc1c731e..5d037ab7f10 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -369,6 +369,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lsx_vsrli_h CODE_FOR_vlshrv8hi3 #define CODE_FOR_lsx_vsrli_w CODE_FOR_vlshrv4si3 #define CODE_FOR_lsx_vsrli_d CODE_FOR_vlshrv2di3 +#define CODE_FOR_lsx_vrotr_b CODE_FOR_vrotrv16qi3 +#define CODE_FOR_lsx_vrotr_h CODE_FOR_vrotrv8hi3 +#define CODE_FOR_lsx_vrotr_w CODE_FOR_vrotrv4si3 +#define CODE_FOR_lsx_vrotr_d CODE_FOR_vrotrv2di3 +#define CODE_FOR_lsx_vrotri_b CODE_FOR_rotrv16qi3 +#define CODE_FOR_lsx_vrotri_h CODE_FOR_rotrv8hi3 +#define CODE_FOR_lsx_vrotri_w CODE_FOR_rotrv4si3 +#define CODE_FOR_lsx_vrotri_d CODE_FOR_rotrv2di3 #define CODE_FOR_lsx_vsub_b CODE_FOR_subv16qi3 #define CODE_FOR_lsx_vsub_h CODE_FOR_subv8hi3 #define CODE_FOR_lsx_vsub_w CODE_FOR_subv4si3 @@ -634,6 +642,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) #define CODE_FOR_lasx_xvsrli_h CODE_FOR_vlshrv16hi3 #define CODE_FOR_lasx_xvsrli_w CODE_FOR_vlshrv8si3 #define CODE_FOR_lasx_xvsrli_d CODE_FOR_vlshrv4di3 +#define CODE_FOR_lasx_xvrotr_b CODE_FOR_vrotrv32qi3 +#define CODE_FOR_lasx_xvrotr_h CODE_FOR_vrotrv16hi3 +#define CODE_FOR_lasx_xvrotr_w CODE_FOR_vrotrv8si3 +#define CODE_FOR_lasx_xvrotr_d CODE_FOR_vrotrv4di3 +#define CODE_FOR_lasx_xvrotri_b CODE_FOR_rotrv32qi3 +#define CODE_FOR_lasx_xvrotri_h CODE_FOR_rotrv16hi3 +#define CODE_FOR_lasx_xvrotri_w CODE_FOR_rotrv8si3 +#define CODE_FOR_lasx_xvrotri_d CODE_FOR_rotrv4di3 #define CODE_FOR_lasx_xvsub_b CODE_FOR_subv32qi3 #define CODE_FOR_lasx_xvsub_h CODE_FOR_subv16hi3 #define CODE_FOR_lasx_xvsub_w CODE_FOR_subv8si3 diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 537afaf9625..23239993404 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -141,7 +141,6 @@ (define_c_enum "unspec" [ UNSPEC_LSX_VMADDWOD UNSPEC_LSX_VMADDWOD2 UNSPEC_LSX_VMADDWOD3 - UNSPEC_LSX_VROTR UNSPEC_LSX_VADD_Q UNSPEC_LSX_VSUB_Q UNSPEC_LSX_VEXTH_Q_D @@ -363,14 +362,6 @@ (define_mode_attr bitmask (V8HI "exp_8") (V16QI "exp_16")]) -;; This attribute is used to form an immediate operand constraint using -;; "const__operand". -(define_mode_attr bitimm - [(V16QI "uimm3") - (V8HI "uimm4") - (V4SI "uimm5") - (V2DI "uimm6")]) - (define_expand "vec_init" [(match_operand:LSX 0 "register_operand") (match_operand:LSX 1 "")] @@ -4152,16 +4143,6 @@ (define_insn "lsx_vmaddwod_q_du_d" [(set_attr "type" "simd_int_arith") (set_attr "mode" "V2DI")]) -(define_insn "lsx_vrotr_" - [(set (match_operand:ILSX 0 "register_operand" "=f") - (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f") - (match_operand:ILSX 2 "register_operand" "f")] - UNSPEC_LSX_VROTR))] - "ISA_HAS_LSX" - "vrotr.\t%w0,%w1,%w2" - [(set_attr "type" "simd_int_arith") - (set_attr "mode" "")]) - (define_insn "lsx_vadd_q" [(set (match_operand:V2DI 0 "register_operand" "=f") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f") @@ -4255,15 +4236,6 @@ (define_insn "lsx_vexth_qu_du" [(set_attr "type" "simd_fcvt") (set_attr "mode" "V2DI")]) -(define_insn "lsx_vrotri_" - [(set (match_operand:ILSX 0 "register_operand" "=f") - (rotatert:ILSX (match_operand:ILSX 1 "register_operand" "f") - (match_operand 2 "const__operand" "")))] - "ISA_HAS_LSX" - "vrotri.\t%w0,%w1,%2" - [(set_attr "type" "simd_shf") - (set_attr "mode" "")]) - (define_insn "lsx_vextl_q_d" [(set (match_operand:V2DI 0 "register_operand" "=f") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")] diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 79324183233..6937477e3df 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -72,6 +72,13 @@ (define_mode_attr elmbits [(V2DI "64") (V4DI "64") (V8HI "16") (V16HI "16") (V16QI "8") (V32QI "8")]) +;; This attribute is used to form an immediate operand constraint using +;; "const__operand". +(define_mode_attr bitimm [(V16QI "uimm3") (V32QI "uimm3") + (V8HI "uimm4") (V16HI "uimm4") + (V4SI "uimm5") (V8SI "uimm5") + (V2DI "uimm6") (V4DI "uimm6")]) + ;; ======================================================================= ;; For many LASX instructions, the only difference of it from the LSX ;; counterpart is the length of vector operands. Describe these LSX/LASX @@ -203,6 +210,28 @@ (define_insn "mul3_highpart" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) +;; vrotr.{b/h/w/d} + +(define_insn "vrotr3" + [(set (match_operand:IVEC 0 "register_operand" "=f") + (rotatert:IVEC (match_operand:IVEC 1 "register_operand" "f") + (match_operand:IVEC 2 "register_operand" "f")))] + "" + "vrotr.\t%0,%1,%2" + [(set_attr "type" "simd_int_arith") + (set_attr "mode" "")]) + +;; vrotri.{b/h/w/d} + +(define_insn "rotr3" + [(set (match_operand:IVEC 0 "register_operand" "=f") + (rotatert:IVEC (match_operand:IVEC 1 "register_operand" "f") + (match_operand:SI 2 "const__operand")))] + "" + "vrotri.\t%0,%1,%2"; + [(set_attr "type" "simd_int_arith") + (set_attr "mode" "")]) + ; The LoongArch SX Instructions. (include "lsx.md") diff --git a/gcc/testsuite/gcc.target/loongarch/vect-rotr.c b/gcc/testsuite/gcc.target/loongarch/vect-rotr.c new file mode 100644 index 00000000000..733c36334ce --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vect-rotr.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlasx" } */ +/* { dg-final { scan-assembler "\tvrotr\.w\t" } } */ +/* { dg-final { scan-assembler "\txvrotr\.w\t" } } */ +/* { dg-final { scan-assembler "\tvrotri\.w\t\[^\n\]*7\n" } } */ +/* { dg-final { scan-assembler "\txvrotri\.w\t\[^\n\]*7\n" } } */ + +unsigned int a[8], b[8]; + +void +test1 (void) +{ + for (int i = 0; i < 4; i++) + a[i] = a[i] >> b[i] | a[i] << (32 - b[i]); +} + +void +test2 (void) +{ + for (int i = 0; i < 8; i++) + a[i] = a[i] >> b[i] | a[i] << (32 - b[i]); +} + +void +test3 (void) +{ + for (int i = 0; i < 4; i++) + a[i] = a[i] >> 7 | a[i] << 25; +} + +void +test4 (void) +{ + for (int i = 0; i < 8; i++) + a[i] = a[i] >> 7 | a[i] << 25; +} From patchwork Mon Nov 20 00:47:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 166913 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9910:0:b0:403:3b70:6f57 with SMTP id i16csp1909037vqn; Sun, 19 Nov 2023 16:48:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IEicTXjjdiQ2tTA3HfzyDRrSbd/Vjv0368CZZtVzih7FAKCJ8dzCWfUqnw2kTLAWsbRfTjM X-Received: by 2002:ad4:5bcf:0:b0:672:20c0:ac08 with SMTP id t15-20020ad45bcf000000b0067220c0ac08mr7502900qvt.48.1700441336377; Sun, 19 Nov 2023 16:48:56 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1700441336; cv=pass; d=google.com; s=arc-20160816; b=mkm228Ffle/PAI4uBHRG9AeKFAAirM2RQ2uoHzqbUop4+n1xwx71XUEAJInEle3t9I fm4jGlV4C5f2XJSTiXz0J1/O0si71AtfCI+s20OGB55XjdHWGPx3MguHlMAsO4JYEIUp wotAqmgBf423H3RpJ4CSPqhCGNB3aA4C9pgL3MM6kRgcGFrFYmXkIkeqSplmZPN9wJhb 1IqzZBPBmMqpFwMlQpaPw6OJ5HCZ/bDVZlvdc79syxh7rQM99D066xxnVene6Y+o9z1Q 7SJwOU4lKKBQFcrTpLR22o7Lh5t551RxVDRP3VbczszNNm+D8nlILR/Kxk8XOpUnwtr4 e92A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=WtFU55GoKOdX2ol5Cgy3bH2UFF+AiGeBI/qktavWd6o=; fh=oUCfM/eMlWtMCtZZKY1bglzxCo7b3kw9D5LTFFWuz38=; b=GdoRkJML4Z/V8hlFB6GFlrDqKmgADYOCVIEmPl8sPR3fr8OqSugsNwzLtKip1ZBDiX o9VNoOOwYpLLsieHjvw6mA4ZmsxV711LKe2BGG9FTZvcfxoAhbARpJu+hjfdg26/MpwA oXelGSxYjwzz7t47rGRCkgarxTUXsOQX7P/i6mCVwYEr5HAuCjWptkcBym2iBci76qH7 MQS+cdf4i6dbU53J7U1uop1TCNyjK/ZpSUD1FnL2/R6p0qLteWP4MM+Jz+ZI++8OuDyh uIFgPMa4s8VoY9mRQMUkdN2XNtbfFwXW4ul66FWayVlcroxi/x7c11IJgjAnDEEGcfaO A6TQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@xry111.site header.s=default header.b=FSwB8pCe; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=xry111.site Received: from server2.sourceware.org (server2.sourceware.org. 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(unknown [IPv6:240e:358:11b1:2500:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 094E666B3B; Sun, 19 Nov 2023 19:48:00 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v3 4/5] LoongArch: Remove lrint_allow_inexact Date: Mon, 20 Nov 2023 08:47:27 +0800 Message-ID: <20231120004728.205167-5-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231120004728.205167-1-xry111@xry111.site> References: <20231120004728.205167-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783041975023796627 X-GMAIL-MSGID: 1783041975023796627 No functional change, just a cleanup. gcc/ChangeLog: * config/loongarch/loongarch.md (lrint_allow_inexact): Remove. (2): Check if == UNSPEC_FTINT instead of . --- gcc/config/loongarch/loongarch.md | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 78ed63f2132..1e019815451 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -585,9 +585,6 @@ (define_int_attr lrint_pattern [(UNSPEC_FTINT "lrint") (define_int_attr lrint_submenmonic [(UNSPEC_FTINT "") (UNSPEC_FTINTRM "rm") (UNSPEC_FTINTRP "rp")]) -(define_int_attr lrint_allow_inexact [(UNSPEC_FTINT "1") - (UNSPEC_FTINTRM "0") - (UNSPEC_FTINTRP "0")]) ;; Iterator and attributes for bytepick.d (define_int_iterator bytepick_w_ashift_amount [8 16 24]) @@ -2384,7 +2381,7 @@ (define_insn "2" (unspec:ANYFI [(match_operand:ANYF 1 "register_operand" "f")] LRINT))] "TARGET_HARD_FLOAT && - ( + ( == UNSPEC_FTINT || flag_fp_int_builtin_inexact || !flag_trapping_math)" "ftint.. %0,%1" From patchwork Mon Nov 20 00:47:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 166914 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9910:0:b0:403:3b70:6f57 with SMTP id i16csp1909217vqn; Sun, 19 Nov 2023 16:49:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IHu2/3EYnKEbr2379mDwajVAukbokIPSFzqRiM5eW5s/zSjuvUNl3eYKI2dYn07NE1zn7Ah X-Received: by 2002:a05:620a:618e:b0:76c:ea3f:9010 with SMTP id or14-20020a05620a618e00b0076cea3f9010mr8125523qkn.16.1700441365413; Sun, 19 Nov 2023 16:49:25 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1700441365; cv=pass; d=google.com; s=arc-20160816; b=DKZ+6ikrBiTqqhL6F2hMXDlxA9zoWhxBXy2kVRyHYgHMu59MlUqbWQpDtUkngJc29Y QerDMjcJ9O6YoS2Fv9A6VsDQyOHjwFZcxYtmwbHk+jXwey3t5H6CUyR4+umq6U+g+v5G yXKsSjZVQf8wywWN62IF3mKHtTptfftYA9qoYKv55yW/Re++IIJa9lpufB42t2WSyTbq d5GNKpye+cqwvlFXQ+/ew4dVo/YqJbewCPeLJ8CCq1+/sFGiPjs4A1i6C6inA/BOhUkL PxHV3yZ5Y9/hlgl6V1QYmYNc6UFuvPrHwCh9Bmgb3RnOxk7/QjE7NO8t0yDYmodrDXXk ioxg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=00YWl3buaxe47y1lw5snagmzs9/KSwL+lEl/7qLnKGE=; fh=oUCfM/eMlWtMCtZZKY1bglzxCo7b3kw9D5LTFFWuz38=; b=kYbOEIRy0u+n1oHush5kbLIlNOCwGY4KWzzeeoTveEaMWHn6pkrlGsilJpTyMApssu lLtXFT85kgPLpMpjwUpx4vEHe2ptq3cRbaQRerZXasxSyMP0YTPfaBiriNJYXlRl8LXq 0eCBo2UjYX55t9LQ1I+twDgpszU6Bq1Q4Ja+K5jOF+/xbwQ1gGEgmncviwig0m0jtxck sgQY3tKtO2YjGUNyOk1UMZI3q3I9VzGliqk1y4YYa45vW5yNMz0XWazpzfhV54bJ6/Wg T6u2wdKAh5H9jANE60a6hFOuTojT3hAOs6nXDyCNGoFRBQgI9fr4YsQ9vCpwYXnp+xbT xOfQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@xry111.site header.s=default header.b=fb6U4kS0; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=xry111.site Received: from server2.sourceware.org (server2.sourceware.org. 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(unknown [IPv6:240e:358:11b1:2500:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 0A2B666B39; Sun, 19 Nov 2023 19:48:05 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v3 5/5] LoongArch: Use LSX for scalar FP rounding with explicit rounding mode Date: Mon, 20 Nov 2023 08:47:28 +0800 Message-ID: <20231120004728.205167-6-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231120004728.205167-1-xry111@xry111.site> References: <20231120004728.205167-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1783042005097398685 X-GMAIL-MSGID: 1783042005097398685 In LoongArch FP base ISA there is only the frint.{s/d} instruction which reads the global rounding mode. Utilize LSX for explicit rounding mode even if the operand is scalar. It seems wasting the CPU power, but still much faster than calling the library function. gcc/ChangeLog: * config/loongarch/simd.md (LSX_SCALAR_FRINT): New int iterator. (VLSX_FOR_FMODE): New mode attribute. (2): New expander, expanding to vreplvei.{w/d} + frint{rp/rz/rm/rne}.{s.d}. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vect-frint-scalar.c: New test. * gcc.target/loongarch/vect-frint-scalar-no-inexact.c: New test. --- gcc/config/loongarch/simd.md | 29 +++++++++++++ .../loongarch/vect-frint-scalar-no-inexact.c | 23 ++++++++++ .../gcc.target/loongarch/vect-frint-scalar.c | 43 +++++++++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-frint-scalar-no-inexact.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-frint-scalar.c diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md index 6937477e3df..e592de49aa0 100644 --- a/gcc/config/loongarch/simd.md +++ b/gcc/config/loongarch/simd.md @@ -150,6 +150,35 @@ (define_expand "ftrunc2" UNSPEC_SIMD_FRINTRZ))] "") +;; Use LSX for scalar ceil/floor/trunc/roundeven when -mlsx and -ffp-int- +;; builtin-inexact. The base FP instruction set lacks these operations. +;; Yes we are wasting 50% or even 75% of the CPU horsepower, but it's still +;; much faster than calling a libc function: on LA464 and LA664 there is a +;; 3x ~ 5x speed up. +;; +;; Note that a vreplvei instruction is needed or we'll also operate on the +;; junk in high bits of the vector register and produce random FP exceptions. + +(define_int_iterator LSX_SCALAR_FRINT + [UNSPEC_SIMD_FRINTRP + UNSPEC_SIMD_FRINTRZ + UNSPEC_SIMD_FRINTRM + UNSPEC_SIMD_FRINTRNE]) + +(define_mode_attr VLSX_FOR_FMODE [(DF "V2DF") (SF "V4SF")]) + +(define_expand "2" + [(set (match_dup 2) + (vec_duplicate: + (match_operand:ANYF 1 "register_operand"))) + (set (match_dup 2) + (unspec: [(match_dup 2)] LSX_SCALAR_FRINT)) + (set (match_operand:ANYF 0 "register_operand") + (vec_select:ANYF (match_dup 2) (parallel [(const_int 0)]))) + (clobber (match_scratch: 3))] + "ISA_HAS_LSX && (flag_fp_int_builtin_inexact || !flag_trapping_math)" + "operands[2] = gen_reg_rtx (mode);") + ;; vftint.{/rp/rz/rm} (define_insn "_vftint__" diff --git a/gcc/testsuite/gcc.target/loongarch/vect-frint-scalar-no-inexact.c b/gcc/testsuite/gcc.target/loongarch/vect-frint-scalar-no-inexact.c new file mode 100644 index 00000000000..002e3b92df7 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vect-frint-scalar-no-inexact.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlsx -fno-fp-int-builtin-inexact" } */ + +#include "vect-frint-scalar.c" + +/* cannot use LSX for these with -fno-fp-int-builtin-inexact, + call library function. */ +/* { dg-final { scan-assembler "\tb\t%plt\\(ceil\\)" } } */ +/* { dg-final { scan-assembler "\tb\t%plt\\(ceilf\\)" } } */ +/* { dg-final { scan-assembler "\tb\t%plt\\(floor\\)" } } */ +/* { dg-final { scan-assembler "\tb\t%plt\\(floorf\\)" } } */ +/* { dg-final { scan-assembler "\tb\t%plt\\(trunc\\)" } } */ +/* { dg-final { scan-assembler "\tb\t%plt\\(truncf\\)" } } */ +/* { dg-final { scan-assembler "\tb\t%plt\\(roundeven\\)" } } */ +/* { dg-final { scan-assembler "\tb\t%plt\\(roundevenf\\)" } } */ + +/* nearbyint is not allowed to rasie FE_INEXACT for decades */ +/* { dg-final { scan-assembler "\tb\t%plt\\(nearbyint\\)" } } */ +/* { dg-final { scan-assembler "\tb\t%plt\\(nearbyintf\\)" } } */ + +/* rint should just use basic FP operation */ +/* { dg-final { scan-assembler "\tfrint\.s" } } */ +/* { dg-final { scan-assembler "\tfrint\.d" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/vect-frint-scalar.c b/gcc/testsuite/gcc.target/loongarch/vect-frint-scalar.c new file mode 100644 index 00000000000..c7cb40be7d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vect-frint-scalar.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlsx" } */ + +#define test(func, suffix) \ +__typeof__ (1.##suffix) \ +_##func##suffix (__typeof__ (1.##suffix) x) \ +{ \ + return __builtin_##func##suffix (x); \ +} + +test (ceil, f) +test (ceil, ) +test (floor, f) +test (floor, ) +test (trunc, f) +test (trunc, ) +test (roundeven, f) +test (roundeven, ) +test (nearbyint, f) +test (nearbyint, ) +test (rint, f) +test (rint, ) + +/* { dg-final { scan-assembler "\tvfrintrp\.s" } } */ +/* { dg-final { scan-assembler "\tvfrintrm\.s" } } */ +/* { dg-final { scan-assembler "\tvfrintrz\.s" } } */ +/* { dg-final { scan-assembler "\tvfrintrne\.s" } } */ +/* { dg-final { scan-assembler "\tvfrintrp\.d" } } */ +/* { dg-final { scan-assembler "\tvfrintrm\.d" } } */ +/* { dg-final { scan-assembler "\tvfrintrz\.d" } } */ +/* { dg-final { scan-assembler "\tvfrintrne\.d" } } */ + +/* must do vreplvei first */ +/* { dg-final { scan-assembler-times "\tvreplvei\.w\t\\\$vr0,\\\$vr0,0" 4 } } */ +/* { dg-final { scan-assembler-times "\tvreplvei\.d\t\\\$vr0,\\\$vr0,0" 4 } } */ + +/* nearbyint is not allowed to rasie FE_INEXACT for decades */ +/* { dg-final { scan-assembler "\tb\t%plt\\(nearbyint\\)" } } */ +/* { dg-final { scan-assembler "\tb\t%plt\\(nearbyintf\\)" } } */ + +/* rint should just use basic FP operation */ +/* { dg-final { scan-assembler "\tfrint\.s" } } */ +/* { dg-final { scan-assembler "\tfrint\.d" } } */