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server2.sourceware.org X-QQ-mid: bizesmtp76t1700358335tuwcy19d Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 19 Nov 2023 09:45:34 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: PwR4Lwy9nzKFsKJksH66l5qih/4zHey9AZNydlsfEKOvEj/8g/mBNTvn53/yF 1ksJm/6U306z9PBNo9Kd0XraeYbNiPXRBkguEb5w5FA4mn3tbE58Kt+6RgEhHejw8TcPAgr GG+lP4BFzfMps6SqDA618yP/Oophxdzu1HJUrvn0/PQwufz8xKvhz1DZX8B6fbR8J5p3k+a mxbQ166F320ePSPqvXWuBkyaBx4W5jrVF1jCrHd/sntIchAso/VVzUsMaWSyWlviFq1WvmF l4mbdsOxLsu/DT74lkAM9EsnRFJqXYUUTCw1VaQ3LvpS1IST9nfb3tbW68JybBUR4aHgzlJ mzEYjXC6SguWjvLkvc8ZYhmsmQ8yw== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 6574165359197561313 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed V3] RISC-V: Fix bug of tuple move splitter Date: Sun, 19 Nov 2023 09:45:33 +0800 Message-Id: <20231119014533.1838815-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782954988869994159 X-GMAIL-MSGID: 1782954988869994159 PR target/112561 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_tuple_move): Fix bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112561.c: New test. --- gcc/config/riscv/riscv-v.cc | 4 ++++ .../gcc.target/riscv/rvv/autovec/pr112561.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 6a2009ffb05..f769c1474e0 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2148,6 +2148,10 @@ expand_tuple_move (rtx *ops) offset = ops[2]; } + /* Non-fractional LMUL has whole register moves that don't require a + vsetvl for VLMAX. */ + if (fractional_p) + emit_vlmax_vsetvl (subpart_mode, ops[4]); if (MEM_P (ops[1])) { /* Load operations. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c new file mode 100644 index 00000000000..25e61fa12c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-options "-O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */ + +int printf(char *, ...); +int a, b, c, e; +short d[7][7] = {}; +int main() { + short f; + c = 0; + for (; c <= 6; c++) { + e |= d[c][c] & 1; + b &= f & 3; + } + printf("%d\n", a); + return 0; +}