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(unknown [IPv6:240e:358:1152:b00:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 3B88C66C08; Fri, 17 Nov 2023 15:44:01 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v2 2/6] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution Date: Sat, 18 Nov 2023 04:43:19 +0800 Message-ID: <20231117204323.453536-3-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231117204323.453536-1-xry111@xry111.site> References: <20231117204323.453536-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_QUOTING autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782845424128710389 X-GMAIL-MSGID: 1782845424128710389 LoongArch v1.10 introduced the concept of ISA evolution. During ISA evolution, many independent features can be added and enumerated via CPUCFG. Add a data file into genopts storing the CPUCFG word, bit, the name of the command line option controlling if this feature should be used for compilation, and the text description. Make genstr.sh process these info and add the command line options into loongarch.opt and loongarch-str.h, and generate a new file loongarch-cpucfg-map.h for mapping CPUCFG output to the corresponding option. When handling -march=native, use the information in loongarch-cpucfg-map.h to generate the corresponding option mask. Enable the features implied by -march setting unless the user has explicitly disabled the feature. The added options (-mdiv32 and -mld-seq-sa) are not really handled yet. They'll be used in the following patches. gcc/ChangeLog: * config/loongarch/genopts/isa-evolution.in: New data file. * config/loongarch/genopts/genstr.sh: Translate info in isa-evolution.in when generating loongarch-str.h, loongarch.opt, and loongarch-cpucfg-map.h. * config/loongarch/genopts/loongarch.opt.in (isa_evolution): New variable. * config/loongarch/t-loongarch: (loongarch-cpucfg-map.h): New rule. (loongarch-str.h): Depend on isa-evolution.in. (loongarch.opt): Depend on isa-evolution.in. (loongarch-cpu.o): Depend on loongarch-cpucfg-map.h. * config/loongarch/loongarch-str.h: Regenerate. * config/loongarch/loongarch-def.h (loongarch_isa): Add field for evolution features. Add helper function to enable features in this field. Probe native CPU capability and save the corresponding options into preset. * config/loongarch/loongarch-cpu.cc (fill_native_cpu_config): Probe native CPU capability and save the corresponding options into preset. (cache_cpucfg): Simplify with C++11-style for loop. (cpucfg_useful_idx, N_CPUCFG_WORDS): Move to ... * config/loongarch/loongarch.cc (loongarch_option_override_internal): Enable the ISA evolution feature options implied by -march and not explicitly disabled. (loongarch_asm_code_end): New function, print ISA information as comments in the assembly if -fverbose-asm. It makes easier to debug things like -march=native. (TARGET_ASM_CODE_END): Define. * config/loongarch/loongarch.opt: Regenerate. * config/loongarch/loongarch-cpucfg-map.h: Generate. (cpucfg_useful_idx, N_CPUCFG_WORDS) ... here. --- gcc/config/loongarch/genopts/genstr.sh | 92 ++++++++++++++++++- gcc/config/loongarch/genopts/isa-evolution.in | 2 + gcc/config/loongarch/genopts/loongarch.opt.in | 7 ++ gcc/config/loongarch/loongarch-cpu.cc | 46 +++++----- gcc/config/loongarch/loongarch-cpucfg-map.h | 48 ++++++++++ gcc/config/loongarch/loongarch-def.h | 7 ++ gcc/config/loongarch/loongarch-str.h | 7 +- gcc/config/loongarch/loongarch.cc | 31 +++++++ gcc/config/loongarch/loongarch.opt | 20 +++- gcc/config/loongarch/t-loongarch | 21 ++++- 10 files changed, 245 insertions(+), 36 deletions(-) create mode 100644 gcc/config/loongarch/genopts/isa-evolution.in create mode 100644 gcc/config/loongarch/loongarch-cpucfg-map.h diff --git a/gcc/config/loongarch/genopts/genstr.sh b/gcc/config/loongarch/genopts/genstr.sh index 04e785576bb..cc83496ae38 100755 --- a/gcc/config/loongarch/genopts/genstr.sh +++ b/gcc/config/loongarch/genopts/genstr.sh @@ -25,8 +25,8 @@ cd "$(dirname "$0")" # Generate a header containing definitions from the string table. gen_defines() { cat <. */ + +#ifndef LOONGARCH_CPUCFG_MAP_H +#define LOONGARCH_CPUCFG_MAP_H + +#include "options.h" + +static constexpr struct { + int cpucfg_word; + unsigned int cpucfg_bit; + HOST_WIDE_INT isa_evolution_bit; +} cpucfg_map[] = { +EOF + + # Generate the strings from isa-evolution.in. + awk '{ + gsub(/-/, "_", $3) + print(" { "$1", 1u << "$2", OPTION_MASK_ISA_"toupper($3)" },") + }' isa-evolution.in + + echo "};" + echo + echo "static constexpr int cpucfg_useful_idx[] = {" + + awk 'BEGIN { print(" 0,\n 1,\n 2,\n 16,\n 17,\n 18,\n 19,") } + {if ($1+0 > max+0) max=$1; print(" "$1",")}' \ + isa-evolution.in | sort -n | uniq + + echo "};" + echo "" + + awk 'BEGIN { max=19 } + { if ($1+0 > max+0) max=$1 } + END { print "static constexpr int N_CPUCFG_WORDS = "1+max";" }' \ + isa-evolution.in + + echo "#endif /* LOONGARCH_CPUCFG_MAP_H */" } main() { case "$1" in + cpucfg-map) gen_cpucfg_map;; header) gen_defines;; opt) gen_options;; - *) echo "Unknown Command: \"$1\". Available: header, opt"; exit 1;; + *) echo "Unknown Command: \"$1\". Available: cpucfg-map, header, opt"; exit 1;; esac } diff --git a/gcc/config/loongarch/genopts/isa-evolution.in b/gcc/config/loongarch/genopts/isa-evolution.in new file mode 100644 index 00000000000..e58f0d6a1a1 --- /dev/null +++ b/gcc/config/loongarch/genopts/isa-evolution.in @@ -0,0 +1,2 @@ +2 26 div32 Support div.w[u] and mod.w[u] instructions with inputs not sign-extended. +3 23 ld-seq-sa Do not need load-load barriers (dbar 0x700). diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in index b274b3fb21e..8af6cc6f532 100644 --- a/gcc/config/loongarch/genopts/loongarch.opt.in +++ b/gcc/config/loongarch/genopts/loongarch.opt.in @@ -247,3 +247,10 @@ Target Undocumented Joined UInteger Var(loongarch_vect_issue_info) Init(4) Integ Indicate how many non memory access vector instructions can be issued per cycle, it's used in unroll factor determination for autovectorizer. The default value is 4. + +; Features added during ISA evolution. This concept is different from ISA +; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the +; explanation. These features may be implemented and enumerated with +; CPUCFG independantly, so we use bit flags to specify them. +Variable +HOST_WIDE_INT isa_evolution = 0 diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc index f3a13414143..f41e175257a 100644 --- a/gcc/config/loongarch/loongarch-cpu.cc +++ b/gcc/config/loongarch/loongarch-cpu.cc @@ -29,12 +29,11 @@ along with GCC; see the file COPYING3. If not see #include "loongarch-def.h" #include "loongarch-opts.h" #include "loongarch-cpu.h" +#include "loongarch-cpucfg-map.h" #include "loongarch-str.h" /* Native CPU detection with "cpucfg" */ -#define N_CPUCFG_WORDS 0x15 static uint32_t cpucfg_cache[N_CPUCFG_WORDS] = { 0 }; -static const int cpucfg_useful_idx[] = {0, 1, 2, 16, 17, 18, 19}; static uint32_t read_cpucfg_word (int wordno) @@ -56,11 +55,8 @@ read_cpucfg_word (int wordno) void cache_cpucfg (void) { - for (unsigned int i = 0; i < sizeof (cpucfg_useful_idx) / sizeof (int); i++) - { - cpucfg_cache[cpucfg_useful_idx[i]] - = read_cpucfg_word (cpucfg_useful_idx[i]); - } + for (int idx: cpucfg_useful_idx) + cpucfg_cache[idx] = read_cpucfg_word (idx); } uint32_t @@ -125,11 +121,12 @@ fill_native_cpu_config (struct loongarch_target *tgt) int tmp; tgt->cpu_arch = native_cpu_type; + auto &preset = loongarch_cpu_default_isa[tgt->cpu_arch]; + /* Fill: loongarch_cpu_default_isa[tgt->cpu_arch].base With: base architecture (ARCH) At: cpucfg_words[1][1:0] */ - #define PRESET_ARCH (loongarch_cpu_default_isa[tgt->cpu_arch].base) switch (cpucfg_cache[1] & 0x3) { case 0x02: @@ -144,19 +141,18 @@ fill_native_cpu_config (struct loongarch_target *tgt) } /* Check consistency with PRID presets. */ - if (native_cpu_type != CPU_NATIVE && tmp != PRESET_ARCH) + if (native_cpu_type != CPU_NATIVE && tmp != preset.base) warning (0, "base architecture %qs differs from PRID preset %qs", loongarch_isa_base_strings[tmp], - loongarch_isa_base_strings[PRESET_ARCH]); + loongarch_isa_base_strings[preset.base]); /* Use the native value anyways. */ - PRESET_ARCH = tmp; + preset.base = tmp; /* Fill: loongarch_cpu_default_isa[tgt->cpu_arch].fpu With: FPU type (FP, FP_SP, FP_DP) At: cpucfg_words[2][2:0] */ - #define PRESET_FPU (loongarch_cpu_default_isa[tgt->cpu_arch].fpu) switch (cpucfg_cache[2] & 0x7) { case 0x07: @@ -179,20 +175,19 @@ fill_native_cpu_config (struct loongarch_target *tgt) } /* Check consistency with PRID presets. */ - if (native_cpu_type != CPU_NATIVE && tmp != PRESET_FPU) + if (native_cpu_type != CPU_NATIVE && tmp != preset.fpu) warning (0, "floating-point unit %qs differs from PRID preset %qs", loongarch_isa_ext_strings[tmp], - loongarch_isa_ext_strings[PRESET_FPU]); + loongarch_isa_ext_strings[preset.fpu]); /* Use the native value anyways. */ - PRESET_FPU = tmp; + preset.fpu = tmp; /* Fill: loongarch_cpu_default_isa[CPU_NATIVE].simd With: SIMD extension type (LSX, LASX) At: cpucfg_words[2][7:6] */ - #define PRESET_SIMD (loongarch_cpu_default_isa[tgt->cpu_arch].simd) switch (cpucfg_cache[2] & 0xc0) { case 0xc0: @@ -219,14 +214,19 @@ fill_native_cpu_config (struct loongarch_target *tgt) /* Check consistency with PRID presets. */ /* - if (native_cpu_type != CPU_NATIVE && tmp != PRESET_SIMD) + if (native_cpu_type != CPU_NATIVE && tmp != preset.simd) warning (0, "SIMD extension %qs differs from PRID preset %qs", loongarch_isa_ext_strings[tmp], - loongarch_isa_ext_strings[PRESET_SIMD]); + loongarch_isa_ext_strings[preset.simd]); */ /* Use the native value anyways. */ - PRESET_SIMD = tmp; + preset.simd = tmp; + + /* Features added during ISA evolution. */ + for (const auto &entry: cpucfg_map) + if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit) + preset.evolution |= entry.isa_evolution_bit; } if (tune_native_p) @@ -237,7 +237,7 @@ fill_native_cpu_config (struct loongarch_target *tgt) With: cache size info At: cpucfg_words[16:20][31:0] */ - #define PRESET_CACHE (loongarch_cpu_cache[tgt->cpu_tune]) + auto &preset_cache = loongarch_cpu_cache[tgt->cpu_tune]; struct loongarch_cache native_cache; int l1d_present = 0, l1u_present = 0; int l2d_present = 0; @@ -268,8 +268,8 @@ fill_native_cpu_config (struct loongarch_target *tgt) >> 10; /* in kibibytes */ /* Use the native value anyways. */ - PRESET_CACHE.l1d_line_size = native_cache.l1d_line_size; - PRESET_CACHE.l1d_size = native_cache.l1d_size; - PRESET_CACHE.l2d_size = native_cache.l2d_size; + preset_cache.l1d_line_size = native_cache.l1d_line_size; + preset_cache.l1d_size = native_cache.l1d_size; + preset_cache.l2d_size = native_cache.l2d_size; } } diff --git a/gcc/config/loongarch/loongarch-cpucfg-map.h b/gcc/config/loongarch/loongarch-cpucfg-map.h new file mode 100644 index 00000000000..0c078c39786 --- /dev/null +++ b/gcc/config/loongarch/loongarch-cpucfg-map.h @@ -0,0 +1,48 @@ +/* Generated automatically by "genstr" from "isa-evolution.in". + Please do not edit this file directly. + + Copyright (C) 2023 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#ifndef LOONGARCH_CPUCFG_MAP_H +#define LOONGARCH_CPUCFG_MAP_H + +#include "options.h" + +static constexpr struct { + int cpucfg_word; + unsigned int cpucfg_bit; + HOST_WIDE_INT isa_evolution_bit; +} cpucfg_map[] = { + { 2, 1u << 26, OPTION_MASK_ISA_DIV32 }, + { 3, 1u << 23, OPTION_MASK_ISA_LD_SEQ_SA }, +}; + +static constexpr int cpucfg_useful_idx[] = { + 0, + 1, + 2, + 3, + 16, + 17, + 18, + 19, +}; + +static constexpr int N_CPUCFG_WORDS = 20; +#endif /* LOONGARCH_CPUCFG_MAP_H */ diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index b319cded456..6123c8e0f19 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -46,6 +46,7 @@ along with GCC; see the file COPYING3. If not see #ifndef LOONGARCH_DEF_H #define LOONGARCH_DEF_H +#include #include "loongarch-tune.h" #ifdef __cplusplus @@ -121,6 +122,12 @@ struct loongarch_isa int base; /* ISA_BASE_ */ int fpu; /* ISA_EXT_FPU_ */ int simd; /* ISA_EXT_SIMD_ */ + + /* ISA evolution features implied by -march=, for -march=native probed + via CPUCFG. The features implied by base may be not included here. + + Using int64_t instead of HOST_WIDE_INT for C compatibility. */ + int64_t evolution; }; struct loongarch_abi diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 114dbc692d7..889962e9ab0 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -1,5 +1,5 @@ -/* Generated automatically by "genstr" from "loongarch-strings". - Please do not edit this file directly. +/* Generated automatically by "genstr" from "loongarch-strings" and + "isa-evolution.in". Please do not edit this file directly. Copyright (C) 2021-2023 Free Software Foundation, Inc. Contributed by Loongson Ltd. @@ -69,4 +69,7 @@ along with GCC; see the file COPYING3. If not see #define STR_EXPLICIT_RELOCS_NONE "none" #define STR_EXPLICIT_RELOCS_ALWAYS "always" +#define OPTSTR_DIV32 "div32" +#define OPTSTR_LD_SEQ_SA "ld-seq-sa" + #endif /* LOONGARCH_STR_H */ diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 5bec10d7418..b4bb2b6eeb5 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -7451,6 +7451,10 @@ loongarch_option_override_internal (struct gcc_options *opts, if (loongarch_branch_cost == 0) loongarch_branch_cost = loongarch_cost->branch_cost; + /* If the user hasn't disabled a feature added during ISA evolution, + use the processor's default. */ + isa_evolution |= (la_target.isa.evolution & + ~global_options_set.x_isa_evolution); /* Enable sw prefetching at -O3 and higher. */ if (opts->x_flag_prefetch_loop_arrays < 0 @@ -11430,6 +11434,30 @@ loongarch_builtin_support_vector_misalignment (machine_mode mode, is_packed); } +/* If -fverbose-asm, dump some info for debugging. */ +static void +loongarch_asm_code_end (void) +{ +#define DUMP_FEATURE(PRED) \ + fprintf (asm_out_file, "%s %s: %s\n", ASM_COMMENT_START, #PRED, \ + (PRED) ? "enabled" : "disabled") + + if (flag_verbose_asm) + { + fprintf (asm_out_file, "\n%s CPU: %s\n", ASM_COMMENT_START, + loongarch_cpu_strings [la_target.cpu_arch]); + fprintf (asm_out_file, "%s Tune: %s\n", ASM_COMMENT_START, + loongarch_cpu_strings [la_target.cpu_tune]); + fprintf (asm_out_file, "%s Base ISA: %s\n", ASM_COMMENT_START, + loongarch_isa_base_strings [la_target.isa.base]); + DUMP_FEATURE (TARGET_DIV32); + DUMP_FEATURE (TARGET_LD_SEQ_SA); + } + + fputs ("\n\n", asm_out_file); +#undef DUMP_FEATURE +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -11449,6 +11477,9 @@ loongarch_builtin_support_vector_misalignment (machine_mode mode, #undef TARGET_ASM_FUNCTION_RODATA_SECTION #define TARGET_ASM_FUNCTION_RODATA_SECTION loongarch_function_rodata_section +#undef TARGET_ASM_CODE_END +#define TARGET_ASM_CODE_END loongarch_asm_code_end + #undef TARGET_SCHED_INIT #define TARGET_SCHED_INIT loongarch_sched_init #undef TARGET_SCHED_REORDER diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index 350ca30d232..a39eddc108b 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -1,9 +1,10 @@ ; Generated by "genstr" from the template "loongarch.opt.in" -; and definitions from "loongarch-strings". +; and definitions from "loongarch-strings" and "isa-evolution.in". ; ; Please do not edit this file directly. ; It will be automatically updated during a gcc build -; if you change "loongarch.opt.in" or "loongarch-strings". +; if you change "loongarch.opt.in", "loongarch-strings", or +; "isa-evolution.in". ; ; Copyright (C) 2021-2023 Free Software Foundation, Inc. ; @@ -254,3 +255,18 @@ Target Undocumented Joined UInteger Var(loongarch_vect_issue_info) Init(4) Integ Indicate how many non memory access vector instructions can be issued per cycle, it's used in unroll factor determination for autovectorizer. The default value is 4. + +; Features added during ISA evolution. This concept is different from ISA +; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the +; explanation. These features may be implemented and enumerated with +; CPUCFG independantly, so we use bit flags to specify them. +Variable +HOST_WIDE_INT isa_evolution = 0 + +mdiv32 +Target Mask(ISA_DIV32) Var(isa_evolution) +Support div.w[u] and mod.w[u] instructions with inputs not sign-extended. + +mld-seq-sa +Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution) +Do not need load-load barriers (dbar 0x700). diff --git a/gcc/config/loongarch/t-loongarch b/gcc/config/loongarch/t-loongarch index 667a6bb3b50..7e65bb6e2a8 100644 --- a/gcc/config/loongarch/t-loongarch +++ b/gcc/config/loongarch/t-loongarch @@ -18,8 +18,9 @@ GTM_H += loongarch-multilib.h -OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h \ - $(srcdir)/config/loongarch/loongarch-tune.h +OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h \ + $(srcdir)/config/loongarch/loongarch-tune.h \ + $(srcdir)/config/loongarch/loongarch-cpucfg-map.h # Canonical target triplet from config.gcc LA_MULTIARCH_TRIPLET = $(patsubst LA_MULTIARCH_TRIPLET=%,%,$\ @@ -31,7 +32,8 @@ LA_STR_H = $(srcdir)/config/loongarch/loongarch-str.h # String definition header $(LA_STR_H): s-loongarch-str ; @true s-loongarch-str: $(srcdir)/config/loongarch/genopts/genstr.sh \ - $(srcdir)/config/loongarch/genopts/loongarch-strings + $(srcdir)/config/loongarch/genopts/loongarch-strings \ + $(srcdir)/config/loongarch/genopts/isa-evolution.in $(SHELL) $(srcdir)/config/loongarch/genopts/genstr.sh header \ $(srcdir)/config/loongarch/genopts/loongarch-strings > \ tmp-loongarch-str.h @@ -58,7 +60,8 @@ loongarch-driver.o : $(srcdir)/config/loongarch/loongarch-driver.cc $(LA_STR_H) loongarch-opts.o: $(srcdir)/config/loongarch/loongarch-opts.cc $(LA_STR_H) $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $< -loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H) +loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H) \ + $(srcdir)/config/loongarch/loongarch-cpucfg-map.h $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $< loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.c $(LA_STR_H) @@ -67,6 +70,7 @@ loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.c $(LA_STR_H) $(srcdir)/config/loongarch/loongarch.opt: s-loongarch-opt ; @true s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \ $(srcdir)/config/loongarch/genopts/loongarch.opt.in \ + $(srcdir)/config/loongarch/genopts/isa-evolution.in \ $(srcdir)/config/loongarch/genopts/loongarch-strings $(LA_STR_H) $(SHELL) $(srcdir)/config/loongarch/genopts/genstr.sh opt \ $(srcdir)/config/loongarch/genopts/loongarch.opt.in \ @@ -74,3 +78,12 @@ s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \ $(SHELL) $(srcdir)/../move-if-change tmp-loongarch.opt \ $(srcdir)/config/loongarch/loongarch.opt $(STAMP) s-loongarch-opt + +$(srcdir)/config/loongarch/loongarch-cpucfg-map.h: s-loongarch-cpucfg-map + @true +s-loongarch-cpucfg-map: $(srcdir)/config/loongarch/genopts/genstr.sh \ + $(srcdir)/config/loongarch/genopts/isa-evolution.in + $(SHELL) $< cpucfg-map > tmp-cpucfg.h + $(SHELL) $(srcdir)/../move-if-change tmp-cpucfg.h \ + $(srcdir)/config/loongarch/loongarch-cpucfg-map.h + $(STAMP) $@ From patchwork Fri Nov 17 20:43:20 2023 Content-Type: text/plain; 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(unknown [IPv6:240e:358:1152:b00:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 96D7666B3B; Fri, 17 Nov 2023 15:44:05 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v2 3/6] LoongArch: Add evolution features of base ISA revisions Date: Sat, 18 Nov 2023 04:43:20 +0800 Message-ID: <20231117204323.453536-4-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231117204323.453536-1-xry111@xry111.site> References: <20231117204323.453536-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782845471807268918 X-GMAIL-MSGID: 1782845471807268918 * config/loongarch/loongarch-def.h: (loongarch_isa_base_features): Declare. Define it in ... * config/loongarch/loongarch-cpu.cc (loongarch_isa_base_features): ... here. (fill_native_cpu_config): If we know the base ISA of the CPU model from PRID, use it instead of la64 (v1.0). Check if all expected features of this base ISA is available, emit a warning if not. * config/loongarch/loongarch-opts.cc (config_target_isa): Enable the features implied by the base ISA if not -march=native. --- gcc/config/loongarch/loongarch-cpu.cc | 62 ++++++++++++++++++-------- gcc/config/loongarch/loongarch-def.h | 5 +++ gcc/config/loongarch/loongarch-opts.cc | 3 ++ 3 files changed, 52 insertions(+), 18 deletions(-) diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc index f41e175257a..7acf1a9121d 100644 --- a/gcc/config/loongarch/loongarch-cpu.cc +++ b/gcc/config/loongarch/loongarch-cpu.cc @@ -32,6 +32,19 @@ along with GCC; see the file COPYING3. If not see #include "loongarch-cpucfg-map.h" #include "loongarch-str.h" +/* loongarch_isa_base_features defined here instead of loongarch-def.c + because we need to use options.h. Pay attention on the order of elements + in the initializer becaue ISO C++ does not allow C99 designated + initializers! */ + +#define ISA_BASE_LA64V110_FEATURES \ + (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA) + +int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = { + /* [ISA_BASE_LA64V100] = */ 0, + /* [ISA_BASE_LA64V110] = */ ISA_BASE_LA64V110_FEATURES, +}; + /* Native CPU detection with "cpucfg" */ static uint32_t cpucfg_cache[N_CPUCFG_WORDS] = { 0 }; @@ -127,24 +140,22 @@ fill_native_cpu_config (struct loongarch_target *tgt) With: base architecture (ARCH) At: cpucfg_words[1][1:0] */ - switch (cpucfg_cache[1] & 0x3) - { - case 0x02: - tmp = ISA_BASE_LA64V100; - break; - - default: - fatal_error (UNKNOWN_LOCATION, - "unknown native base architecture %<0x%x%>, " - "%qs failed", (unsigned int) (cpucfg_cache[1] & 0x3), - "-m" OPTSTR_ARCH "=" STR_CPU_NATIVE); - } - - /* Check consistency with PRID presets. */ - if (native_cpu_type != CPU_NATIVE && tmp != preset.base) - warning (0, "base architecture %qs differs from PRID preset %qs", - loongarch_isa_base_strings[tmp], - loongarch_isa_base_strings[preset.base]); + if (native_cpu_type != CPU_NATIVE) + tmp = loongarch_cpu_default_isa[native_cpu_type].base; + else + switch (cpucfg_cache[1] & 0x3) + { + case 0x02: + tmp = ISA_BASE_LA64V100; + break; + + default: + fatal_error (UNKNOWN_LOCATION, + "unknown native base architecture %<0x%x%>, " + "%qs failed", + (unsigned int) (cpucfg_cache[1] & 0x3), + "-m" OPTSTR_ARCH "=" STR_CPU_NATIVE); + } /* Use the native value anyways. */ preset.base = tmp; @@ -227,6 +238,21 @@ fill_native_cpu_config (struct loongarch_target *tgt) for (const auto &entry: cpucfg_map) if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit) preset.evolution |= entry.isa_evolution_bit; + + if (native_cpu_type != CPU_NATIVE) + { + /* Check if the local CPU really supports the features of the base + ISA of probed native_cpu_type. If any feature is not detected, + either GCC or the hardware is buggy. */ + auto base_isa_feature = loongarch_isa_base_features[preset.base]; + if ((preset.evolution & base_isa_feature) != base_isa_feature) + warning (0, + "detected base architecture %qs, but some of its " + "features are not detected; the detected base " + "architecture may be unreliable, only detected " + "features will be enabled", + loongarch_isa_base_strings[preset.base]); + } } if (tune_native_p) diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h index 6123c8e0f19..af7bd635d6e 100644 --- a/gcc/config/loongarch/loongarch-def.h +++ b/gcc/config/loongarch/loongarch-def.h @@ -55,12 +55,17 @@ extern "C" { /* enum isa_base */ extern const char* loongarch_isa_base_strings[]; + /* LoongArch V1.00. */ #define ISA_BASE_LA64V100 0 /* LoongArch V1.10. */ #define ISA_BASE_LA64V110 1 #define N_ISA_BASE_TYPES 2 +/* Unlike other arrays, this is defined in loongarch-cpu.cc. The problem is + we cannot use the C++ header options.h in loongarch-def.c. */ +extern int64_t loongarch_isa_base_features[]; + /* enum isa_ext_* */ extern const char* loongarch_isa_ext_strings[]; #define ISA_EXT_NONE 0 diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc index 67a59152a01..b5836f198c0 100644 --- a/gcc/config/loongarch/loongarch-opts.cc +++ b/gcc/config/loongarch/loongarch-opts.cc @@ -284,6 +284,9 @@ config_target_isa: /* Get default ISA from "-march" or its default value. */ t.isa = loongarch_cpu_default_isa[t.cpu_arch]; + if (t.cpu_arch != CPU_NATIVE) + t.isa.evolution |= loongarch_isa_base_features[t.isa.base]; + /* Apply incremental changes. */ /* "-march=native" overrides the default FPU type. */ From patchwork Fri Nov 17 20:43:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 166334 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9910:0:b0:403:3b70:6f57 with SMTP id i16csp802549vqn; Fri, 17 Nov 2023 12:45:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IG8w677b9oyYl/PwG3Lbon7Ec4pkHfCc2CPQAdpHSJ9+jr6YOc1cO6+r+znyzhJsmdbg+f8 X-Received: by 2002:ac8:5f4f:0:b0:41e:2d77:c727 with SMTP id y15-20020ac85f4f000000b0041e2d77c727mr967640qta.29.1700253924879; Fri, 17 Nov 2023 12:45:24 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1700253924; cv=pass; d=google.com; s=arc-20160816; b=llKRymK6GdzgKiyZd6vHdNjMYR8QbMUDwsmdonA2pzXiWv8L3hmglm+PO6cTTzDNjS oPGFSnGPKmM0NpJjWPpDWpQBeqAQ5lhX7nbw9WJfpAOPiFn6Rh5WtJi15eNDa+nTC7kJ +RWwAB1JAMjuz2In85QBgTKz9uhDsMQzO72IBkZsngodljsPXix5Gxc6KEO+X62OKj2E ywCJXv3RaP9W12qTRxac3C3tVeZ0kn59IZZSo9RXuxn0hzmr6/GEBHm943klYq8HGkPC n1Heh1xUG3fLj3wabMvQUD97AAeWMeDFWlAzzw6+RANeFvmGQWP6v4ZUHvcs5i/hdAF9 Em/Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=Z1pSoBCOVi+99S7y4X0SPx5rKtWH3L6LD2i/qjL9JSQ=; fh=oUCfM/eMlWtMCtZZKY1bglzxCo7b3kw9D5LTFFWuz38=; b=W21TLjOCymHchdAj61YR/b4I1a4v/64KUlKbCCUqIzbAzzsXuwkWHjUVxKRq++u6Yk XiiGSn+xeNF9fFnGBezUIcVMkGbN1ELWzq42oU3lfTHsK7iGKXjUpj6Ii7Kj5HwrsC1U cX9qYl8ObuQghOLSdSM34ne5FTVOn3MaQX4V1i4my6CVh6LGn205RZ/sJo1od/7tn8aw clC+0Q9gwMC0rDCK24OGaNSFLaROMptt9Ya55ce9GGLtFeVM8mkRSQzEEKU59KuPdBD7 tPqfIAf5OWH/Ln/t80Apvl+ut9he6PxvN6y4gZGz0tElcrMzQaA0g7S+YCd2l6lBPFV7 Mw4A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@xry111.site header.s=default header.b=jkEs6ZVC; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=xry111.site Received: from server2.sourceware.org (server2.sourceware.org. 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(unknown [IPv6:240e:358:1152:b00:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id F132966B06; Fri, 17 Nov 2023 15:44:08 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v2 4/6] LoongArch: Take the advantage of -mdiv32 if it's enabled Date: Sat, 18 Nov 2023 04:43:21 +0800 Message-ID: <20231117204323.453536-5-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231117204323.453536-1-xry111@xry111.site> References: <20231117204323.453536-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782845460039048673 X-GMAIL-MSGID: 1782845460039048673 With -mdiv32, we can assume div.w[u] and mod.w[u] works on low 32 bits of a 64-bit GPR even if it's not sign-extended. gcc/ChangeLog: * config/loongarch/loongarch.md (DIV): New mode iterator. (3): Don't expand if TARGET_DIV32. (di3_fake): Disable if TARGET_DIV32. (*3): Allow SImode if TARGET_DIV32. (si3_extended): New insn if TARGET_DIV32. gcc/testsuite/ChangeLog: * gcc.target/loongarch/div-div32.c: New test. * gcc.target/loongarch/div-no-div32.c: New test. --- gcc/config/loongarch/loongarch.md | 31 ++++++++++++++++--- .../gcc.target/loongarch/div-div32.c | 31 +++++++++++++++++++ .../gcc.target/loongarch/div-no-div32.c | 11 +++++++ 3 files changed, 68 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/div-div32.c create mode 100644 gcc/testsuite/gcc.target/loongarch/div-no-div32.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 22814a3679c..a97e5ee094a 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -408,6 +408,10 @@ (define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF]) ;; st.w. (define_mode_iterator ST_ANY [QHWD ANYF]) +;; A mode for anything legal as a input of a div or mod instruction. +(define_mode_iterator DIV [(DI "TARGET_64BIT") + (SI "!TARGET_64BIT || TARGET_DIV32")]) + ;; In GPR templates, a string like "mul." will expand to "mul.w" in the ;; 32-bit version and "mul.d" in the 64-bit version. (define_mode_attr d [(SI "w") (DI "d")]) @@ -914,7 +918,7 @@ (define_expand "3" (match_operand:GPR 2 "register_operand")))] "" { - if (GET_MODE (operands[0]) == SImode && TARGET_64BIT) + if (GET_MODE (operands[0]) == SImode && TARGET_64BIT && !TARGET_DIV32) { rtx reg1 = gen_reg_rtx (DImode); rtx reg2 = gen_reg_rtx (DImode); @@ -934,9 +938,9 @@ (define_expand "3" }) (define_insn "*3" - [(set (match_operand:X 0 "register_operand" "=r,&r,&r") - (any_div:X (match_operand:X 1 "register_operand" "r,r,0") - (match_operand:X 2 "register_operand" "r,r,r")))] + [(set (match_operand:DIV 0 "register_operand" "=r,&r,&r") + (any_div:DIV (match_operand:DIV 1 "register_operand" "r,r,0") + (match_operand:DIV 2 "register_operand" "r,r,r")))] "" { return loongarch_output_division (".\t%0,%1,%2", operands); @@ -949,6 +953,23 @@ (define_insn "*3" (const_string "yes") (const_string "no")))]) +(define_insn "si3_extended" + [(set (match_operand:DI 0 "register_operand" "=r,&r,&r") + (sign_extend + (any_div:SI (match_operand:SI 1 "register_operand" "r,r,0") + (match_operand:SI 2 "register_operand" "r,r,r"))))] + "TARGET_64BIT && TARGET_DIV32" +{ + return loongarch_output_division (".w\t%0,%1,%2", operands); +} + [(set_attr "type" "idiv") + (set_attr "mode" "SI") + (set (attr "enabled") + (if_then_else + (match_test "!!which_alternative == loongarch_check_zero_div_p()") + (const_string "yes") + (const_string "no")))]) + (define_insn "di3_fake" [(set (match_operand:DI 0 "register_operand" "=r,&r,&r") (sign_extend:DI @@ -957,7 +978,7 @@ (define_insn "di3_fake" (any_div:DI (match_operand:DI 1 "register_operand" "r,r,0") (match_operand:DI 2 "register_operand" "r,r,r")) 0)] UNSPEC_FAKE_ANY_DIV)))] - "TARGET_64BIT" + "TARGET_64BIT && !TARGET_DIV32" { return loongarch_output_division (".w\t%0,%1,%2", operands); } diff --git a/gcc/testsuite/gcc.target/loongarch/div-div32.c b/gcc/testsuite/gcc.target/loongarch/div-div32.c new file mode 100644 index 00000000000..8b1f686eca2 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/div-div32.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mdiv32" } */ +/* { dg-final { scan-assembler "div\.w" } } */ +/* { dg-final { scan-assembler "div\.wu" } } */ +/* { dg-final { scan-assembler "mod\.w" } } */ +/* { dg-final { scan-assembler "mod\.wu" } } */ +/* { dg-final { scan-assembler-not "slli\.w.*,0" } } */ + +int +divw (long a, long b) +{ + return (int)a / (int)b; +} + +unsigned int +divwu (long a, long b) +{ + return (unsigned int)a / (unsigned int)b; +} + +int +modw (long a, long b) +{ + return (int)a % (int)b; +} + +unsigned int +modwu (long a, long b) +{ + return (unsigned int)a % (unsigned int)b; +} diff --git a/gcc/testsuite/gcc.target/loongarch/div-no-div32.c b/gcc/testsuite/gcc.target/loongarch/div-no-div32.c new file mode 100644 index 00000000000..f0f697ba589 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/div-no-div32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */ +/* { dg-final { scan-assembler "div\.w" } } */ +/* { dg-final { scan-assembler "div\.wu" } } */ +/* { dg-final { scan-assembler "mod\.w" } } */ +/* { dg-final { scan-assembler "mod\.wu" } } */ + +/* -mno-div32 should be implied by -march=loongarch64. */ +/* { dg-final { scan-assembler-times "slli\.w\[^\n\]*0" 8 } } */ + +#include "div-div32.c" From patchwork Fri Nov 17 20:43:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 166332 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9910:0:b0:403:3b70:6f57 with SMTP id i16csp802343vqn; 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(unknown [IPv6:240e:358:1152:b00:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 4363F66B3B; Fri, 17 Nov 2023 15:44:11 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v2 5/6] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa Date: Sat, 18 Nov 2023 04:43:22 +0800 Message-ID: <20231117204323.453536-6-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231117204323.453536-1-xry111@xry111.site> References: <20231117204323.453536-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782845438544757570 X-GMAIL-MSGID: 1782845438544757570 This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that two loads on the same address won't be reordered with each other". Thus we can omit the "load-load" barrier dbar 0x700. This is only a micro-optimization because dbar 0x700 is already treated as nop if the hardware supports LD_SEQ_SA. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_print_operand): Don't print dbar 0x700 if TARGET_LD_SEQ_SA. * config/loongarch/sync.md (atomic_load): Likewise. --- gcc/config/loongarch/loongarch.cc | 2 +- gcc/config/loongarch/sync.md | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index b4bb2b6eeb5..5d3282c5e93 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -6057,7 +6057,7 @@ loongarch_print_operand (FILE *file, rtx op, int letter) if (loongarch_cas_failure_memorder_needs_acquire ( memmodel_from_int (INTVAL (op)))) fputs ("dbar\t0b10100", file); - else + else if (!TARGET_LD_SEQ_SA) fputs ("dbar\t0x700", file); break; diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md index 67848d72b87..ce3ce89a61d 100644 --- a/gcc/config/loongarch/sync.md +++ b/gcc/config/loongarch/sync.md @@ -119,13 +119,14 @@ (define_insn "atomic_load" case MEMMODEL_SEQ_CST: return "dbar\t0x11\\n\\t" "ld.\t%0,%1\\n\\t" - "dbar\t0x14\\n\\t"; + "dbar\t0x14"; case MEMMODEL_ACQUIRE: return "ld.\t%0,%1\\n\\t" - "dbar\t0x14\\n\\t"; + "dbar\t0x14"; case MEMMODEL_RELAXED: - return "ld.\t%0,%1\\n\\t" - "dbar\t0x700\\n\\t"; + return TARGET_LD_SEQ_SA ? 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(unknown [IPv6:240e:358:1152:b00:dc73:854d:832e:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 1999E66B06; Fri, 17 Nov 2023 15:44:15 -0500 (EST) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: chenglulu , i@xen0n.name, xuchenghua@loongson.cn, Xi Ruoyao Subject: [PATCH v2 6/6] LoongArch: Add fine-grained control for LAM_BH and LAMCAS Date: Sat, 18 Nov 2023 04:43:23 +0800 Message-ID: <20231117204323.453536-7-xry111@xry111.site> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231117204323.453536-1-xry111@xry111.site> References: <20231117204323.453536-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782845448057099354 X-GMAIL-MSGID: 1782845448057099354 gcc/ChangeLog: * config/loongarch/genopts/isa-evolution.in: (lam-bh, lamcas): Add. * config/loongarch/loongarch-str.h: Regenerate. * config/loongarch/loongarch.opt: Regenerate. * config/loongarch/loongarch-cpucfg-map.h: Regenerate. * config/loongarch/loongarch-cpu.cc (ISA_BASE_LA64V110_FEATURES): Include OPTION_MASK_ISA_LAM_BH and OPTION_MASK_ISA_LAMCAS. * config/loongarch/sync.md (atomic_add): Use TARGET_LAM_BH instead of ISA_BASE_IS_LA64V110. Remove empty lines from assembly output. (atomic_exchange_short): Likewise. (atomic_exchange): Likewise. (atomic_fetch_add_short): Likewise. (atomic_fetch_add): Likewise. (atomic_cas_value_strong_amcas): Use TARGET_LAMCAS instead of ISA_BASE_IS_LA64V110. (atomic_compare_and_swap): Likewise. (atomic_compare_and_swap): Likewise. (atomic_compare_and_swap): Likewise. * config/loongarch/loongarch.cc (loongarch_asm_code_end): Dump status if -mlam-bh and -mlamcas if -fverbose-asm. --- gcc/config/loongarch/genopts/isa-evolution.in | 2 ++ gcc/config/loongarch/loongarch-cpu.cc | 3 ++- gcc/config/loongarch/loongarch-cpucfg-map.h | 2 ++ gcc/config/loongarch/loongarch-str.h | 2 ++ gcc/config/loongarch/loongarch.cc | 2 ++ gcc/config/loongarch/loongarch.opt | 8 ++++++++ gcc/config/loongarch/sync.md | 18 +++++++++--------- 7 files changed, 27 insertions(+), 10 deletions(-) diff --git a/gcc/config/loongarch/genopts/isa-evolution.in b/gcc/config/loongarch/genopts/isa-evolution.in index e58f0d6a1a1..a6bc3f87f20 100644 --- a/gcc/config/loongarch/genopts/isa-evolution.in +++ b/gcc/config/loongarch/genopts/isa-evolution.in @@ -1,2 +1,4 @@ 2 26 div32 Support div.w[u] and mod.w[u] instructions with inputs not sign-extended. +2 27 lam-bh Support am{swap/add}[_db].{b/h} instructions. +2 28 lamcas Support amcas[_db].{b/h/w/d} instructions. 3 23 ld-seq-sa Do not need load-load barriers (dbar 0x700). diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc index 7acf1a9121d..622df47916f 100644 --- a/gcc/config/loongarch/loongarch-cpu.cc +++ b/gcc/config/loongarch/loongarch-cpu.cc @@ -38,7 +38,8 @@ along with GCC; see the file COPYING3. If not see initializers! */ #define ISA_BASE_LA64V110_FEATURES \ - (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA) + (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA \ + | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS) int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = { /* [ISA_BASE_LA64V100] = */ 0, diff --git a/gcc/config/loongarch/loongarch-cpucfg-map.h b/gcc/config/loongarch/loongarch-cpucfg-map.h index 0c078c39786..02ff1671255 100644 --- a/gcc/config/loongarch/loongarch-cpucfg-map.h +++ b/gcc/config/loongarch/loongarch-cpucfg-map.h @@ -30,6 +30,8 @@ static constexpr struct { HOST_WIDE_INT isa_evolution_bit; } cpucfg_map[] = { { 2, 1u << 26, OPTION_MASK_ISA_DIV32 }, + { 2, 1u << 27, OPTION_MASK_ISA_LAM_BH }, + { 2, 1u << 28, OPTION_MASK_ISA_LAMCAS }, { 3, 1u << 23, OPTION_MASK_ISA_LD_SEQ_SA }, }; diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h index 889962e9ab0..0384493765c 100644 --- a/gcc/config/loongarch/loongarch-str.h +++ b/gcc/config/loongarch/loongarch-str.h @@ -70,6 +70,8 @@ along with GCC; see the file COPYING3. If not see #define STR_EXPLICIT_RELOCS_ALWAYS "always" #define OPTSTR_DIV32 "div32" +#define OPTSTR_LAM_BH "lam-bh" +#define OPTSTR_LAMCAS "lamcas" #define OPTSTR_LD_SEQ_SA "ld-seq-sa" #endif /* LOONGARCH_STR_H */ diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 5d3282c5e93..46a898b79b7 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -11451,6 +11451,8 @@ loongarch_asm_code_end (void) fprintf (asm_out_file, "%s Base ISA: %s\n", ASM_COMMENT_START, loongarch_isa_base_strings [la_target.isa.base]); DUMP_FEATURE (TARGET_DIV32); + DUMP_FEATURE (TARGET_LAM_BH); + DUMP_FEATURE (TARGET_LAMCAS); DUMP_FEATURE (TARGET_LD_SEQ_SA); } diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt index a39eddc108b..4d36e3ec4de 100644 --- a/gcc/config/loongarch/loongarch.opt +++ b/gcc/config/loongarch/loongarch.opt @@ -267,6 +267,14 @@ mdiv32 Target Mask(ISA_DIV32) Var(isa_evolution) Support div.w[u] and mod.w[u] instructions with inputs not sign-extended. +mlam-bh +Target Mask(ISA_LAM_BH) Var(isa_evolution) +Support am{swap/add}[_db].{b/h} instructions. + +mlamcas +Target Mask(ISA_LAMCAS) Var(isa_evolution) +Support amcas[_db].{b/h/w/d} instructions. + mld-seq-sa Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution) Do not need load-load barriers (dbar 0x700). diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md index ce3ce89a61d..229fc50360a 100644 --- a/gcc/config/loongarch/sync.md +++ b/gcc/config/loongarch/sync.md @@ -124,7 +124,7 @@ (define_insn "atomic_load" return "ld.\t%0,%1\\n\\t" "dbar\t0x14"; case MEMMODEL_RELAXED: - return TARGET_LD_SEQ_SA ? "ld.\t%0,%1\\n\\t" + return TARGET_LD_SEQ_SA ? "ld.\t%0,%1" : "ld.\t%0,%1\\n\\t" "dbar\t0x700"; @@ -193,7 +193,7 @@ (define_insn "atomic_add" (match_operand:SHORT 1 "reg_or_0_operand" "rJ")) (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "ISA_BASE_IS_LA64V110" + "TARGET_LAM_BH" "amadd%A2.\t$zero,%z1,%0" [(set (attr "length") (const_int 4))]) @@ -230,7 +230,7 @@ (define_insn "atomic_exchange_short" UNSPEC_SYNC_EXCHANGE)) (set (match_dup 1) (match_operand:SHORT 2 "register_operand" "r"))] - "ISA_BASE_IS_LA64V110" + "TARGET_LAM_BH" "amswap%A3.\t%0,%z2,%1" [(set (attr "length") (const_int 4))]) @@ -266,7 +266,7 @@ (define_insn "atomic_cas_value_strong_amcas" (match_operand:QHWD 3 "reg_or_0_operand" "rJ") (match_operand:SI 4 "const_int_operand")] ;; mod_s UNSPEC_COMPARE_AND_SWAP))] - "ISA_BASE_IS_LA64V110" + "TARGET_LAMCAS" "ori\t%0,%z2,0\n\tamcas%A4.\t%0,%z3,%1" [(set (attr "length") (const_int 8))]) @@ -296,7 +296,7 @@ (define_expand "atomic_compare_and_swap" operands[6] = mod_s; - if (ISA_BASE_IS_LA64V110) + if (TARGET_LAMCAS) emit_insn (gen_atomic_cas_value_strong_amcas (operands[1], operands[2], operands[3], operands[4], operands[6])); @@ -422,7 +422,7 @@ (define_expand "atomic_compare_and_swap" operands[6] = mod_s; - if (ISA_BASE_IS_LA64V110) + if (TARGET_LAMCAS) emit_insn (gen_atomic_cas_value_strong_amcas (operands[1], operands[2], operands[3], operands[4], operands[6])); @@ -642,7 +642,7 @@ (define_expand "atomic_exchange" (match_operand:SHORT 2 "register_operand"))] "" { - if (ISA_BASE_IS_LA64V110) + if (TARGET_LAM_BH) emit_insn (gen_atomic_exchange_short (operands[0], operands[1], operands[2], operands[3])); else { @@ -663,7 +663,7 @@ (define_insn "atomic_fetch_add_short" (match_operand:SHORT 2 "reg_or_0_operand" "rJ")) (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] - "ISA_BASE_IS_LA64V110" + "TARGET_LAM_BH" "amadd%A3.\t%0,%z2,%1" [(set (attr "length") (const_int 4))]) @@ -678,7 +678,7 @@ (define_expand "atomic_fetch_add" UNSPEC_SYNC_OLD_OP))] "" { - if (ISA_BASE_IS_LA64V110) + if (TARGET_LAM_BH) emit_insn (gen_atomic_fetch_add_short (operands[0], operands[1], operands[2], operands[3])); else