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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id c11-20020a05640227cb00b0045c3f5b458fsi19010267ede.397.2022.11.09.05.55.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Nov 2022 05:55:15 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ITvWaGfa; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3903C3887F58 for ; Wed, 9 Nov 2022 13:54:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3903C3887F58 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668002075; bh=RggD1Vm/Jdi0f7jbQ5OReSxaGHia3RrXeR/9/dOlaWc=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=ITvWaGfaB+GwvOeaWVJwvsylS6Aq8hZlQ0R/JocLMk6c3YGQXUrO+XHKyWLuz5tXE pbqkuAPN6CobJigKPdVJ+BVJBUhgGJBifjYiKHXvx04kL4d7J8gMSV6E1hyvBDIbCj 9Z975vnYV40m9EFH5wJgSmrNXN5HfTsZ0hRnyzF4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [IPv6:2001:470:683e::1]) by sourceware.org (Postfix) with ESMTPS id 279223858434 for ; Wed, 9 Nov 2022 13:53:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 279223858434 Received: from xry111-x57s1.. (unknown [IPv6:240e:358:113a:1300:dc73:854d:832e:2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 88EA166887; Wed, 9 Nov 2022 08:53:45 -0500 (EST) To: gcc-patches@gcc.gnu.org Cc: Lulu Cheng , Wang Xuerui , Chenghua Xu , Xiaolin Tang , Xi Ruoyao Subject: [PATCH v2 1/4] LoongArch: Rename frint_ to rint2 Date: Wed, 9 Nov 2022 21:53:26 +0800 Message-Id: <20221109135329.952128-2-xry111@xry111.site> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221109135329.952128-1-xry111@xry111.site> References: <20221109135329.952128-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FROM_SUSPICIOUS_NTLD, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, LIKELY_SPAM_FROM, PDS_OTHER_BAD_TLD, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Xi Ruoyao via Gcc-patches From: Xi Ruoyao Reply-To: Xi Ruoyao Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749026986113257058?= X-GMAIL-MSGID: =?utf-8?q?1749026986113257058?= Use standard name so __builtin_rint{,f} can be expanded to one instruction. gcc/ChangeLog: * config/loongarch/loongarch.md (frint_): Rename to .. (rint2): .. this. gcc/testsuite/ChangeLog: * gcc.target/loongarch/frint.c: New test. --- gcc/config/loongarch/loongarch.md | 4 ++-- gcc/testsuite/gcc.target/loongarch/frint.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/frint.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index bda34d0f3db..a14ab14ac24 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -2012,8 +2012,8 @@ (define_insn "lui_h_hi12" [(set_attr "type" "move")] ) -;; Convert floating-point numbers to integers -(define_insn "frint_" +;; Round floating-point numbers to integers +(define_insn "rint2" [(set (match_operand:ANYF 0 "register_operand" "=f") (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] UNSPEC_FRINT))] diff --git a/gcc/testsuite/gcc.target/loongarch/frint.c b/gcc/testsuite/gcc.target/loongarch/frint.c new file mode 100644 index 00000000000..3ee6a8f973a --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/frint.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mdouble-float" } */ +/* { dg-final { scan-assembler "frint\\.s" } } */ +/* { dg-final { scan-assembler "frint\\.d" } } */ + +double +my_rint (double a) +{ + return __builtin_rint (a); +} + +float +my_rintf (float a) +{ + return __builtin_rintf (a); +} From patchwork Wed Nov 9 13:53:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 17557 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp345902wru; Wed, 9 Nov 2022 05:57:09 -0800 (PST) X-Google-Smtp-Source: AMsMyM4nV4FBbsPO+h+hdXVpPL2CJmfo0PDA5ZoXZs4ZKgRBdsYNTs64Cy9KF2q6gKYX6ojF42Lc X-Received: by 2002:a17:906:847b:b0:7a6:2ad9:298 with SMTP id hx27-20020a170906847b00b007a62ad90298mr56252871ejc.90.1668002229160; Wed, 09 Nov 2022 05:57:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668002229; cv=none; d=google.com; s=arc-20160816; b=BjwS4c9c8werXK7uKtuehQ4SOg/G1DPYeVMBMeLZMm9RqlXlbG0vgvhIrDuS5o7pQ5 PJATlVHtgxqKHivC2QBFE7I+3Elm3+Vq71P0m9AjSv9AjOKuLDjXSlXNUa3KaePwXdXR fPgam9b6fbbuc2/LHwru2WSTSIq6OLoiwH0id6b8WBhl2TunTHmQCHKnLWRXX/nKTNA2 cT8ubXeDf3R5GpsWJLZTcSpQXb6HvT7Iq2TBIxGzI/otca7vA52FbxxW4O19h7/zWT7P jg65njnf2GLJF1PwFN4PnIAyi9N+ejDpOndERKc19JZ+eDGftBjUQ8M3VC2fkoR9RGq+ Q4WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=DMipL7rxOzVosuk9NRnZ+oEAxYgB/UClPJaveKENBLE=; b=VdR7I2Ya8PuJ/FlriPdlNwlcBrphrAb5xn3ZaGVfMuzQiGOw146Xy99qfU1VzEOdgG k+W/IsWwh38U68xVt/t7NhzVA/tjN1o7FC2b1T2K/otmmey6nOtinCDaBdiVFvr64bEa ZfknE9Q7Cw0fu8pJ8TtBjLRpPy0Un3H5M0z6reO18bGco21PZU+GUJALEo9GWv9nxem/ z23Ufx6leTHvUt+chw/QXrkItpKjq12Ib6CoPHCYpgkZs3aP8pNJ1xKC8cCuPvGNmnpn o+bYXB/ynpX2qS53lOxTPZnRnMl92Fpa/gKIcygMnN5vcv2wfff1DK4/0d5SoszoxDbf +68g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Q9v9Ok7V; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. 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(unknown [IPv6:240e:358:113a:1300:dc73:854d:832e:2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 0A57E66888; Wed, 9 Nov 2022 08:53:49 -0500 (EST) To: gcc-patches@gcc.gnu.org Cc: Lulu Cheng , Wang Xuerui , Chenghua Xu , Xiaolin Tang , Xi Ruoyao Subject: [PATCH v2 2/4] LoongArch: Add ftint{,rm,rp}.{w,l}.{s,d} instructions Date: Wed, 9 Nov 2022 21:53:27 +0800 Message-Id: <20221109135329.952128-3-xry111@xry111.site> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221109135329.952128-1-xry111@xry111.site> References: <20221109135329.952128-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FROM_SUSPICIOUS_NTLD, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, PDS_OTHER_BAD_TLD, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Xi Ruoyao via Gcc-patches From: Xi Ruoyao Reply-To: Xi Ruoyao Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749027105320204535?= X-GMAIL-MSGID: =?utf-8?q?1749027105320204535?= This allows to optimize the following builtins if -fno-math-errno: - __builtin_lrint{,f} - __builtin_lfloor{,f} - __builtin_lceil{,f} Inspired by https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605287.html. ANYFI is added so the compiler won't try ftint.l.s if -mfpu=32. If we simply used GPR here an ICE would be triggered with __builtin_lrintf and -mfpu=32. ftint{rm,rp} instructions may raise inexact exception, so they can't be used if -fno-trapping-math -fno-fp-int-builtin-inexact. Note that the .w.{s,d} variants are not tested because we don't support ILP32 for now. gcc/ChangeLog: * config/loongarch/loongarch.md (UNSPEC_FTINT): New unspec. (UNSPEC_FTINTRM): Likewise. (UNSPEC_FTINTRP): Likewise. (LRINT): New define_int_iterator. (lrint_pattern): New define_int_attr. (lrint_submenmonic): Likewise. (lrint_allow_inexact): Likewise. (ANYFI): New define_mode_iterator. (lrint): New instruction template. gcc/testsuite/ChangeLog: * gcc.target/loongarch/ftint.c: New test. * gcc.target/loongarch/ftint-no-inexact.c: New test. --- gcc/config/loongarch/loongarch.md | 34 ++++++++++++++ .../gcc.target/loongarch/ftint-no-inexact.c | 44 +++++++++++++++++++ gcc/testsuite/gcc.target/loongarch/ftint.c | 44 +++++++++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c create mode 100644 gcc/testsuite/gcc.target/loongarch/ftint.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index a14ab14ac24..eb127c346a3 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -38,6 +38,9 @@ (define_c_enum "unspec" [ UNSPEC_FMAX UNSPEC_FMIN UNSPEC_FCOPYSIGN + UNSPEC_FTINT + UNSPEC_FTINTRM + UNSPEC_FTINTRP ;; Override return address for exception handling. UNSPEC_EH_RETURN @@ -374,6 +377,11 @@ (define_mode_iterator QHWD [QI HI SI (DI "TARGET_64BIT")]) (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") (DF "TARGET_DOUBLE_FLOAT")]) +;; Iterator for fixed-point modes which can be hold by a hardware +;; floating-point register. +(define_mode_iterator ANYFI [(SI "TARGET_HARD_FLOAT") + (DI "TARGET_DOUBLE_FLOAT")]) + ;; A mode for which moves involving FPRs may need to be split. (define_mode_iterator SPLITF [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") @@ -515,6 +523,19 @@ (define_code_attr fcond [(unordered "cun") (define_code_attr sel [(eq "masknez") (ne "maskeqz")]) (define_code_attr selinv [(eq "maskeqz") (ne "masknez")]) +;; Iterator and attributes for floating-point to fixed-point conversion +;; instructions. +(define_int_iterator LRINT [UNSPEC_FTINT UNSPEC_FTINTRM UNSPEC_FTINTRP]) +(define_int_attr lrint_pattern [(UNSPEC_FTINT "lrint") + (UNSPEC_FTINTRM "lfloor") + (UNSPEC_FTINTRP "lceil")]) +(define_int_attr lrint_submenmonic [(UNSPEC_FTINT "") + (UNSPEC_FTINTRM "rm") + (UNSPEC_FTINTRP "rp")]) +(define_int_attr lrint_allow_inexact [(UNSPEC_FTINT "1") + (UNSPEC_FTINTRM "0") + (UNSPEC_FTINTRP "0")]) + ;; ;; .................... ;; @@ -2022,6 +2043,19 @@ (define_insn "rint2" [(set_attr "type" "fcvt") (set_attr "mode" "")]) +;; Convert floating-point numbers to integers +(define_insn "2" + [(set (match_operand:ANYFI 0 "register_operand" "=f") + (unspec:ANYFI [(match_operand:ANYF 1 "register_operand" "f")] + LRINT))] + "TARGET_HARD_FLOAT && + ( + || flag_fp_int_builtin_inexact + || !flag_trapping_math)" + "ftint.. %0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "")]) + ;; Load the low word of operand 0 with operand 1. (define_insn "load_low" [(set (match_operand:SPLITF 0 "register_operand" "=f,f") diff --git a/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c b/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c new file mode 100644 index 00000000000..88b83a9c056 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=lp64d -mdouble-float -fno-math-errno -fno-fp-int-builtin-inexact" } */ +/* { dg-final { scan-assembler "ftint\\.l\\.s" } } */ +/* { dg-final { scan-assembler "ftint\\.l\\.d" } } */ +/* { dg-final { scan-assembler-not "ftintrm\\.l\\.s" } } */ +/* { dg-final { scan-assembler-not "ftintrm\\.l\\.d" } } */ +/* { dg-final { scan-assembler-not "ftintrp\\.l\\.s" } } */ +/* { dg-final { scan-assembler-not "ftintrp\\.l\\.d" } } */ + +long +my_lrint (double a) +{ + return __builtin_lrint (a); +} + +long +my_lrintf (float a) +{ + return __builtin_lrintf (a); +} + +long +my_lfloor (double a) +{ + return __builtin_lfloor (a); +} + +long +my_lfloorf (float a) +{ + return __builtin_lfloorf (a); +} + +long +my_lceil (double a) +{ + return __builtin_lceil (a); +} + +long +my_lceilf (float a) +{ + return __builtin_lceilf (a); +} diff --git a/gcc/testsuite/gcc.target/loongarch/ftint.c b/gcc/testsuite/gcc.target/loongarch/ftint.c new file mode 100644 index 00000000000..7a326a454d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/ftint.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=lp64d -mdouble-float -fno-math-errno -ffp-int-builtin-inexact" } */ +/* { dg-final { scan-assembler "ftint\\.l\\.s" } } */ +/* { dg-final { scan-assembler "ftint\\.l\\.d" } } */ +/* { dg-final { scan-assembler "ftintrm\\.l\\.s" } } */ +/* { dg-final { scan-assembler "ftintrm\\.l\\.d" } } */ +/* { dg-final { scan-assembler "ftintrp\\.l\\.s" } } */ +/* { dg-final { scan-assembler "ftintrp\\.l\\.d" } } */ + +long +my_lrint (double a) +{ + return __builtin_lrint (a); +} + +long +my_lrintf (float a) +{ + return __builtin_lrintf (a); +} + +long +my_lfloor (double a) +{ + return __builtin_lfloor (a); +} + +long +my_lfloorf (float a) +{ + return __builtin_lfloorf (a); +} + +long +my_lceil (double a) +{ + return __builtin_lceil (a); +} + +long +my_lceilf (float a) +{ + return __builtin_lceilf (a); +} From patchwork Wed Nov 9 13:53:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 17554 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp345190wru; Wed, 9 Nov 2022 05:55:40 -0800 (PST) X-Google-Smtp-Source: AA0mqf4YoBToVUjsHO3ftl6za1PY6WEAHtSr9zgf60fyKdkS+Hn1UrJd9GQMqjQ/3aiDviBhIpWc X-Received: by 2002:a17:906:a059:b0:7ae:9fc4:28ee with SMTP id bg25-20020a170906a05900b007ae9fc428eemr597589ejb.407.1668002140422; Wed, 09 Nov 2022 05:55:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668002140; cv=none; d=google.com; s=arc-20160816; b=nC9im382Syt42/1rN4pAia4hyxD3exGGhwPD9uwK3gLCuWaCX0Zq1ZbPT7CfRblLUV 8mwkQ5slg+HwZO2SEZuzET1MZ5GdtbpC4lTyLahz7T9LjkR2ARfXxFQW7IuXtL1NS1ax fhYt1oxRk2ykNopKBtagAtP1W9WUnKQIx56xlNz32RwFPFtIj83gbnQH1XCLzy8ywknd hjMXJynD8NTr8OOTR99B3OGVDyrfM10xL1oga7gj+N1zf7MNBbDsqEhlaKBo90EZunTP ZBMqX6CWsORUFHiNy7vV0um7whVco9io4iPFV1YWfp6Z67yaJgekdbh5ZAOy/BAj8wqe s3Kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=/HhmholP03x/SwIqP1eH4tGwCqOJIPT08IEWtpb7FLM=; b=meT8LjmVkpOBosZzDL7xMlCe5/MKWoBENVfLjAhywca9NH+TIAOnL9/Q2hboW0nI8s t8XsrXYeoXO9lAic4EN5wr38srOY7Q0v9Nvt1XPSheZKZtbxw/Do0WJGZsyMXTSvWwlx yzb0P9p9NnR5m+Z8Z+A5ScLaI0akFsGTntbEZiXHzP5niIXyj4nH95xaUBQXwupCirmA tpcQIcdqETxUlJ7YuZbFZHQpZjkUfGA5t6Hu7hWIWjCqTPvhJDDOykvV6dfnQXfT1pkX +PooFPnogNvRgYecenF59RlPkGJSdIZz/M7R0x1OWSJHHe5popLOZCM0Lvx2q9qaXcfL XbjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ApGSWQUS; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id s6-20020a056402520600b00461d2ed78afsi19912559edd.563.2022.11.09.05.55.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Nov 2022 05:55:40 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ApGSWQUS; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4FFB43887F6D for ; Wed, 9 Nov 2022 13:54:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4FFB43887F6D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668002088; bh=/HhmholP03x/SwIqP1eH4tGwCqOJIPT08IEWtpb7FLM=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=ApGSWQUS2gM2o5lFfvc31OhyC3AVsKGPUs6FqLw8l9L85ccnA+1jkXuacOdD6wyKE G3wq9Vdt0jLAtJQwxLvqxDI4oJSuntlnF3S+Lktq34ymxEe8rfJXynEkt6Puk2rt8R CEYeY5xEQSXau3LdgWY9p4cn419AF/nT3bAMnI5s= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [IPv6:2001:470:683e::1]) by sourceware.org (Postfix) with ESMTPS id 60E123858C2F for ; Wed, 9 Nov 2022 13:54:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 60E123858C2F Received: from xry111-x57s1.. (unknown [IPv6:240e:358:113a:1300:dc73:854d:832e:2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 5E47B66887; Wed, 9 Nov 2022 08:53:55 -0500 (EST) To: gcc-patches@gcc.gnu.org Cc: Lulu Cheng , Wang Xuerui , Chenghua Xu , Xiaolin Tang , Xi Ruoyao Subject: [PATCH v2 3/4] LoongArch: Add fscaleb.{s, d} instructions as ldexp{sf, df}3 Date: Wed, 9 Nov 2022 21:53:28 +0800 Message-Id: <20221109135329.952128-4-xry111@xry111.site> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221109135329.952128-1-xry111@xry111.site> References: <20221109135329.952128-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FROM_SUSPICIOUS_NTLD, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, LIKELY_SPAM_FROM, PDS_OTHER_BAD_TLD, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Xi Ruoyao via Gcc-patches From: Xi Ruoyao Reply-To: Xi Ruoyao Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749027012575733079?= X-GMAIL-MSGID: =?utf-8?q?1749027012575733079?= This allows optimizing __builtin_ldexp{,f} and __builtin_scalbn{,f} with -fno-math-errno. IMODE is added because we can't hard code SI for operand 2: fscaleb.d instruction always take the high half of both source registers into account. See my_ldexp_long in the test case. gcc/ChangeLog: * config/loongarch/loongarch.md (UNSPEC_FSCALEB): New unspec. (type): Add fscaleb. (IMODE): New mode attr. (ldexp3): New instruction template. gcc/testsuite/ChangeLog: * gcc.target/loongarch/fscaleb.c: New test. --- gcc/config/loongarch/loongarch.md | 26 ++++++++++- gcc/testsuite/gcc.target/loongarch/fscaleb.c | 48 ++++++++++++++++++++ 2 files changed, 72 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/fscaleb.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index eb127c346a3..c141c9adde2 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -41,6 +41,7 @@ (define_c_enum "unspec" [ UNSPEC_FTINT UNSPEC_FTINTRM UNSPEC_FTINTRP + UNSPEC_FSCALEB ;; Override return address for exception handling. UNSPEC_EH_RETURN @@ -220,6 +221,7 @@ (define_attr "qword_mode" "no,yes" ;; fcmp floating point compare ;; fcopysign floating point copysign ;; fcvt floating point convert +;; fscaleb floating point scale ;; fsqrt floating point square root ;; frsqrt floating point reciprocal square root ;; multi multiword sequence (or user asm statements) @@ -231,8 +233,8 @@ (define_attr "type" "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, prefetch,prefetchx,condmove,mgtf,mftg,const,arith,logical, shift,slt,signext,clz,trap,imul,idiv,move, - fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fsqrt, - frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost" + fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fscaleb, + fsqrt,frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost" (cond [(eq_attr "jirl" "!unset") (const_string "call") (eq_attr "got" "load") (const_string "load") @@ -418,6 +420,10 @@ (define_mode_attr UNITMODE [(SF "SF") (DF "DF")]) ;; the controlling mode. (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")]) +;; This attribute gives the integer mode that has the same size of a +;; floating-point mode. +(define_mode_attr IMODE [(SF "SI") (DF "DI")]) + ;; This code iterator allows signed and unsigned widening multiplications ;; to use the same template. (define_code_iterator any_extend [sign_extend zero_extend]) @@ -1014,7 +1020,23 @@ (define_insn "copysign3" "fcopysign.\t%0,%1,%2" [(set_attr "type" "fcopysign") (set_attr "mode" "")]) + +;; +;; .................... +;; +;; FLOATING POINT SCALE +;; +;; .................... +(define_insn "ldexp3" + [(set (match_operand:ANYF 0 "register_operand" "=f") + (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") + (match_operand: 2 "register_operand" "f")] + UNSPEC_FSCALEB))] + "TARGET_HARD_FLOAT" + "fscaleb.\t%0,%1,%2" + [(set_attr "type" "fscaleb") + (set_attr "mode" "")]) ;; ;; ................... diff --git a/gcc/testsuite/gcc.target/loongarch/fscaleb.c b/gcc/testsuite/gcc.target/loongarch/fscaleb.c new file mode 100644 index 00000000000..f18470fbb8f --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/fscaleb.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabi=lp64d -mdouble-float -fno-math-errno" } */ +/* { dg-final { scan-assembler-times "fscaleb\\.s" 3 } } */ +/* { dg-final { scan-assembler-times "fscaleb\\.d" 4 } } */ +/* { dg-final { scan-assembler-times "slli\\.w" 1 } } */ + +double +my_scalbln (double a, long b) +{ + return __builtin_scalbln (a, b); +} + +double +my_scalbn (double a, int b) +{ + return __builtin_scalbn (a, b); +} + +double +my_ldexp (double a, int b) +{ + return __builtin_ldexp (a, b); +} + +float +my_scalblnf (float a, long b) +{ + return __builtin_scalblnf (a, b); +} + +float +my_scalbnf (float a, int b) +{ + return __builtin_scalbnf (a, b); +} + +float +my_ldexpf (float a, int b) +{ + return __builtin_ldexpf (a, b); +} + +/* b must be sign-extended */ +double +my_ldexp_long (double a, long b) +{ + return __builtin_ldexp (a, b); +} From patchwork Wed Nov 9 13:53:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 17558 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp346166wru; Wed, 9 Nov 2022 05:57:50 -0800 (PST) X-Google-Smtp-Source: AMsMyM730rqhcxbFFluIAZIlK8bUwv0VuVVPsS9Aq2k0xwweocfrXjoLyiqX4Ao0ahFMdepd4ix1 X-Received: by 2002:a17:907:1b24:b0:76d:7b9d:2f8b with SMTP id mp36-20020a1709071b2400b0076d7b9d2f8bmr55964678ejc.414.1668002270617; Wed, 09 Nov 2022 05:57:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668002270; cv=none; d=google.com; s=arc-20160816; b=um3UoghUfSbWFqHo+DaU+aerl7SohQjIAH9XpyvcwdwNT++dyl+PwDlP6o2/vUe4w7 GvKq0lPZ4CQfXtJMyE1dRCGfYlzB/4QVMIJu9cJpeGI/qFIHrU+ac7GcLfV3eZXlnknQ xaoUv9N8vbYSRQU6kva5r/eZzyveteN5DMggAnP2J/f3zatQ0CQt9N9CX0AB+Ib5RTVI aQMHA+SPvQjBE8fKeQBy5FAJ76Sj4U4cxR0Am5chQhuJumaeBIN5GEknhenMGwSmLwEB vqbzk47SNGTQVhU5XuHHCSho8cuD7rWq6DOVUOw00GgweJfTpNZTBlfZcvr4MV2vQNC6 uvyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=mu2j23TrABHjBfieg/G9m3r3ghPsjCcVCvkE2yYqpok=; b=jeGwnC77AUSbMz3i3sOy9o0YNFFlI16+PwjnQ8go3P6EuxQdRNsUvfSfq3kTHU5j8N ZrBHgiz8hkal4H3QjPSSQ46uIeNGWgDR2pm8aJLW06EEliiMn9k0djKfaVfQOACsYBgS 5UivcpGUuV/8YCEKNijTnCliyktzsq7U8+oZ8OiBYZPmilILJLVvFsHBkAWm3VWI5j8D 1apJWyE2uUFyDbJOFX/CghCb5EyjHKr5LdPYKRtKRy6t1Y3H3xDuJ5icuaIpCSYQ6v3t SIYDW8+AQts/5r+EIysMnf1esiK/X0++CjpcgrWazWkYpsyvrzslhbuotC1/rRybNsbS /fpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="tG//UVl+"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. 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(unknown [IPv6:240e:358:113a:1300:dc73:854d:832e:2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 7196166888; Wed, 9 Nov 2022 08:54:02 -0500 (EST) To: gcc-patches@gcc.gnu.org Cc: Lulu Cheng , Wang Xuerui , Chenghua Xu , Xiaolin Tang , Xi Ruoyao Subject: [PATCH v2 4/4] LoongArch: Add flogb.{s, d} instructions and expand logb{sf, df}2 Date: Wed, 9 Nov 2022 21:53:29 +0800 Message-Id: <20221109135329.952128-5-xry111@xry111.site> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221109135329.952128-1-xry111@xry111.site> References: <20221109135329.952128-1-xry111@xry111.site> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FROM_SUSPICIOUS_NTLD, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, LIKELY_SPAM_FROM, PDS_OTHER_BAD_TLD, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Xi Ruoyao via Gcc-patches From: Xi Ruoyao Reply-To: Xi Ruoyao Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749027148602327655?= X-GMAIL-MSGID: =?utf-8?q?1749027148602327655?= On LoongArch, flogb instructions extract the exponent of a non-negative floating point value, but produces NaN for negative values. So we need to add a fabs instruction when we expand logb. gcc/ChangeLog: * config/loongarch/loongarch.md (UNSPEC_FLOGB): New unspec. (type): Add flogb. (logb_non_negative2): New instruction template. (logb2): New define_expand. gcc/testsuite/ChangeLog: * gcc.target/loongarch/flogb.c: New test. --- gcc/config/loongarch/loongarch.md | 35 ++++++++++++++++++++-- gcc/testsuite/gcc.target/loongarch/flogb.c | 18 +++++++++++ 2 files changed, 51 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/flogb.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index c141c9adde2..682ab961741 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -42,6 +42,7 @@ (define_c_enum "unspec" [ UNSPEC_FTINTRM UNSPEC_FTINTRP UNSPEC_FSCALEB + UNSPEC_FLOGB ;; Override return address for exception handling. UNSPEC_EH_RETURN @@ -217,6 +218,7 @@ (define_attr "qword_mode" "no,yes" ;; fdiv floating point divide ;; frdiv floating point reciprocal divide ;; fabs floating point absolute value +;; flogb floating point exponent extract ;; fneg floating point negation ;; fcmp floating point compare ;; fcopysign floating point copysign @@ -233,8 +235,8 @@ (define_attr "type" "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, prefetch,prefetchx,condmove,mgtf,mftg,const,arith,logical, shift,slt,signext,clz,trap,imul,idiv,move, - fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fscaleb, - fsqrt,frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost" + fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,flogb,fneg,fcmp,fcopysign,fcvt, + fscaleb,fsqrt,frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost" (cond [(eq_attr "jirl" "!unset") (const_string "call") (eq_attr "got" "load") (const_string "load") @@ -1039,6 +1041,35 @@ (define_insn "ldexp3" (set_attr "mode" "")]) ;; +;; .................... +;; +;; FLOATING POINT EXPONENT EXTRACT +;; +;; .................... + +(define_insn "logb_non_negative2" + [(set (match_operand:ANYF 0 "register_operand" "=f") + (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] + UNSPEC_FLOGB))] + "TARGET_HARD_FLOAT" + "flogb.\t%0,%1" + [(set_attr "type" "flogb") + (set_attr "mode" "")]) + +(define_expand "logb2" + [(set (match_operand:ANYF 0 "register_operand") + (unspec:ANYF [(abs:ANYF (match_operand:ANYF 1 "register_operand"))] + UNSPEC_FLOGB))] + "TARGET_HARD_FLOAT" +{ + rtx tmp = gen_reg_rtx (mode); + + emit_insn (gen_abs2 (tmp, operands[1])); + emit_insn (gen_logb_non_negative2 (operands[0], tmp)); + DONE; +}) + +;; ;; ................... ;; ;; Count leading zeroes. diff --git a/gcc/testsuite/gcc.target/loongarch/flogb.c b/gcc/testsuite/gcc.target/loongarch/flogb.c new file mode 100644 index 00000000000..1daefe54e13 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/flogb.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mdouble-float -fno-math-errno" } */ +/* { dg-final { scan-assembler "fabs\\.s" } } */ +/* { dg-final { scan-assembler "fabs\\.d" } } */ +/* { dg-final { scan-assembler "flogb\\.s" } } */ +/* { dg-final { scan-assembler "flogb\\.d" } } */ + +double +my_logb (double a) +{ + return __builtin_logb (a); +} + +float +my_logbf (float a) +{ + return __builtin_logbf (a); +}