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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id et14-20020a056214176e00b00677acf81975si919747qvb.512.2023.11.16.21.13.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Nov 2023 21:13:32 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9043D3858422 for ; Fri, 17 Nov 2023 05:13:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [20.231.56.155]) by sourceware.org (Postfix) with ESMTP id ED1FA3858D32 for ; Fri, 17 Nov 2023 05:13:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ED1FA3858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org ED1FA3858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=20.231.56.155 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700197985; cv=none; b=Rsr0FHxOehWlCWZ9tfP5KcP8rjHlUtMolRh0JqB4COAwqF9E5XcD3/TZQqEmIAfF+lh5ARyaxKCD0WEGFM2dVLwvlRsuUyAC/jF0whVEovRND08dQvSz0Y66aV3dKLc97LjWVffTcxR7YV7wwvI5D0XZYJNGGhjmqBDDe0B9n0E= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700197985; c=relaxed/simple; bh=bYmQwI65hbmP5QzVkUQqXiKLWG7ugeC/a4Yg0m8DKvY=; h=From:To:Subject:Date:Message-Id; b=LAfDYAIIziEm8UVGsrYFKY5oqg2qghSmiKoIznbhsu1sKUKoz12VHlI9G6sfAr7YhCIgqzHmvcZVwvyMjlXiWooqHZhBYRr/iLkA7RUFIZkwWCd+m7Z8lx9eWLU8KIdNx48v1Rtjvq1XxODI8senOfDtZ6BJdXcGLHygJTdLEW4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id TAJkCgCXcn8v9lZlWWAAAA--.2594S4; Fri, 17 Nov 2023 13:12:16 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, juzhe.zhong@rivai.ai, xuli Subject: [PATCH] RISC-V: Implement -mmemcpy-strategy= options[PR112537] Date: Fri, 17 Nov 2023 05:12:32 +0000 Message-Id: <20231117051232.10396-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TAJkCgCXcn8v9lZlWWAAAA--.2594S4 X-Coremail-Antispam: 1UD129KBjvJXoW3GryUCr1rKFWxZryftw13Jwb_yoW3uFy8pa yUCw4akrW8JFs7KwsavF1UJry5Gws3ur15u3s3Cr1UAayrJrWqqasIg3W7Aw43Wa1UCry7 uFnI9r15Cr1rtwUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782786831087575883 X-GMAIL-MSGID: 1782786831087575883 From: xuli https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112537 -mmemcpy-strategy=[auto|libcall|scalar|vector] auto: Current status, use scalar or vector instructions. libcall: Always use a library call. scalar: Only use scalar instructions. vector: Only use vector instructions. PR target/112537 gcc/ChangeLog: * config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum): Strategy enum. * config/riscv/riscv-string.cc (riscv_expand_block_move): Disabled based on options. (expand_block_move): Ditto. * config/riscv/riscv.opt: Add -mmemcpy-strategy=. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/cpymem-strategy-1.c: New test. * gcc.target/riscv/rvv/base/cpymem-strategy-2.c: New test. * gcc.target/riscv/rvv/base/cpymem-strategy-3.c: New test. * gcc.target/riscv/rvv/base/cpymem-strategy-4.c: New test. * gcc.target/riscv/rvv/base/cpymem-strategy-5.c: New test. * gcc.target/riscv/rvv/base/cpymem-strategy.h: New test. --- gcc/config/riscv/riscv-opts.h | 12 +++++++++++ gcc/config/riscv/riscv-string.cc | 7 ++++++- gcc/config/riscv/riscv.opt | 20 +++++++++++++++++++ .../riscv/rvv/base/cpymem-strategy-1.c | 6 ++++++ .../riscv/rvv/base/cpymem-strategy-2.c | 6 ++++++ .../riscv/rvv/base/cpymem-strategy-3.c | 6 ++++++ .../riscv/rvv/base/cpymem-strategy-4.c | 6 ++++++ .../riscv/rvv/base/cpymem-strategy-5.c | 6 ++++++ .../riscv/rvv/base/cpymem-strategy.h | 12 +++++++++++ 9 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy.h diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 532b1b6b84a..0b242f068e1 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -102,6 +102,18 @@ enum riscv_entity MAX_RISCV_ENTITIES }; +/* RISC-V stringop strategy. */ +enum riscv_stringop_strategy_enum { + /* Use scalar or vector instructions. */ + USE_AUTO, + /* Always use a library call. */ + USE_LIBCALL, + /* Only use scalar instructions. */ + USE_SCALAR, + /* Only use vector instructions. */ + USE_VECTOR +}; + #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT)) /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc index 57e8ad698d7..3b5e05e2c44 100644 --- a/gcc/config/riscv/riscv-string.cc +++ b/gcc/config/riscv/riscv-string.cc @@ -710,6 +710,10 @@ riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length, bool riscv_expand_block_move (rtx dest, rtx src, rtx length) { + if (riscv_memcpy_strategy == USE_LIBCALL + || riscv_memcpy_strategy == USE_VECTOR) + return false; + if (CONST_INT_P (length)) { unsigned HOST_WIDE_INT hwi_length = UINTVAL (length); @@ -773,7 +777,8 @@ expand_block_move (rtx dst_in, rtx src_in, rtx length_in) bnez a2, loop # Any more? ret # Return */ - if (!TARGET_VECTOR) + if (!TARGET_VECTOR || riscv_memcpy_strategy == USE_LIBCALL + || riscv_memcpy_strategy == USE_SCALAR) return false; HOST_WIDE_INT potential_ew = (MIN (MIN (MEM_ALIGN (src_in), MEM_ALIGN (dst_in)), BITS_PER_WORD) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 70d78151cee..4f3ce2233b2 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -527,3 +527,23 @@ Target Var(TARGET_ADJUST_LMUL_COST) Init(0) Target Undocumented Bool Var(riscv_vector_abi) Init(0) Enable the use of vector registers for function arguments and return value. This is an experimental switch and may be subject to change in the future. + +Enum +Name(riscv_stringop_strategy) Type(enum riscv_stringop_strategy_enum) +Valid arguments to -mmemcpy-strategy=: + +EnumValue +Enum(riscv_stringop_strategy) String(auto) Value(USE_AUTO) + +EnumValue +Enum(riscv_stringop_strategy) String(libcall) Value(USE_LIBCALL) + +EnumValue +Enum(riscv_stringop_strategy) String(scalar) Value(USE_SCALAR) + +EnumValue +Enum(riscv_stringop_strategy) String(vector) Value(USE_VECTOR) + +mmemcpy-strategy= +Target RejectNegative Joined Enum(riscv_stringop_strategy) Var(riscv_memcpy_strategy) Init(USE_AUTO) +Specify memcpy expansion strategy. diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-1.c new file mode 100644 index 00000000000..ae49706dca5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -mmemcpy-strategy=libcall" } */ + +#include "cpymem-strategy.h" + +/* { dg-final { scan-assembler-times {call\tmemcpy} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-2.c new file mode 100644 index 00000000000..73ffc5783d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gcv -mabi=ilp32d -mmemcpy-strategy=scalar" } */ + +#include "cpymem-strategy.h" + +/* { dg-final { scan-assembler-times {call\tmemcpy} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c new file mode 100644 index 00000000000..44f5f783962 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -mmemcpy-strategy=vector" } */ + +#include "cpymem-strategy.h" + +/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c new file mode 100644 index 00000000000..8056895334a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -mmemcpy-strategy=auto" } */ + +#include "cpymem-strategy.h" + +/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-5.c new file mode 100644 index 00000000000..82ecab04a40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -mmemcpy-strategy=vector" } */ + +#include "cpymem-strategy.h" + +/* { dg-final { scan-assembler-times {call\tmemcpy} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy.h b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy.h new file mode 100644 index 00000000000..700d224c01f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy.h @@ -0,0 +1,12 @@ +typedef struct { unsigned char a[56]; } a56; +typedef struct { int b[32]; } b32; + +void f1 (a56 *v1, a56 *v2) +{ + *v1 = *v2; +} + +void f2 (b32 *v1, b32 *v2) +{ + *v1 = *v2; +}