From patchwork Thu Nov 16 18:07:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Coplan X-Patchwork-Id: 165910 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6359:6513:b0:164:83eb:24d7 with SMTP id sk19csp41894rwb; Thu, 16 Nov 2023 10:07:48 -0800 (PST) X-Google-Smtp-Source: AGHT+IHp70DEZn6ayJoCtMWtWM5X3H6dibSulkyvXANa39VpCXaJ30VIrQ37gZ55wqGMsLoRoFtX X-Received: by 2002:a37:ef19:0:b0:777:27a5:d1e with SMTP id j25-20020a37ef19000000b0077727a50d1emr9012173qkk.41.1700158067622; Thu, 16 Nov 2023 10:07:47 -0800 (PST) ARC-Seal: i=4; a=rsa-sha256; t=1700158067; cv=pass; d=google.com; s=arc-20160816; b=MqNdLM+0PnApWNrEoBwQO8pQZc9/4pxRM7igm9Ks6pG8BOaT8W8YhPXLhZqNXLVIN2 nq2In/aa0NzqIDr9uJDZZyY0bgzetThgFw0H4tvgxsTplVZKq7OLIc98GcUbLdJftMRR /dI5llz2cTXWl74+0ad1xwC1OOWbDebKmIEsqklaABH8lBRoeegInDJoOsjv70YhKJyv xDbMPbZ5dBo4CtL2txw5NL5aUCnvn/Ashjy+hM/fFIUtP8Xw++8jT1Dl7a/0MVA52TPq +0HiOJQd6p9F9bGm2eFpeaH5L5AhhghoH20ljyWlKlAsUrYRr+R4e8ZqAPHqsdg9IxSb GMEQ== ARC-Message-Signature: i=4; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:original-authentication-results :nodisclaimer:mime-version:content-transfer-encoding :content-disposition:message-id:subject:cc:to:from:date :authentication-results-original:dkim-signature:dkim-signature :arc-filter:dmarc-filter:delivered-to; bh=PRUTHX9d+6OLzzfU5ld4LGePund9c6BKeSXUPeivWV0=; fh=oBREkWEOK+vBJwK/8m3Xyoxxy+JRDn9wOQNt/tlZ9u8=; b=kZMYBau/ur+Xc2FTJuGj5lq829COQuIRe3DqkSzX6yXYNrVPcWZ7wdnD965zVDiRjE LcUPkOdm+BR6PPcyYsG5Lfcqy0WTT/V6u0PpFQl9svbK83x7PFuIi+sqn+YpEBaZI+Z4 qCOpy5P3by1frj/yCoMZYBvO/U/9geZFyXRUe4ydIHiJeqUimIv4jhxF/39AZK7GMvgb I+vYCXiyJy/+n7nUKmwPhicBa/Uw9y2caB67hy+A5p2/Oyx784Ujm4i62aZpL8CJntvx NHhyAL6ePVb09pOZze46Hzm5QvbW5cKEAHyTA6NxKCqjQ7z2PezqclATBKJBRF1BPI9c 24Jg== ARC-Authentication-Results: i=4; mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b="zpK0K/BS"; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b="zpK0K/BS"; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id j9-20020a05620a288900b007740be11648si12057019qkp.38.2023.11.16.10.07.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Nov 2023 10:07:47 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b="zpK0K/BS"; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b="zpK0K/BS"; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1AC6A3856975 for ; Thu, 16 Nov 2023 18:07:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2043.outbound.protection.outlook.com [40.107.6.43]) by sourceware.org (Postfix) with ESMTPS id 9942A3875DD2 for ; Thu, 16 Nov 2023 18:07:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9942A3875DD2 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9942A3875DD2 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.6.43 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1700158041; cv=pass; b=KiQWnWKWtXXQ8infUWY0e2Qt59xKt/ccDhoBcef7Dc0gH6VxYqC90h6D6b+xfHUIHPXjgiqmHiTfg1OqqMlDSp/A3MV10TQTZnTF7BO0ps/r1Qa9+2IHVHnkldtbfBNp3TCrVyzidaTupEFjSRWmJcAmA09S2GZWtz/sJ+ofElM= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1700158041; c=relaxed/simple; bh=o7w+OzLe5Ys55K5crE6SrG/DXYiI9OurAoFawR+xGCM=; h=DKIM-Signature:DKIM-Signature:Date:From:To:Subject:Message-ID: MIME-Version; b=xcb+UK0hJplyKsiiolVwuF9CRoLtzA2bDQ32DtmKvb7+WAwEVlCsNP/C8REJPf8SUxZdcR7DWJ/hsFsl9XnLFcblQgDqlvxpVM6Br4JtoaGsDmDIeFsgtt4siSDdT5EEVrCnv04ja0ty1SScPGCWo2zvaUN9e71jFEL3lY90Xkc= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=kB0EmaYOXgh5kPHZ96sdQE7ci0ukF8mVEelyiPbSAp05m2OLI6JP8Tr2aeG1hnBA1AtY4xMMY1FEfi4kXjJkVvGDO60dxBHZ3eaxZQfGzepwLIEktLIdjgLJfndJTfVgTxYhk25xD80uN7aw1kY3v0rBdt2fYwkv8RXVwejvlAh07yLyoKeQZg0z4Pr9eDgqcYz/lTs3tAFhKYJVqZ/FRWCJBU7/k2yySmwNHfSAZvBLbuBizNEwFcNScV9os2VQGmUvw4LDJh6xld0YqfhrmpslZ4Bu+BCVd2jGq7PbT950hGxskhXQLpfBgoh0mOn8ktvf5PyAJGGahvfgnUQQag== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PRUTHX9d+6OLzzfU5ld4LGePund9c6BKeSXUPeivWV0=; b=GJwS59fXtKHaKaxr+h6zJTqhf1+fwyCZUlb6m3g3vozpeBFFQig5j4gGaAt4iVTRkyrn5yLIyKIi6YN53ITpTaTG1dNZnyuUpt2djo6NjhGC/doggXHt8w9VyR4pp0rHvzHaqdbsOnG9KSxnbWdYbPrSGqoET7lPJmHF38QM2qVl/g7slcTPSEFg/399a4QuqMsIVD2KLAJaj0NEwtFpKXDBhe/fkBwlruHZO9TUnR9Rry1agNRZuJCMft7qX8FMpF24/kvY85H0ietX7Cctiul+ARs/6VCudOmQGIvFDm2IFK8KVqxVlQH8VPRlclKFNSQAORZV14dpaiZUyJHOlg== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PRUTHX9d+6OLzzfU5ld4LGePund9c6BKeSXUPeivWV0=; b=zpK0K/BSRaLTrugYOrJqkrDidCYsOs2tX9ZrG2VOXJhJRXmo8aagYLEwgF0rUcDmMKJ+QPb0yGn9z0p4rBGm+KuNH7DUneuk5rVWTUXIkzj7FVJ01MT/jTH2SzH7oAtOzQI5OmDP1tdCOHzvfA5P0hV5Bp59WFR3cQiZtDSgIvY= Received: from AM6PR05CA0036.eurprd05.prod.outlook.com (2603:10a6:20b:2e::49) by VI0PR08MB10780.eurprd08.prod.outlook.com (2603:10a6:800:204::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.21; Thu, 16 Nov 2023 18:07:18 +0000 Received: from AMS0EPF000001B4.eurprd05.prod.outlook.com (2603:10a6:20b:2e:cafe::2b) by AM6PR05CA0036.outlook.office365.com (2603:10a6:20b:2e::49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.21 via Frontend Transport; Thu, 16 Nov 2023 18:07:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AMS0EPF000001B4.mail.protection.outlook.com (10.167.16.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.19 via Frontend Transport; Thu, 16 Nov 2023 18:07:18 +0000 Received: ("Tessian outbound 26ee1d40577c:v228"); Thu, 16 Nov 2023 18:07:17 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 9a0625d862b149a2 X-CR-MTA-TID: 64aa7808 Received: from 12a0f1343511.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 08BDA194-F602-4904-8DCD-EAB765542858.1; Thu, 16 Nov 2023 18:07:06 +0000 Received: from EUR05-AM6-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 12a0f1343511.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 16 Nov 2023 18:07:06 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HIxCBpDLKC0PfyxRruNvatfAj5jvUdQKxiYMXup/hhsJlJES3o92UBaSARhM73KBVaUknpFeC2hxaPNbhc5QVCs6Oxjjl1ps5pPTaVm77jUdc+v+kZYoocWgRfgAN+IyrupaZubpG4Maz9LeJjp+obyYB9Jpo+UTzCNTYUhmpWlY8s5FerOVA1elPagDtRsW3ZrQrL1DvlG+dayLhouV/gR1eJ/APhen4VPCDz689+xZb5La696ZblfMqGjilm60xN9GG6MoIVKRe7hLkGk85YLQxj8mmfy8/u7jLIjaRD6+hhT1wn2YQPZW0hwunSCfoBopWABZLwkDbLOsFd2QzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PRUTHX9d+6OLzzfU5ld4LGePund9c6BKeSXUPeivWV0=; b=H1X9wuDY1iTS6UK1Ox5G7yXg6g1oQHmOVVllUnFeqI6+Z0fcxqkHKZ2fTHOekTY8Dj9JM5kBUuc3scKOE4QOShOylEeMhlaYdcmvGeYEabrpP91Liv9StXM9lDh7JXU4ovBxH28DffAwZtxiwuC1ed9O0WD3t8echWO8l3E0azapyGDlkkU/SfitMidPALREgarOkW4C4HeGuSGuQRoPa97XqBb+qSV4ayYmvmvlhZOYwzdOkKVFXbN8kanZjaBbM3kofjLKCmYjXzN4gmUWx/DZv997VBWOCwgcK44dzlRS+z193tAAb8jpA1qMQSYXJyySlx8IJEYxymYLMBhEOQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PRUTHX9d+6OLzzfU5ld4LGePund9c6BKeSXUPeivWV0=; b=zpK0K/BSRaLTrugYOrJqkrDidCYsOs2tX9ZrG2VOXJhJRXmo8aagYLEwgF0rUcDmMKJ+QPb0yGn9z0p4rBGm+KuNH7DUneuk5rVWTUXIkzj7FVJ01MT/jTH2SzH7oAtOzQI5OmDP1tdCOHzvfA5P0hV5Bp59WFR3cQiZtDSgIvY= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from PAWPR08MB8958.eurprd08.prod.outlook.com (2603:10a6:102:33e::15) by GV1PR08MB7378.eurprd08.prod.outlook.com (2603:10a6:150:22::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.21; Thu, 16 Nov 2023 18:07:04 +0000 Received: from PAWPR08MB8958.eurprd08.prod.outlook.com ([fe80::8512:cc10:24d4:1919]) by PAWPR08MB8958.eurprd08.prod.outlook.com ([fe80::8512:cc10:24d4:1919%5]) with mapi id 15.20.6977.029; Thu, 16 Nov 2023 18:07:04 +0000 Date: Thu, 16 Nov 2023 18:07:02 +0000 From: Alex Coplan To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford , Kyrylo Tkachov Subject: [PATCH 02/11] rtl-ssa: Add some helpers for removing accesses Message-ID: Content-Disposition: inline X-ClientProxiedBy: LO2P265CA0163.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:9::31) To PAWPR08MB8958.eurprd08.prod.outlook.com (2603:10a6:102:33e::15) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: PAWPR08MB8958:EE_|GV1PR08MB7378:EE_|AMS0EPF000001B4:EE_|VI0PR08MB10780:EE_ X-MS-Office365-Filtering-Correlation-Id: 72f5183e-6a19-4179-3ee2-08dbe6cedef3 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 0uGyTqFWOWYnoV9cGhRYWdhG4pkG3uIl4758UGUF74PmF5D+/jYT/fq2D2S63uC0ix6Rmu6+acqUWuSxUwtqf2KAQlo9jXE4AxZW88FdXRQqBkIFbNFzHKBdnbzvVmV6OCRVmVFsSuXxe+Y46XFKNxBKR7lPHZ8ylDcUNm+NZ/QKvYxZj6MHakMwfqS3VpVjn2NWM1jLSfNkvQietuY1OQ/5K/MwXGL18bP3xgoFegn8SuLFu4Mb48xTpSyVg8sCCdBV2B1OIfb1LwVGaVouVXBuiTnk0OPzx9OuTEEjsSwWO0c91mcVZMgFYAmdCwBlLqfLcLthK5nSnTAuTe8mmo+2JY+JJ8c5GnZCmN5clp9YBt5bu/MgRJTMzrvPu5jm87hNkR+lXLemabdt20sS9pMBJURku/I/gIi5QxLTyNwGu86XGG4hOcO2TnsMxVjiHi6jzjm8yjJEE12iYSip8/6Z4w+WqW1MNcTmgDoppcTUv2VYIdaGRQHqTHVT6663JsFzb598V/jC84kHO81XlMlBAYqG4KjueBXOoN7qFso/pPyG01v6C/Q8EeG3rloa9bkUDflWcoWZuD68MD7QwQekUNpprGGOhf4SQFx4j+r7/mgIXVktqKBDFByR7RW7 X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PAWPR08MB8958.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(136003)(39860400002)(376002)(346002)(396003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(2906002)(41300700001)(316002)(66476007)(66556008)(54906003)(6916009)(36756003)(8936002)(8676002)(66946007)(4326008)(38100700002)(478600001)(235185007)(5660300002)(44832011)(6486002)(86362001)(83380400001)(26005)(6512007)(2616005)(6506007)(44144004)(33964004)(2700100001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB7378 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AMS0EPF000001B4.eurprd05.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: bba1b864-9c82-4cba-b37c-08dbe6ced6f3 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ez4tZ8WEDmhQL1/JymFBSkaD7A4CW+31doNUJbUC8wwm0ffHalzE/N3jcmwrVnOYtEHdD71cEheVY2hbcERVd81kI66v12ENwUt+iWv+18hCaXOWXQEOEKx1yD02nG06w8epvndgYdQ3VcWa7HtF5lxoFVkRwh5m3ATypWdyj5vrtUYWF0Hobz6jiIZDkOJ3RLJ3BUp2EyP2LXgkAN3xh+gGGbK5TfqWrJxN6dMvNuo5vzhbeCp1SHc1lm8+gsveomjjCjAngTSP050tr4N1ULehzuuEdPOPQK9vJBynyIgs4Mbi9uoGL3uuEd2z58YzQBvTG+2ZjrtOVU9eoJZLfN8xjR/CqELGbcKsvhi7BKgw/biWclAzqlKsLuBcmlblfKaqFVyhhD7YuDpwyZSq0ALjaqvD6TDFyDm+MwbaJTwQCYhRih5CNrjfCPdea0ltWhscZRSobU0mN4sxHaDBdo5/Gs1IHYavBY3iroDM6jgNHN53jvHaQMoU7+fCZawOtFOgUotr8nEfP5QiXtKuFnawAuePpSE8bQnTbfOkrUEf2XdbR0a/UBQfTD86LrMC48C6GFY1I2cmaEf6XTQH7G0lChXXjCENV/r4R2HRz/BKD7n/jHZadOrq5E0XflvqT3IFC7eG9KuBUvVU33Dd4TycLVdnvE3WzDD+B3bqmSTBS4VRM5FSxUdjlPqIHTYzReeLhXdrYSboN++FYO0cQyTaJ2lIK9wFc6gDVpt+UnbuZIIw5whJGTPCAL8oA4FTAZCnwgGXXu6jIZlWoO26Fg== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(136003)(39860400002)(376002)(346002)(396003)(230922051799003)(1800799009)(82310400011)(64100799003)(186009)(451199024)(36840700001)(46966006)(40470700004)(40480700001)(2906002)(36860700001)(41300700001)(316002)(54906003)(6916009)(36756003)(8936002)(8676002)(70206006)(4326008)(70586007)(478600001)(47076005)(81166007)(235185007)(5660300002)(44832011)(6486002)(86362001)(356005)(83380400001)(40460700003)(336012)(82740400003)(26005)(6512007)(2616005)(6506007)(44144004)(33964004)(2700100001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2023 18:07:18.0723 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72f5183e-6a19-4179-3ee2-08dbe6cedef3 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001B4.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI0PR08MB10780 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782744945906740151 X-GMAIL-MSGID: 1782744945906740151 This adds some helpers to access-utils.h for removing accesses from an access_array. This is needed by the upcoming aarch64 load/store pair fusion pass. Bootstrapped/regtested as a series on aarch64-linux-gnu, OK for trunk? gcc/ChangeLog: * rtl-ssa/access-utils.h (filter_accesses): New. (remove_regno_access): New. (check_remove_regno_access): New. --- gcc/rtl-ssa/access-utils.h | 42 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/gcc/rtl-ssa/access-utils.h b/gcc/rtl-ssa/access-utils.h index f078625babf..31259d742d9 100644 --- a/gcc/rtl-ssa/access-utils.h +++ b/gcc/rtl-ssa/access-utils.h @@ -78,6 +78,48 @@ drop_memory_access (T accesses) return T (arr.begin (), accesses.size () - 1); } +// Filter ACCESSES to return an access_array of only those accesses that +// satisfy PREDICATE. Alocate the new array above WATERMARK. +template +inline T +filter_accesses (obstack_watermark &watermark, + T accesses, + FilterPredicate predicate) +{ + access_array_builder builder (watermark); + builder.reserve (accesses.size ()); + auto it = accesses.begin (); + auto end = accesses.end (); + for (; it != end; it++) + if (predicate (*it)) + builder.quick_push (*it); + return T (builder.finish ()); +} + +// Given an array of ACCESSES, remove any access with regno REGNO. +// Allocate the new access array above WM. +template +inline T +remove_regno_access (obstack_watermark &watermark, + T accesses, unsigned int regno) +{ + using Access = decltype (accesses[0]); + auto pred = [regno](Access a) { return a->regno () != regno; }; + return filter_accesses (watermark, accesses, pred); +} + +// As above, but additionally check that we actually did remove an access. +template +inline T +check_remove_regno_access (obstack_watermark &watermark, + T accesses, unsigned regno) +{ + auto orig_size = accesses.size (); + auto result = remove_regno_access (watermark, accesses, regno); + gcc_assert (result.size () < orig_size); + return result; +} + // If sorted array ACCESSES includes a reference to REGNO, return the // access, otherwise return null. template From patchwork Thu Nov 16 18:07:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Coplan X-Patchwork-Id: 165911 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6359:6513:b0:164:83eb:24d7 with SMTP id sk19csp42189rwb; Thu, 16 Nov 2023 10:08:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IENlHh8atzwG7EZEnY6DsjpaN3mbLDZ01FrUW2uAlo5mbqbHr+j35tl1tqJ6Q7MOz8dGykT X-Received: by 2002:a05:6214:1850:b0:671:49d7:6077 with SMTP id d16-20020a056214185000b0067149d76077mr8319683qvy.30.1700158090532; Thu, 16 Nov 2023 10:08:10 -0800 (PST) ARC-Seal: i=4; a=rsa-sha256; t=1700158090; cv=pass; d=google.com; s=arc-20160816; b=DJA8vMGJ7UKZnacw4ooAMHShy9Z40CSrLSatq3ibBpLsoRKjSQH2tT2+19De7ZHmrh uy6MOzpjExmZRIFxx9ri3+UMpbQcq14qqNAQE6RnEwjOQIJRx1rPWO4pjK875OdzvLHX l4nSXe1POmc1QuV7F/76XRJCY2H50dpTGXHKcMA/mRvfYWN29NbbwZuwbg6iD0vBJu4R qjV15ZTGylZsCyG5QNRwvKFF5PpXnbTh+/ygpZ4vNbxoGJFcprwTdSypnJ1eDGX0fZRR /FCi4JOJvC57lJShGqKfEby/SS5SjWvhMB+8V/JZixJnRvbZz7U0389uMiaeAz9ahCwN gmkg== ARC-Message-Signature: i=4; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:original-authentication-results :nodisclaimer:mime-version:content-transfer-encoding :content-disposition:message-id:subject:cc:to:from:date :authentication-results-original:dkim-signature:dkim-signature :arc-filter:dmarc-filter:delivered-to; bh=ROIhS7MZ/13Rp1vndjq3sK9s/aOjfxtgIUi6aHRaIpI=; fh=oBREkWEOK+vBJwK/8m3Xyoxxy+JRDn9wOQNt/tlZ9u8=; b=pviQrTDnZMEsswcCEG4DCdoc+522eqYOPiI3q6sOIMyWqiK8mWJwXujvsKmRQDpFbE 2O2HiuZ9RxRr4uzpTwNkhP+IeIA57te16HKNaiYNY0BOIMsL1D+BJXejL0MPSCt4FAa7 hZfB2e6PMLE/Ttt2b8WxK2sWsANPFc15u4Cyra+eu/OiydZLkjzM3/ZbfloQH8U+FEkg drrFjGsHk9XTiba4bwJsQ6nLniEvYVOqn72emnYIGj4FxTvLxAW/1iJCKNfhICPSRzw1 l1NjV1aN8ZUMuTp/1hLXjGMKI69qj+kCgwDVrSOAy9jDZ+ArNWSdPaDYi9DHa5/W2W+3 OzWA== ARC-Authentication-Results: i=4; mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=8vQUDRna; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=8vQUDRna; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id ef14-20020a0562140a6e00b0066d0819ca14si12091192qvb.380.2023.11.16.10.08.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Nov 2023 10:08:10 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=8vQUDRna; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=8vQUDRna; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7B3923875DE7 for ; Thu, 16 Nov 2023 18:08:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2041.outbound.protection.outlook.com [40.107.104.41]) by sourceware.org (Postfix) with ESMTPS id DBF18383E71E for ; Thu, 16 Nov 2023 18:07:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DBF18383E71E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DBF18383E71E Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.104.41 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1700158061; cv=pass; b=eL7JvSpV68cQELgx9mu5Upisg5ec7pFQ1agRGxVTM+dHPpi2KTAKfwYBc13EuOr+L2kvdNJ/CkUot6kd1BBlqZZJnXmw645aT+YY2AShF9Utf4A+ipRtOVjEwuSuhufkjargxrSJ08FEWRuNZY50qmKcDRXBFkwLdponvCMnD0c= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1700158061; c=relaxed/simple; bh=J7BbB+8CSgWeyDk95am6fyDn2ZTUlP6exfb+SqqE4/w=; h=DKIM-Signature:DKIM-Signature:Date:From:To:Subject:Message-ID: MIME-Version; b=gDLmK83FWV9BZdGHSjX+kPJ9S0tChGbkei8NUsdb7E0/KRkzA6ksUBewD2Pvj62FrsrkLy6p0z3HdlmQ0D3ne1aemGSG0lpzpwmKJkgemjIcR8IrCUuvqCFBOPv2PWCqkP9CvO/3phrcwpxAr5trOHjBwtQByQqYuOeJcDJyL4M= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=GZIO5RhL2OlRugrZR1O10CZVoRlpZryqb0FWNtthsci9EvwE+Mnf9Zmp7Lf2Y66yvLv7BppGdbUqGGYCOvzILBC/XY5i/DK1LP6let1uB0t+mjMRDEpVo3FmAQ/JAAhfdRojWcxTEx88vi0weROWSYQJTqTquAKkGrGOmR6BaeieTzrzkOEmAUQmIIQM0mftw8u+2F6cWvGc9TH2xQd1XyaIARIAeQ/FmAeLDZT/q1FDA/gbozMCHTOe8JkEJXGh9+2HZXZ1l1hccZC4Wy+5GWKIUlTaLPvNJuL9uVzKnNJTxcJbMNmLwfiWOxInW7YsOWqSMyrCyPKRDdDxjvwd/g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ROIhS7MZ/13Rp1vndjq3sK9s/aOjfxtgIUi6aHRaIpI=; b=dKMKRV4KJ/37WSx4tbGnRhkqnLsM5sKr+Fylqe7p3+F944sudRLiBq1BrbzT2GqK8Sv0uH6xpELqN8PK/ltBKDknohB4tQZcfssHdgzcsxQP81L+F5zLjZiPIiusdi4tZD3ZZ6Y3Rb0I9ZPULAA8oD5Rjh+Mc1UytRGYBygQub1wq4i9TaWHa5h6T6QepGoCHgCI54nLr/ZKS7Pos/EGhXEU+aKdLJGRWElsY2yDP4ERkpnBYagpdGpw6eoeuE7q2VRR0oFRJ0NnidDH0DmwWlfJ5++bv39e/J2VtJuLrqBbF9AGlXL+8EvPlCkqrrqByo26P+/v2EeXwfpptMvGAg== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ROIhS7MZ/13Rp1vndjq3sK9s/aOjfxtgIUi6aHRaIpI=; b=8vQUDRnapia7xqkLm/ZHoVtqXxIZpQhWj1i0+2/utlJXyXr9Evr1ZI/rDaSvnAJ6ChM3sdPUYRrXZFBWPSuAwBl4rjGzwwnQ/6k1Urx1DhXGjdwD7Y74MRjAjx8QAkpVDslnt71iAr55iBRJQAAEwjWJAA3HJnqufTi0MznYlQk= Received: from AS9PR06CA0694.eurprd06.prod.outlook.com (2603:10a6:20b:49f::7) by PAVPR08MB9747.eurprd08.prod.outlook.com (2603:10a6:102:31e::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.18; Thu, 16 Nov 2023 18:07:37 +0000 Received: from AMS1EPF00000044.eurprd04.prod.outlook.com (2603:10a6:20b:49f:cafe::7c) by AS9PR06CA0694.outlook.office365.com (2603:10a6:20b:49f::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.21 via Frontend Transport; Thu, 16 Nov 2023 18:07:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AMS1EPF00000044.mail.protection.outlook.com (10.167.16.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.20 via Frontend Transport; Thu, 16 Nov 2023 18:07:37 +0000 Received: ("Tessian outbound 8289ea11ec17:v228"); Thu, 16 Nov 2023 18:07:37 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 39d2571c7df41fcf X-CR-MTA-TID: 64aa7808 Received: from 6ae9a4459328.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id B0C56C97-F8FA-4944-B5F2-F82E1E7DFBB5.1; Thu, 16 Nov 2023 18:07:30 +0000 Received: from EUR05-AM6-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 6ae9a4459328.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 16 Nov 2023 18:07:30 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=oaIU7U3+hjtR1UpYPCctW7e8yeSHJq3btKqE8g5BfG1YlLmSGbp3drCKB2KcNIxGBHm8j/Fd5rmZh6AFfU4/O15XnNijJlrMHoW5o02tpDGJFaQmTDOSfF4xZRdhFZ1n4Teb6nbLiYyqhnLivEZzsdHA7yWkgUcUIg32782LQJCgEnLDTQZe9dQxLnix/JqcJPx2J77nM7ArcwAhevLYpuU22tcFuyVRCQhHOdE3HXZ5z+7I+MbEQcebB9TY0S/p/+Veyv4S9BJ0R0/n+1194QwZabK5GHEC5rkzU5VASDx2/f7cALKYi6K1VVeHlXmf8q33ZLMfVQrEPsmhZ6GFYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ROIhS7MZ/13Rp1vndjq3sK9s/aOjfxtgIUi6aHRaIpI=; b=COIQYwJWoBX6rQdWRmvvIDn3sWvZTUeo9keAwkVjSRuAL6Ja7QSdbrIHF1YtoV6xtTYfOnUHZmRq5KBIlwjHST3jTNoOJPhpm/dkbNGEq5YGhXX8mGWniEMKRZ4emox8sxVP5LF+W3b4AfLmizYtTcm5Qvolu9m2HorQKseMgphV7mHASzIoxstkBtMmsCJ0+L5AyIAngQh1BDglayHC+lX8R7aVglEntdOqJn3Ylrj6s3l19oXkxLVtTCzykpt4K+WFQ7aQo/RwuMy2XZovLCTxfBCIYyebL2G2qjDJ/XL9YJRsFxV/oGj4wMRperL1KEzwR68I9FQ9gQP9aJpTBA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ROIhS7MZ/13Rp1vndjq3sK9s/aOjfxtgIUi6aHRaIpI=; b=8vQUDRnapia7xqkLm/ZHoVtqXxIZpQhWj1i0+2/utlJXyXr9Evr1ZI/rDaSvnAJ6ChM3sdPUYRrXZFBWPSuAwBl4rjGzwwnQ/6k1Urx1DhXGjdwD7Y74MRjAjx8QAkpVDslnt71iAr55iBRJQAAEwjWJAA3HJnqufTi0MznYlQk= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from PAWPR08MB8958.eurprd08.prod.outlook.com (2603:10a6:102:33e::15) by GV1PR08MB7378.eurprd08.prod.outlook.com (2603:10a6:150:22::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.21; Thu, 16 Nov 2023 18:07:28 +0000 Received: from PAWPR08MB8958.eurprd08.prod.outlook.com ([fe80::8512:cc10:24d4:1919]) by PAWPR08MB8958.eurprd08.prod.outlook.com ([fe80::8512:cc10:24d4:1919%5]) with mapi id 15.20.6977.029; Thu, 16 Nov 2023 18:07:28 +0000 Date: Thu, 16 Nov 2023 18:07:24 +0000 From: Alex Coplan To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford , Kyrylo Tkachov Subject: [PATCH 03/11] aarch64, testsuite: Fix up auto-init-padding tests Message-ID: Content-Disposition: inline X-ClientProxiedBy: LO2P123CA0084.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:138::17) To PAWPR08MB8958.eurprd08.prod.outlook.com (2603:10a6:102:33e::15) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: PAWPR08MB8958:EE_|GV1PR08MB7378:EE_|AMS1EPF00000044:EE_|PAVPR08MB9747:EE_ X-MS-Office365-Filtering-Correlation-Id: 623f6309-2669-4304-b6f9-08dbe6ceea80 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: lIeH24LlzRTKkWlwYabWwXW70jtPiuNxE3mVKxf9hwZnB2ga30bo7ZQW4TGJvB8/ZaE+BXWNHV8BKRBqQ0+dz9EmcbEiYzM/Sac3p5Ob3ow8gyRL8L9UD5aI8RYxHB0CfxZxG700Fihbp4af/ZcdIm8ICXNDoH7NhwaWKMEy1ecpndADtWd7yPmPLuV3aELR2pLt96qWR60y4tXcKZWkXEjsDMPagpMGFo07Zou4kQsHRuPOM+3hu+IR62jC34mGerkwzM2D6GheDMmrpsPliRHRQarmLAyPHk7r0U7HqZ/rEyj6UzuRsNEjlzSutOldPyUTWHNmT2OP+SubvRf/o5sTA9H9z0kEMTfRXPt5/bFoq/Qfw/j0wX3Sl9r/xKwW8M5HBJ7lc44pNSt9lyQd8pNtOolCivpvi7uBOrOpC870s0ktC32lxUHlEEXYOifM4uRYEbR9sYggovMB/i0Wfc276uPrUhYi+GMT9ueo7CMTWO8DFXVdq1QCHeFJd0cTS+n60Oat0E74mpoE2p3EBNcrlHoOh97kcC55SOAa54De+vXZx208yBchEgJdMTlUEJFduqOgBbw7Eu0ZhjdiNDv9nqxCTiaZNMZ2/RPbh/dH9b8L3bsrOWuEqOaW4AQjwxZ6UfEILz2wBzvNgcmNgg== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PAWPR08MB8958.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(136003)(39860400002)(376002)(346002)(396003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(2906002)(84970400001)(41300700001)(316002)(66476007)(66556008)(54906003)(6916009)(36756003)(8936002)(8676002)(66946007)(4326008)(38100700002)(478600001)(235185007)(5660300002)(44832011)(6486002)(86362001)(83380400001)(26005)(6512007)(2616005)(6666004)(6506007)(44144004)(33964004)(2700100001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB7378 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AMS1EPF00000044.eurprd04.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 00fede20-7579-4805-c93f-08dbe6cee52e X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yCd1l4MQdxC6PN7EvAoN4ywmmPxpf+yo+45TPLPvWnGEpLYDy9y3icVhSen9CXK4vwRn+MNJSGe5re4VtfwH/CJT+ySux3Scpr9wBOq34G/fV0sFpqfVo8Vn8D/0Ox/SZ0qH+LAnogjtLSU8A8ucjaudwzG/SV79BNf/WxuzzrIVx7gEjFFrlg0CRfmB6XLhDLBYtbp2LTZNnLkC7jRjDsEoDsAm8J4TU4ZpMOs6z33ZwE2McLJJrrwyhwLMTzKgvw8F3bcZfZFwyOJ21Broukl3p2J2mqP4KQp7uJJctvigXTNh7UxiZ9Iwi6FxVvocWPdlg1MvE1FUKDWvbDgPEbDnXkXq9D00gFEtWWMb2Q3AXllnrN0g+3FswKZv7p863XPk509ZBQX8maU4e3y8WpEQp4oRHzYYWWtKvdsZWPRGYGHhkT+zI9MqVjQVMC+QAOWQzbCAVnOiCfixcIg1BiIblMpL7ZOzO001iYZm7GcbdayT9Jb8mRDMxTvFfQKtHXv8X4jQQCBtH+bee15Ew8LyJzbOOzJ+35blRpjWgMCXNgZIg0BXa4NZAFBO5RqfdL9wnvqKPVy9mdon36yCmUSM/JaybtLCMkfvUdGzGE80yofQA0CaQOhS2i2fxfY/OTmY56dzPBYw1V/Wa2sgHzhVpmYVFLRMhLQuoxaSdM2ibslOgpIubcdRxmvzYV84D6X/MZsEcI3nhGRevvajr9yf2uYjmsQDscrAG6/w+1MTvN1zM0ujmQLnoV4da61W+1zd+pMLBYH8aeCI9h1R2IHFzGcPCP2hnFvJqgZXfw4= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(346002)(376002)(39860400002)(136003)(396003)(230922051799003)(64100799003)(1800799009)(451199024)(186009)(82310400011)(36840700001)(46966006)(40470700004)(82740400003)(40480700001)(44144004)(6512007)(6506007)(6666004)(33964004)(36860700001)(336012)(2616005)(84970400001)(26005)(478600001)(6486002)(86362001)(41300700001)(6916009)(70586007)(70206006)(54906003)(83380400001)(81166007)(356005)(316002)(47076005)(235185007)(44832011)(4326008)(2906002)(8676002)(5660300002)(36756003)(8936002)(40460700003)(2700100001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2023 18:07:37.4543 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 623f6309-2669-4304-b6f9-08dbe6ceea80 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF00000044.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9747 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782744970053941223 X-GMAIL-MSGID: 1782744970053941223 The tests currently depending on memcpy lowering forming stps at -O0, but we no longer want to form stps during memcpy lowering, but instead in the load/store pair fusion pass. This patch therefore tweaks affected tests to enable optimizations (-O1), and adjusts the tests to avoid parts of the structures being optimized away where necessary. OK for trunk? gcc/testsuite/ChangeLog: * gcc.target/aarch64/auto-init-padding-1.c: Add -O to options, adjust test to work with optimizations enabled. * gcc.target/aarch64/auto-init-padding-2.c: Add -O to options. * gcc.target/aarch64/auto-init-padding-3.c: Add -O to options, adjust test to work with optimizations enabled. * gcc.target/aarch64/auto-init-padding-4.c: Likewise. * gcc.target/aarch64/auto-init-padding-9.c: Likewise. --- gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c | 8 +++++--- gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c | 2 +- gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c | 7 ++++--- gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c | 4 ++-- gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c | 7 ++++--- 5 files changed, 16 insertions(+), 12 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c index c747ebdcdf7..7027454dc74 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c @@ -1,17 +1,19 @@ /* Verify zero initialization for structure type automatic variables with padding. */ /* { dg-do compile } */ -/* { dg-options "-ftrivial-auto-var-init=zero" } */ +/* { dg-options "-O -ftrivial-auto-var-init=zero" } */ struct test_aligned { int internal1; long long internal2; } __attribute__ ((aligned(64))); -int foo () +void bar (struct test_aligned *); + +void foo () { struct test_aligned var; - return var.internal1; + bar(&var); } /* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c index 6e280904da1..d3b6591c9b0 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c @@ -1,7 +1,7 @@ /* Verify pattern initialization for structure type automatic variables with padding. */ /* { dg-do compile } */ -/* { dg-options "-ftrivial-auto-var-init=pattern" } */ +/* { dg-options "-O -ftrivial-auto-var-init=pattern" } */ struct test_aligned { int internal1; diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c index 9ddea58b468..aad4bb8944f 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c @@ -1,7 +1,7 @@ /* Verify zero initialization for nested structure type automatic variables with padding. */ /* { dg-do compile } */ -/* { dg-options "-ftrivial-auto-var-init=zero" } */ +/* { dg-options "-O -ftrivial-auto-var-init=zero" } */ struct test_aligned { unsigned internal1; @@ -16,11 +16,12 @@ struct test_big_hole { struct test_aligned four; } __attribute__ ((aligned(64))); +void bar (struct test_big_hole *); -int foo () +void foo () { struct test_big_hole var; - return var.four.internal1; + bar (&var); } /* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 4 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c index 75bba82ed34..efd310f054d 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c @@ -1,7 +1,7 @@ /* Verify pattern initialization for nested structure type automatic variables with padding. */ /* { dg-do compile } */ -/* { dg-options "-ftrivial-auto-var-init=pattern" } */ +/* { dg-options "-O -ftrivial-auto-var-init=pattern" } */ struct test_aligned { unsigned internal1; @@ -23,4 +23,4 @@ int foo () return var.four.internal1; } -/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 5 } } */ +/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 4 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c index 0f1930f813e..64ed8f11fe6 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c @@ -1,7 +1,7 @@ /* Verify zero initialization for array type with structure element with padding. */ /* { dg-do compile } */ -/* { dg-options "-ftrivial-auto-var-init=zero" } */ +/* { dg-options "-O -ftrivial-auto-var-init=zero" } */ struct test_trailing_hole { int one; @@ -11,11 +11,12 @@ struct test_trailing_hole { /* "sizeof(unsigned long) - 1" byte padding hole here. */ }; +void bar (void *); -int foo () +void foo () { struct test_trailing_hole var[10]; - return var[2].four; + bar (var); } /* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 5 } } */ From patchwork Thu Nov 16 18:10:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Coplan X-Patchwork-Id: 165915 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6359:6513:b0:164:83eb:24d7 with SMTP id sk19csp44392rwb; Thu, 16 Nov 2023 10:11:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IGIt0HNhCfeYpyGHI+2QO7SGMahxS4XBKu8yoxcvZcu9jNbDn2CvMAGDRYH2l+RF0NcFh9B X-Received: by 2002:a05:620a:bcb:b0:779:fb0e:ba96 with SMTP id s11-20020a05620a0bcb00b00779fb0eba96mr10445195qki.3.1700158270239; Thu, 16 Nov 2023 10:11:10 -0800 (PST) ARC-Seal: i=4; a=rsa-sha256; t=1700158270; cv=pass; d=google.com; s=arc-20160816; b=phEENASP+ym328V20IG2kRvI6TjYz5G6QyeGedCSd5DAzaOPQ5BgRietZ4r8TirL2u unuJy18EMFLDxi1Lj+t8sBGH/1tVdb8AB/A2hpxL7uz9bsYqquF8RJauTA0HYEr4d/gt CRv+DRtHDwsh0m1Itxr6QLQDrcgRiKsglUMYNS5cKRq/qKrN5ivaKMRHHOI2Omqt08p9 cJ8NRq32x3zKHqRq/FcWXymc3RbDW2wlt7XIkU9PhfwL6tAQiQX1vBciiPDzluUx+Jfr UdhJ8htkgIxxHHgyAwoNYiWpY9wVKagCGqLnxAm+2uToZmHEuh9gfjuq6NYOw3GpzIvJ G8Xg== ARC-Message-Signature: i=4; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:original-authentication-results :nodisclaimer:mime-version:content-transfer-encoding :content-disposition:message-id:subject:cc:to:from:date :authentication-results-original:dkim-signature:dkim-signature :arc-filter:dmarc-filter:delivered-to; bh=ChBANwPMtGKRsPcrYcKmd2uZa/Q/i4YNqAbIgIgt4H8=; fh=oBREkWEOK+vBJwK/8m3Xyoxxy+JRDn9wOQNt/tlZ9u8=; b=sVYeVgoIfU9kwBQeOY2ejBbPJ+2tlXaGKWWPrpmiSrVHEjA5bEja30+JFOBPMwjyqK avg1MIYr5ND2gdxVc3iY4PNg/+MI5htavtmzAVCbM0ZinuWaKfINzPnKrl9K420b+0qu UYEzv/J9fFzjOio6CuTvEzSxFqUmRgJE8OQqEDrGG6iFDFN2dCrDEhEvuRQf79wd7eCh jeobb8x0H6b1RXw3h938uiJOM0bwmcIkSsOAIKrppw9yz+vdvh0tG35jY3vHucfMSZb/ KA7rRgROSFddou8F4utLvaEqFC1DdP7KUj0gEuTxHpdnjbN/L8vZPIzTkuFFaCHqApW7 lu1g== ARC-Authentication-Results: i=4; mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=HR0DoWWR; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=HR0DoWWR; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id b27-20020a05620a271b00b0077436023382si12181896qkp.198.2023.11.16.10.11.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Nov 2023 10:11:10 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=HR0DoWWR; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=HR0DoWWR; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DE4993856975 for ; Thu, 16 Nov 2023 18:11:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2057.outbound.protection.outlook.com [40.107.22.57]) by sourceware.org (Postfix) with ESMTPS id 0524E3856975 for ; Thu, 16 Nov 2023 18:10:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0524E3856975 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0524E3856975 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.22.57 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1700158237; cv=pass; b=qnJKYe6wpSZUuTx3pvgr2OgHb3wFFvJN0vm0ya8q0ZlrmLWJeN5AmN/FccVsh02oam0525HMKqgGrpHs46jEqNk9YjwdCIkeudZfpUGVzaH1lcxQ2B7XJgINNNu8s/rOJGiGyx0n0c03/RqovcL/gmZ/4/u471Z5H4WBUJ5bEOQ= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1700158237; c=relaxed/simple; bh=sP37SVB7drhla4t81KM89lSNZjFh7fu1MWW7s3Hx2cw=; h=DKIM-Signature:DKIM-Signature:Date:From:To:Subject:Message-ID: MIME-Version; b=C4/BMc0Rta4JdEzA8ugcgC2QyOb4SyjNSywfQVgt0sGk36wYLnUO+a1hj7fzlMru+bpu32gsZ73UKe4ijvfaJgcOKuGyHSlbm34CZiqa4YrCVxD2skSMsdovW9z2CpZ5Lg00L9AcZRHCPRqlofldVZ/4BLk8ZtKm/uKQVHcUuC0= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=fysQNRFOvqVwjYFDzqxbglT3qjOWsFpzExchTzqGcCZv2FKgTafomd1ZglLYSnPy2EUuVF4Em6xr/BN/pEZIoIkU11FXWLm4RlF7IiAH5naULEaObqxnKnaJ6gheraZ0E3CbdEFWwmUzf0UdZBdXpAULW5WdMxmibZuvEfB/e0OFFuPTQW5fUtj/9ngS5q5gRCjzzWy9OY7TK4iJDkYT/VpeZQEwu0OaVcGfZyngblMiDjTC5+Vx7tVqhiBQurjwaoUwOPbjADweYwjc4TwWggaM+2uqbYG27aHMpierfJA144Rf3OjXznj8eBwbTpQn3z+zGDudQkULE9ZOnpU6+Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ChBANwPMtGKRsPcrYcKmd2uZa/Q/i4YNqAbIgIgt4H8=; b=lGlHWWxmM8fpDbj29GqQQKTVoeW1aspXmWEzr2p7fAJmYxt/izIViOwLSvcepby6rrcXkY0kbQErOTTqWONrSz0uxhKKJGsOgLkS8f6ucno1aveTN6wqsPukzmMfHqkHFWgypOjNsPXo1XYy2pvcM3mgP7akhgDoEZ1VKHunIwVqivlXdeogtKg/WYTvWHQ+nyElHp92P4V+l8N2ssLpTLYoGeq8/0Q4O4FubYQ/afuZjhCzTLCirWtxXyi+AbowxojS1UNm5TJeyzjg1Fp41oCRSFxEvNhWhUX8MeAPaxAhzlw3m72meIdziuKDOZ735RjTsEbEupDUEYyGA/mH3A== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ChBANwPMtGKRsPcrYcKmd2uZa/Q/i4YNqAbIgIgt4H8=; b=HR0DoWWRpg1E+xNlRZDKEUe8MYIMdl+e2NTIJ32bCZHt+ZOIr/479h3ijMo5NAt8I8mjVc59LCX8gZa95NCwy9yf0pfPF7P4GBdotVXxbSpzoR4ltuUPyJcp+g0+NhMIQdtlHw0MOQMHQ740s851kqNDeCy5hPry9b4GmSmfHUA= Received: from AS4PR09CA0025.eurprd09.prod.outlook.com (2603:10a6:20b:5d4::15) by PAVPR08MB9282.eurprd08.prod.outlook.com (2603:10a6:102:305::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.31; Thu, 16 Nov 2023 18:10:29 +0000 Received: from AM1PEPF000252DF.eurprd07.prod.outlook.com (2603:10a6:20b:5d4:cafe::6d) by AS4PR09CA0025.outlook.office365.com (2603:10a6:20b:5d4::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.18 via Frontend Transport; Thu, 16 Nov 2023 18:10:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM1PEPF000252DF.mail.protection.outlook.com (10.167.16.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.19 via Frontend Transport; Thu, 16 Nov 2023 18:10:29 +0000 Received: ("Tessian outbound 20615a7e7970:v228"); Thu, 16 Nov 2023 18:10:29 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 3446c021e80b5c90 X-CR-MTA-TID: 64aa7808 Received: from a804d6167438.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 58BC2F1B-0CEE-4838-BD6C-022ABC17D4CC.1; Thu, 16 Nov 2023 18:10:22 +0000 Received: from EUR04-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id a804d6167438.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 16 Nov 2023 18:10:22 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=R05Uvb9Esqb86lvs8ybLxNwLW3IdeiGE4jjGS0/pPSsJSYaXa0ZOMwI2Ewv7jhlKC+IxyybN3xEljFvknUWryI8XCzkz9y5mBpWeUgvXNZN7a8QeZC/0/i9EUlkuhSZgVjm8tiXw+lYDADqbWLqgKfHmPHlRYmlZ08qWwpQKChbwchCgUwTp1C7641V0EDKuGD6/zDiZQTVD2vikpXJ/kjXx8GPfTEBDuyP50d7wQI4xoYG3ySPkvkR3YAxyby5c01CrDzjBFgoAAw6Ofb7k7IO2kot4UwPP9vz66YC8rpM0nFv81SvDRIwVLc5ZZQJ/hIjlMrpidRQszN4OahpKOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ChBANwPMtGKRsPcrYcKmd2uZa/Q/i4YNqAbIgIgt4H8=; b=jjKyfouJWlNCePZiq48mmViGANWnmmMxHTxLwbd5Amq+PfOLnBxofCvXbtLa0F0bB/vIWdUDYlHeJcMyqPl3HU0Nsuqv3qX15R2Xw9fjxqdEu1yFlUDi/PVmmZItQVdcTHSkj1NqG67ous9ef7VTDR+QRq4ObS03B46ZOA3ikADLrTb3cMNpuSQo0SxJ6STq4NG7NDVJzOwbyTMt0WQsd0pOaIJEW8xZtLIiL6ywjk7C0HyvdTj8ngGfQ2PjWhd8l/MjoqDHSu8O1M17IUvXrZ7pqCP/+dK50aq6hkZhg1Tj0lFPj19zqOLzyil3EX5MglRbs/qAu0ioNc/QjU64vQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ChBANwPMtGKRsPcrYcKmd2uZa/Q/i4YNqAbIgIgt4H8=; b=HR0DoWWRpg1E+xNlRZDKEUe8MYIMdl+e2NTIJ32bCZHt+ZOIr/479h3ijMo5NAt8I8mjVc59LCX8gZa95NCwy9yf0pfPF7P4GBdotVXxbSpzoR4ltuUPyJcp+g0+NhMIQdtlHw0MOQMHQ740s851kqNDeCy5hPry9b4GmSmfHUA= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from PAWPR08MB8958.eurprd08.prod.outlook.com (2603:10a6:102:33e::15) by GV1PR08MB10424.eurprd08.prod.outlook.com (2603:10a6:150:15e::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.31; Thu, 16 Nov 2023 18:10:19 +0000 Received: from PAWPR08MB8958.eurprd08.prod.outlook.com ([fe80::8512:cc10:24d4:1919]) by PAWPR08MB8958.eurprd08.prod.outlook.com ([fe80::8512:cc10:24d4:1919%5]) with mapi id 15.20.6977.029; Thu, 16 Nov 2023 18:10:19 +0000 Date: Thu, 16 Nov 2023 18:10:15 +0000 From: Alex Coplan To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford , Kyrylo Tkachov Subject: [PATCH 09/11] aarch64: Rewrite non-writeback ldp/stp patterns Message-ID: Content-Disposition: inline X-ClientProxiedBy: LO2P265CA0387.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:f::15) To PAWPR08MB8958.eurprd08.prod.outlook.com (2603:10a6:102:33e::15) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: PAWPR08MB8958:EE_|GV1PR08MB10424:EE_|AM1PEPF000252DF:EE_|PAVPR08MB9282:EE_ X-MS-Office365-Filtering-Correlation-Id: a7cc6e8c-a3a6-4d74-f6d1-08dbe6cf50eb x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: GjBNS7rm/Wn/tTAyW3DgR4MyyU5xSIZ8neWlRq1fqAvyCYJMKkR/YkNwIjisvazuQ3T0ex4v3um6IhsBnk3m0Zu2ESL4wUFgeINswvR7en6GwZM3NxMe/uIjv+cykFFsD6bNKbPToletJ4H5Yu2/RMfdUbimXSoTx3BWNRS66bGuYcIpLC0RwZiL4pL2TkBWNdGCz5imIOLZQDDAWBpJrvjZIV5ThAfv4Nix5DX1Ynj8Zl2LbPt1E17rsvUGo7g2XcA0pFOFRJeNxMzT6IWvNwrUodBimTnCr1LTVSCm2iel5uB31v2hlBpY0SZIBVs6crtiAQsMmJ+Q9FbRTUOQFkfyxgPbgcG/t+XVFEzdxu+DsfD0gvuUngjiXO78h6E4jhoxxKHsrMVmoGklP+tZBddu/YlpyGPqrdbfqXZ/qxjdlsuebSBmip3F8eaW+pK/Y+dgx1s+ABuebFfj06t4mIGCTfR7hNEkQWMOxuqdB+q+3f8jiWLd0K42cX56r0nOfYQ0eKVM7BdSxHL1JQpk444HhxPUgjFttpztoQuyxnhKSLC+t98BhxcKON3PKWdKYoG4G9LSpLAS76qZwS53RTri+jOs8GkNzUwBuwv0WebaP78lFa80ZuhMJCjxTo81 X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PAWPR08MB8958.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(376002)(366004)(396003)(39860400002)(346002)(136003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(2906002)(66556008)(478600001)(38100700002)(41300700001)(66476007)(66946007)(36756003)(86362001)(54906003)(6916009)(6486002)(316002)(2616005)(235185007)(5660300002)(6512007)(44144004)(26005)(6506007)(33964004)(6666004)(44832011)(4326008)(8936002)(83380400001)(8676002)(2700100001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB10424 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM1PEPF000252DF.eurprd07.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 6290a6a8-a843-4ba5-150a-08dbe6cf4af3 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8pDl2QxrbBMhWrUblsTiYAsp5rwQfydWMBDPkzfZSiWtUmw9XkRs1cZMmP6rxMGUrEGSLsc9TdxwXv+S8Xvuq3VaQzKxAp96BBfZq/QPda6hPesKjdXXv2eacdI0+qQ4VizYMq/fGH9QD/90DL17Q7RX0xIWqTdMG1ACxUpKLu4a1IosMkYNk8czKBmGgt8pDKVhi8KU9GLhuL2rsU5enqSL43QLMSv7+eTQeL48EzZw2DRhNWeFnJQ6Ygvl6mQaB0szNm6P7U7NOwO8YsfXTH5XO6ia04GHcV3aSMr9UduNbBV+5YaDl6NxW9s0w7deOVOcPqZUmPHNuV5HsoMx3rqS0bQNcpHmi9mqsmAtulzbIUZyaZWDrdVTVX1iChJtC3Q9FTSOIz7xt+DOrDn4YS9XkjDaS2b5A2gnL7xcgwsg6O1BKYwxhTQ+SfdhLkzJKvS+Y+h2tAmFbDqRXeotmwEaOPR74T/wMbKCQvs+kEhK3yoCXIuuyih8tVCi0VmVa5zQDmVnJ7QAvaY+FIjz4OFSd/GpjvyvSZ376TenU0+PkHt7oxT0uJk0OTkZIuhT85ALfBXjiGXLKAwkAyHsskfUyySPvDC53KBzhRvBbw63mNiElOqNRnXSsHZofz3m7mElwWi1VjrrLiOxCBtNvP76lWb2bONwbpAdtdlfWXS7fR0SvUttYHj6MP6dEaByCxwOu0RcTgYqAAXk0hdG4TAcArNVZ4Kr6rgE22DQ9uv1ELbzlIw1toi5+/bl0zDGkHYazZiGgdiocihoJ3P5nQ== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(346002)(39860400002)(396003)(136003)(376002)(230922051799003)(451199024)(64100799003)(1800799009)(186009)(82310400011)(40470700004)(46966006)(36840700001)(235185007)(2906002)(40460700003)(4326008)(54906003)(8936002)(70206006)(6916009)(70586007)(86362001)(5660300002)(316002)(44832011)(8676002)(36756003)(81166007)(83380400001)(478600001)(40480700001)(6486002)(2616005)(6666004)(36860700001)(356005)(6512007)(33964004)(44144004)(41300700001)(47076005)(26005)(6506007)(336012)(82740400003)(2700100001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2023 18:10:29.2692 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7cc6e8c-a3a6-4d74-f6d1-08dbe6cf50eb X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM1PEPF000252DF.eurprd07.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9282 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782745158590521246 X-GMAIL-MSGID: 1782745158590521246 This patch overhauls the load/store pair patterns with two main goals: 1. Fixing a correctness issue (the current patterns are not RA-friendly). 2. Allowing more flexibility in which operand modes are supported, and which combinations of modes are allowed in the two arms of the load/store pair, while reducing the number of patterns required both in the source and in the generated code. The correctness issue (1) is due to the fact that the current patterns have two independent memory operands tied together only by a predicate on the insns. Since LRA only looks at the constraints, one of the memory operands can get reloaded without the other one being changed, leading to the insn becoming unrecognizable after reload. We fix this issue by changing the patterns such that they only ever have one memory operand representing the entire pair. For the store case, we use an unspec to logically concatenate the register operands before storing them. For the load case, we use unspecs to extract the "lanes" from the pair mem, with the second occurrence of the mem matched using a match_dup (such that there is still really only one memory operand as far as the RA is concerned). In terms of the modes used for the pair memory operands, we canonicalize these to V2x4QImode, V2x8QImode, and V2x16QImode. These modes have not only the correct size but also correct alignment requirement for a memory operand representing an entire load/store pair. Unlike the other two, V2x4QImode didn't previously exist, so had to be added with the patch. As with the previous patch generalizing the writeback patterns, this patch aims to be flexible in the combinations of modes supported by the patterns without requiring a large number of generated patterns by using distinct mode iterators. The new scheme means we only need a single (generated) pattern for each load/store operation of a given operand size. For the 4-byte and 8-byte operand cases, we use the GPI iterator to synthesize the two patterns. The 16-byte case is implemented as a separate pattern in the source (due to only having a single possible alternative). Since the UNSPEC patterns can't be interpreted by the dwarf2cfi code, we add REG_CFA_OFFSET notes to the store pair insns emitted by aarch64_save_callee_saves, so that correct CFI information can still be generated. Furthermore, we now unconditionally generate these CFA notes on frame-related insns emitted by aarch64_save_callee_saves. This is done in case that the load/store pair pass forms these into pairs, in which case the CFA notes would be needed. We also adjust the ldp/stp peepholes to generate the new form. This is done by switching the generation to use the aarch64_gen_{load,store}_pair interface, making it easier to change the form in the future if needed. (Likewise, the upcoming aarch64 load/store pair pass also makes use of this interface). This patch also adds an "ldpstp" attribute to the non-writeback load/store pair patterns, which is used by the post-RA load/store pair pass to identify existing patterns and see if they can be promoted to writeback variants. One potential concern with using unspecs for the patterns is that it can block optimization by the generic RTL passes. This patch series tries to mitigate this in two ways: 1. The pre-RA load/store pair pass runs very late in the pre-RA pipeline. 2. A later patch in the series adjusts the aarch64 mem{cpy,set} expansion to emit individual loads/stores instead of ldp/stp. These should then be formed back into load/store pairs much later in the RTL pipeline by the new load/store pair pass. Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk? Thanks, Alex gcc/ChangeLog: * config/aarch64/aarch64-ldpstp.md: Abstract ldp/stp representation from peepholes, allowing use of new form. * config/aarch64/aarch64-modes.def (V2x4QImode): Define. * config/aarch64/aarch64-protos.h (aarch64_finish_ldpstp_peephole): Declare. (aarch64_swap_ldrstr_operands): Delete declaration. (aarch64_gen_load_pair): Declare. (aarch64_gen_store_pair): Declare. * config/aarch64/aarch64-simd.md (load_pair): Delete. (vec_store_pair): Delete. (load_pair): Delete. (vec_store_pair): Delete. * config/aarch64/aarch64.cc (aarch64_pair_mode_for_mode): New. (aarch64_gen_store_pair): Adjust to use new unspec form of stp. Drop second mem from parameters. (aarch64_gen_load_pair): Likewise. (aarch64_pair_mem_from_base): New. (aarch64_save_callee_saves): Emit REG_CFA_OFFSET notes for frame-related saves. Adjust call to aarch64_gen_store_pair (aarch64_restore_callee_saves): Adjust calls to aarch64_gen_load_pair to account for change in interface. (aarch64_process_components): Likewise. (aarch64_classify_address): Handle 32-byte pair mems in LDP_STP_N case. (aarch64_print_operand): Likewise. (aarch64_copy_one_block_and_progress_pointers): Adjust calls to account for change in aarch64_gen_{load,store}_pair interface. (aarch64_set_one_block_and_progress_pointer): Likewise. (aarch64_finish_ldpstp_peephole): New. (aarch64_gen_adjusted_ldpstp): Adjust to use generation helper. * config/aarch64/aarch64.md (ldpstp): New attribute. (load_pair_sw_): Delete. (load_pair_dw_): Delete. (load_pair_dw_): Delete. (*load_pair_): New. (*load_pair_16): New. (store_pair_sw_): Delete. (store_pair_dw_): Delete. (store_pair_dw_): Delete. (*store_pair_): New. (*store_pair_16): New. (*load_pair_extendsidi2_aarch64): Adjust to use new form. (*zero_extendsidi2_aarch64): Likewise. * config/aarch64/iterators.md (VPAIR): New. * config/aarch64/predicates.md (aarch64_mem_pair_operand): Change to a special predicate derived from aarch64_mem_pair_operator. --- gcc/config/aarch64/aarch64-ldpstp.md | 66 +++---- gcc/config/aarch64/aarch64-modes.def | 6 +- gcc/config/aarch64/aarch64-protos.h | 5 +- gcc/config/aarch64/aarch64-simd.md | 60 ------- gcc/config/aarch64/aarch64.cc | 257 +++++++++++++++------------ gcc/config/aarch64/aarch64.md | 188 +++++++++----------- gcc/config/aarch64/iterators.md | 3 + gcc/config/aarch64/predicates.md | 10 +- 8 files changed, 270 insertions(+), 325 deletions(-) diff --git a/gcc/config/aarch64/aarch64-ldpstp.md b/gcc/config/aarch64/aarch64-ldpstp.md index 1ee7c73ff0c..dc39af85254 100644 --- a/gcc/config/aarch64/aarch64-ldpstp.md +++ b/gcc/config/aarch64/aarch64-ldpstp.md @@ -24,10 +24,10 @@ (define_peephole2 (set (match_operand:GPI 2 "register_operand" "") (match_operand:GPI 3 "memory_operand" ""))] "aarch64_operands_ok_for_ldpstp (operands, true, mode)" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] + [(const_int 0)] { - aarch64_swap_ldrstr_operands (operands, true); + aarch64_finish_ldpstp_peephole (operands, true); + DONE; }) (define_peephole2 @@ -36,10 +36,10 @@ (define_peephole2 (set (match_operand:GPI 2 "memory_operand" "") (match_operand:GPI 3 "aarch64_reg_or_zero" ""))] "aarch64_operands_ok_for_ldpstp (operands, false, mode)" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] + [(const_int 0)] { - aarch64_swap_ldrstr_operands (operands, false); + aarch64_finish_ldpstp_peephole (operands, false); + DONE; }) (define_peephole2 @@ -48,10 +48,10 @@ (define_peephole2 (set (match_operand:GPF 2 "register_operand" "") (match_operand:GPF 3 "memory_operand" ""))] "aarch64_operands_ok_for_ldpstp (operands, true, mode)" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] + [(const_int 0)] { - aarch64_swap_ldrstr_operands (operands, true); + aarch64_finish_ldpstp_peephole (operands, true); + DONE; }) (define_peephole2 @@ -60,10 +60,10 @@ (define_peephole2 (set (match_operand:GPF 2 "memory_operand" "") (match_operand:GPF 3 "aarch64_reg_or_fp_zero" ""))] "aarch64_operands_ok_for_ldpstp (operands, false, mode)" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] + [(const_int 0)] { - aarch64_swap_ldrstr_operands (operands, false); + aarch64_finish_ldpstp_peephole (operands, false); + DONE; }) (define_peephole2 @@ -72,10 +72,10 @@ (define_peephole2 (set (match_operand:DREG2 2 "register_operand" "") (match_operand:DREG2 3 "memory_operand" ""))] "aarch64_operands_ok_for_ldpstp (operands, true, mode)" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] + [(const_int 0)] { - aarch64_swap_ldrstr_operands (operands, true); + aarch64_finish_ldpstp_peephole (operands, true); + DONE; }) (define_peephole2 @@ -84,10 +84,10 @@ (define_peephole2 (set (match_operand:DREG2 2 "memory_operand" "") (match_operand:DREG2 3 "register_operand" ""))] "aarch64_operands_ok_for_ldpstp (operands, false, mode)" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] + [(const_int 0)] { - aarch64_swap_ldrstr_operands (operands, false); + aarch64_finish_ldpstp_peephole (operands, false); + DONE; }) (define_peephole2 @@ -99,10 +99,10 @@ (define_peephole2 && aarch64_operands_ok_for_ldpstp (operands, true, mode) && (aarch64_tune_params.extra_tuning_flags & AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS) == 0" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] + [(const_int 0)] { - aarch64_swap_ldrstr_operands (operands, true); + aarch64_finish_ldpstp_peephole (operands, true); + DONE; }) (define_peephole2 @@ -114,10 +114,10 @@ (define_peephole2 && aarch64_operands_ok_for_ldpstp (operands, false, mode) && (aarch64_tune_params.extra_tuning_flags & AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS) == 0" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] + [(const_int 0)] { - aarch64_swap_ldrstr_operands (operands, false); + aarch64_finish_ldpstp_peephole (operands, false); + DONE; }) @@ -129,10 +129,10 @@ (define_peephole2 (set (match_operand:DI 2 "register_operand" "") (sign_extend:DI (match_operand:SI 3 "memory_operand" "")))] "aarch64_operands_ok_for_ldpstp (operands, true, SImode)" - [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1))) - (set (match_dup 2) (sign_extend:DI (match_dup 3)))])] + [(const_int 0)] { - aarch64_swap_ldrstr_operands (operands, true); + aarch64_finish_ldpstp_peephole (operands, true, SIGN_EXTEND); + DONE; }) (define_peephole2 @@ -141,10 +141,10 @@ (define_peephole2 (set (match_operand:DI 2 "register_operand" "") (zero_extend:DI (match_operand:SI 3 "memory_operand" "")))] "aarch64_operands_ok_for_ldpstp (operands, true, SImode)" - [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1))) - (set (match_dup 2) (zero_extend:DI (match_dup 3)))])] + [(const_int 0)] { - aarch64_swap_ldrstr_operands (operands, true); + aarch64_finish_ldpstp_peephole (operands, true, ZERO_EXTEND); + DONE; }) ;; Handle storing of a floating point zero with integer data. @@ -163,10 +163,10 @@ (define_peephole2 (set (match_operand: 2 "memory_operand" "") (match_operand: 3 "aarch64_reg_zero_or_fp_zero" ""))] "aarch64_operands_ok_for_ldpstp (operands, false, mode)" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] + [(const_int 0)] { - aarch64_swap_ldrstr_operands (operands, false); + aarch64_finish_ldpstp_peephole (operands, false); + DONE; }) ;; Handle consecutive load/store whose offset is out of the range diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def index 6b4f4e17dd5..1e0d770f72f 100644 --- a/gcc/config/aarch64/aarch64-modes.def +++ b/gcc/config/aarch64/aarch64-modes.def @@ -93,9 +93,13 @@ INT_MODE (XI, 64); /* V8DI mode. */ VECTOR_MODE_WITH_PREFIX (V, INT, DI, 8, 5); - ADJUST_ALIGNMENT (V8DI, 8); +/* V2x4QImode. Used in load/store pair patterns. */ +VECTOR_MODE_WITH_PREFIX (V2x, INT, QI, 4, 5); +ADJUST_NUNITS (V2x4QI, 8); +ADJUST_ALIGNMENT (V2x4QI, 4); + /* Define Advanced SIMD modes for structures of 2, 3 and 4 d-registers. */ #define ADV_SIMD_D_REG_STRUCT_MODES(NVECS, VB, VH, VS, VD) \ VECTOR_MODES_WITH_PREFIX (V##NVECS##x, INT, 8, 3); \ diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index e463fd5c817..2ab54f244a7 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -967,6 +967,8 @@ void aarch64_split_compare_and_swap (rtx op[]); void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx); bool aarch64_gen_adjusted_ldpstp (rtx *, bool, machine_mode, RTX_CODE); +void aarch64_finish_ldpstp_peephole (rtx *, bool, + enum rtx_code = (enum rtx_code)0); void aarch64_expand_sve_vec_cmp_int (rtx, rtx_code, rtx, rtx); bool aarch64_expand_sve_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); @@ -1022,8 +1024,9 @@ bool aarch64_mergeable_load_pair_p (machine_mode, rtx, rtx); bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode); bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, machine_mode); bool aarch64_mem_ok_with_ldpstp_policy_model (rtx, bool, machine_mode); -void aarch64_swap_ldrstr_operands (rtx *, bool); bool aarch64_ldpstp_operand_mode_p (machine_mode); +rtx aarch64_gen_load_pair (rtx, rtx, rtx, enum rtx_code = (enum rtx_code)0); +rtx aarch64_gen_store_pair (rtx, rtx, rtx); extern void aarch64_asm_output_pool_epilogue (FILE *, const char *, tree, HOST_WIDE_INT); diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index c6f2d582837..6f5080ab030 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -231,38 +231,6 @@ (define_insn "aarch64_store_lane0" [(set_attr "type" "neon_store1_1reg")] ) -(define_insn "load_pair" - [(set (match_operand:DREG 0 "register_operand") - (match_operand:DREG 1 "aarch64_mem_pair_operand")) - (set (match_operand:DREG2 2 "register_operand") - (match_operand:DREG2 3 "memory_operand"))] - "TARGET_FLOAT - && rtx_equal_p (XEXP (operands[3], 0), - plus_constant (Pmode, - XEXP (operands[1], 0), - GET_MODE_SIZE (mode)))" - {@ [ cons: =0 , 1 , =2 , 3 ; attrs: type ] - [ w , Ump , w , m ; neon_ldp ] ldp\t%d0, %d2, %z1 - [ r , Ump , r , m ; load_16 ] ldp\t%x0, %x2, %z1 - } -) - -(define_insn "vec_store_pair" - [(set (match_operand:DREG 0 "aarch64_mem_pair_operand") - (match_operand:DREG 1 "register_operand")) - (set (match_operand:DREG2 2 "memory_operand") - (match_operand:DREG2 3 "register_operand"))] - "TARGET_FLOAT - && rtx_equal_p (XEXP (operands[2], 0), - plus_constant (Pmode, - XEXP (operands[0], 0), - GET_MODE_SIZE (mode)))" - {@ [ cons: =0 , 1 , =2 , 3 ; attrs: type ] - [ Ump , w , m , w ; neon_stp ] stp\t%d1, %d3, %z0 - [ Ump , r , m , r ; store_16 ] stp\t%x1, %x3, %z0 - } -) - (define_insn "aarch64_simd_stp" [(set (match_operand:VP_2E 0 "aarch64_mem_pair_lanes_operand") (vec_duplicate:VP_2E (match_operand: 1 "register_operand")))] @@ -273,34 +241,6 @@ (define_insn "aarch64_simd_stp" } ) -(define_insn "load_pair" - [(set (match_operand:VQ 0 "register_operand" "=w") - (match_operand:VQ 1 "aarch64_mem_pair_operand" "Ump")) - (set (match_operand:VQ2 2 "register_operand" "=w") - (match_operand:VQ2 3 "memory_operand" "m"))] - "TARGET_FLOAT - && rtx_equal_p (XEXP (operands[3], 0), - plus_constant (Pmode, - XEXP (operands[1], 0), - GET_MODE_SIZE (mode)))" - "ldp\\t%q0, %q2, %z1" - [(set_attr "type" "neon_ldp_q")] -) - -(define_insn "vec_store_pair" - [(set (match_operand:VQ 0 "aarch64_mem_pair_operand" "=Ump") - (match_operand:VQ 1 "register_operand" "w")) - (set (match_operand:VQ2 2 "memory_operand" "=m") - (match_operand:VQ2 3 "register_operand" "w"))] - "TARGET_FLOAT - && rtx_equal_p (XEXP (operands[2], 0), - plus_constant (Pmode, - XEXP (operands[0], 0), - GET_MODE_SIZE (mode)))" - "stp\\t%q1, %q3, %z0" - [(set_attr "type" "neon_stp_q")] -) - (define_expand "@aarch64_split_simd_mov" [(set (match_operand:VQMOV 0) (match_operand:VQMOV 1))] diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index ccf081d2a16..1f6094bf1bc 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -9056,59 +9056,81 @@ aarch64_pop_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment, } } -/* Generate and return a store pair instruction of mode MODE to store - register REG1 to MEM1 and register REG2 to MEM2. */ +static machine_mode +aarch64_pair_mode_for_mode (machine_mode mode) +{ + if (known_eq (GET_MODE_SIZE (mode), 4)) + return E_V2x4QImode; + else if (known_eq (GET_MODE_SIZE (mode), 8)) + return E_V2x8QImode; + else if (known_eq (GET_MODE_SIZE (mode), 16)) + return E_V2x16QImode; + else + gcc_unreachable (); +} static rtx -aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2, - rtx reg2) +aarch64_pair_mem_from_base (rtx mem) { - switch (mode) - { - case E_DImode: - return gen_store_pair_dw_didi (mem1, reg1, mem2, reg2); - - case E_DFmode: - return gen_store_pair_dw_dfdf (mem1, reg1, mem2, reg2); - - case E_TFmode: - return gen_store_pair_dw_tftf (mem1, reg1, mem2, reg2); + auto pair_mode = aarch64_pair_mode_for_mode (GET_MODE (mem)); + mem = adjust_bitfield_address_nv (mem, pair_mode, 0); + gcc_assert (aarch64_mem_pair_lanes_operand (mem, pair_mode)); + return mem; +} - case E_V4SImode: - return gen_vec_store_pairv4siv4si (mem1, reg1, mem2, reg2); +/* Generate and return a store pair instruction to store REG1 and REG2 + into memory starting at BASE_MEM. All three rtxes should have modes of the + same size. */ - case E_V16QImode: - return gen_vec_store_pairv16qiv16qi (mem1, reg1, mem2, reg2); +rtx +aarch64_gen_store_pair (rtx base_mem, rtx reg1, rtx reg2) +{ + rtx pair_mem = aarch64_pair_mem_from_base (base_mem); - default: - gcc_unreachable (); - } + return gen_rtx_SET (pair_mem, + gen_rtx_UNSPEC (GET_MODE (pair_mem), + gen_rtvec (2, reg1, reg2), + UNSPEC_STP)); } -/* Generate and regurn a load pair isntruction of mode MODE to load register - REG1 from MEM1 and register REG2 from MEM2. */ +/* Generate and return a load pair instruction to load a pair of + registers starting at BASE_MEM into REG1 and REG2. If CODE is + UNKNOWN, all three rtxes should have modes of the same size. + Otherwise, CODE is {SIGN,ZERO}_EXTEND, base_mem should be in SImode, + and REG{1,2} should be in DImode. */ -static rtx -aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2, - rtx mem2) +rtx +aarch64_gen_load_pair (rtx reg1, rtx reg2, rtx base_mem, enum rtx_code code) { - switch (mode) - { - case E_DImode: - return gen_load_pair_dw_didi (reg1, mem1, reg2, mem2); + rtx pair_mem = aarch64_pair_mem_from_base (base_mem); - case E_DFmode: - return gen_load_pair_dw_dfdf (reg1, mem1, reg2, mem2); - - case E_TFmode: - return gen_load_pair_dw_tftf (reg1, mem1, reg2, mem2); + const bool any_extend_p = (code == ZERO_EXTEND || code == SIGN_EXTEND); + if (any_extend_p) + { + gcc_checking_assert (GET_MODE (base_mem) == SImode); + gcc_checking_assert (GET_MODE (reg1) == DImode); + gcc_checking_assert (GET_MODE (reg2) == DImode); + } + else + gcc_assert (code == UNKNOWN); + + rtx unspecs[2] = { + gen_rtx_UNSPEC (any_extend_p ? SImode : GET_MODE (reg1), + gen_rtvec (1, pair_mem), + UNSPEC_LDP_FST), + gen_rtx_UNSPEC (any_extend_p ? SImode : GET_MODE (reg2), + gen_rtvec (1, copy_rtx (pair_mem)), + UNSPEC_LDP_SND) + }; - case E_V4SImode: - return gen_load_pairv4siv4si (reg1, mem1, reg2, mem2); + if (any_extend_p) + for (int i = 0; i < 2; i++) + unspecs[i] = gen_rtx_fmt_e (code, DImode, unspecs[i]); - default: - gcc_unreachable (); - } + return gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (2, + gen_rtx_SET (reg1, unspecs[0]), + gen_rtx_SET (reg2, unspecs[1]))); } /* Return TRUE if return address signing should be enabled for the current @@ -9321,8 +9343,19 @@ aarch64_save_callee_saves (poly_int64 bytes_below_sp, offset -= fp_offset; } rtx mem = gen_frame_mem (mode, plus_constant (Pmode, base_rtx, offset)); - bool need_cfa_note_p = (base_rtx != stack_pointer_rtx); + rtx cfa_base = stack_pointer_rtx; + poly_int64 cfa_offset = sp_offset; + + if (hard_fp_valid_p && frame_pointer_needed) + { + cfa_base = hard_frame_pointer_rtx; + cfa_offset += (bytes_below_sp - frame.bytes_below_hard_fp); + } + + rtx cfa_mem = gen_frame_mem (mode, + plus_constant (Pmode, + cfa_base, cfa_offset)); unsigned int regno2; if (!aarch64_sve_mode_p (mode) && i + 1 < regs.size () @@ -9331,45 +9364,37 @@ aarch64_save_callee_saves (poly_int64 bytes_below_sp, frame.reg_offset[regno2] - frame.reg_offset[regno])) { rtx reg2 = gen_rtx_REG (mode, regno2); - rtx mem2; offset += GET_MODE_SIZE (mode); - mem2 = gen_frame_mem (mode, plus_constant (Pmode, base_rtx, offset)); - insn = emit_insn (aarch64_gen_store_pair (mode, mem, reg, mem2, - reg2)); - - /* The first part of a frame-related parallel insn is - always assumed to be relevant to the frame - calculations; subsequent parts, are only - frame-related if explicitly marked. */ + insn = emit_insn (aarch64_gen_store_pair (mem, reg, reg2)); + if (aarch64_emit_cfi_for_reg_p (regno2)) { - if (need_cfa_note_p) - aarch64_add_cfa_expression (insn, reg2, stack_pointer_rtx, - sp_offset + GET_MODE_SIZE (mode)); - else - RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; + rtx cfa_mem2 = adjust_address_nv (cfa_mem, + Pmode, + GET_MODE_SIZE (mode)); + add_reg_note (insn, REG_CFA_OFFSET, + gen_rtx_SET (cfa_mem2, reg2)); } regno = regno2; ++i; } else if (mode == VNx2DImode && BYTES_BIG_ENDIAN) - { - insn = emit_insn (gen_aarch64_pred_mov (mode, mem, ptrue, reg)); - need_cfa_note_p = true; - } + insn = emit_insn (gen_aarch64_pred_mov (mode, mem, ptrue, reg)); else if (aarch64_sve_mode_p (mode)) insn = emit_insn (gen_rtx_SET (mem, reg)); else insn = emit_move_insn (mem, reg); RTX_FRAME_RELATED_P (insn) = frame_related_p; - if (frame_related_p && need_cfa_note_p) - aarch64_add_cfa_expression (insn, reg, stack_pointer_rtx, sp_offset); + + if (frame_related_p) + add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (cfa_mem, reg)); } } + /* Emit code to restore the callee registers in REGS, ignoring pop candidates and any other registers that are handled separately. Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. @@ -9425,12 +9450,7 @@ aarch64_restore_callee_saves (poly_int64 bytes_below_sp, frame.reg_offset[regno2] - frame.reg_offset[regno])) { rtx reg2 = gen_rtx_REG (mode, regno2); - rtx mem2; - - offset += GET_MODE_SIZE (mode); - mem2 = gen_frame_mem (mode, plus_constant (Pmode, base_rtx, offset)); - emit_insn (aarch64_gen_load_pair (mode, reg, mem, reg2, mem2)); - + emit_insn (aarch64_gen_load_pair (reg, reg2, mem)); *cfi_ops = alloc_reg_note (REG_CFA_RESTORE, reg2, *cfi_ops); regno = regno2; ++i; @@ -9762,9 +9782,9 @@ aarch64_process_components (sbitmap components, bool prologue_p) : gen_rtx_SET (reg2, mem2); if (prologue_p) - insn = emit_insn (aarch64_gen_store_pair (mode, mem, reg, mem2, reg2)); + insn = emit_insn (aarch64_gen_store_pair (mem, reg, reg2)); else - insn = emit_insn (aarch64_gen_load_pair (mode, reg, mem, reg2, mem2)); + insn = emit_insn (aarch64_gen_load_pair (reg, reg2, mem)); if (frame_related_p || frame_related2_p) { @@ -10983,12 +11003,18 @@ aarch64_classify_address (struct aarch64_address_info *info, mode of the corresponding addressing mode is half of that. */ if (type == ADDR_QUERY_LDP_STP_N) { - if (known_eq (GET_MODE_SIZE (mode), 16)) + if (known_eq (GET_MODE_SIZE (mode), 32)) + mode = V16QImode; + else if (known_eq (GET_MODE_SIZE (mode), 16)) mode = DFmode; else if (known_eq (GET_MODE_SIZE (mode), 8)) mode = SFmode; else return false; + + /* This isn't really an Advanced SIMD struct mode, but a mode + used to represent the complete mem in a load/store pair. */ + advsimd_struct_p = false; } bool allow_reg_index_p = (!load_store_pair_p @@ -12609,7 +12635,8 @@ aarch64_print_operand (FILE *f, rtx x, int code) if (!MEM_P (x) || (code == 'y' && maybe_ne (GET_MODE_SIZE (mode), 8) - && maybe_ne (GET_MODE_SIZE (mode), 16))) + && maybe_ne (GET_MODE_SIZE (mode), 16) + && maybe_ne (GET_MODE_SIZE (mode), 32))) { output_operand_lossage ("invalid operand for '%%%c'", code); return; @@ -25431,10 +25458,8 @@ aarch64_copy_one_block_and_progress_pointers (rtx *src, rtx *dst, *src = adjust_address (*src, mode, 0); *dst = adjust_address (*dst, mode, 0); /* Emit the memcpy. */ - emit_insn (aarch64_gen_load_pair (mode, reg1, *src, reg2, - aarch64_progress_pointer (*src))); - emit_insn (aarch64_gen_store_pair (mode, *dst, reg1, - aarch64_progress_pointer (*dst), reg2)); + emit_insn (aarch64_gen_load_pair (reg1, reg2, *src)); + emit_insn (aarch64_gen_store_pair (*dst, reg1, reg2)); /* Move the pointers forward. */ *src = aarch64_move_pointer (*src, 32); *dst = aarch64_move_pointer (*dst, 32); @@ -25613,8 +25638,7 @@ aarch64_set_one_block_and_progress_pointer (rtx src, rtx *dst, /* "Cast" the *dst to the correct mode. */ *dst = adjust_address (*dst, mode, 0); /* Emit the memset. */ - emit_insn (aarch64_gen_store_pair (mode, *dst, src, - aarch64_progress_pointer (*dst), src)); + emit_insn (aarch64_gen_store_pair (*dst, src, src)); /* Move the pointers forward. */ *dst = aarch64_move_pointer (*dst, 32); @@ -26812,6 +26836,22 @@ aarch64_swap_ldrstr_operands (rtx* operands, bool load) } } +void +aarch64_finish_ldpstp_peephole (rtx *operands, bool load_p, enum rtx_code code) +{ + aarch64_swap_ldrstr_operands (operands, load_p); + + if (load_p) + emit_insn (aarch64_gen_load_pair (operands[0], operands[2], + operands[1], code)); + else + { + gcc_assert (code == UNKNOWN); + emit_insn (aarch64_gen_store_pair (operands[0], operands[1], + operands[3])); + } +} + /* Taking X and Y to be HOST_WIDE_INT pointers, return the result of a comparison between the two. */ int @@ -26993,8 +27033,8 @@ bool aarch64_gen_adjusted_ldpstp (rtx *operands, bool load, machine_mode mode, RTX_CODE code) { - rtx base, offset_1, offset_3, t1, t2; - rtx mem_1, mem_2, mem_3, mem_4; + rtx base, offset_1, offset_3; + rtx mem_1, mem_2; rtx temp_operands[8]; HOST_WIDE_INT off_val_1, off_val_3, base_off, new_off_1, new_off_3, stp_off_upper_limit, stp_off_lower_limit, msize; @@ -27019,21 +27059,17 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load, if (load) { mem_1 = copy_rtx (temp_operands[1]); - mem_2 = copy_rtx (temp_operands[3]); - mem_3 = copy_rtx (temp_operands[5]); - mem_4 = copy_rtx (temp_operands[7]); + mem_2 = copy_rtx (temp_operands[5]); } else { mem_1 = copy_rtx (temp_operands[0]); - mem_2 = copy_rtx (temp_operands[2]); - mem_3 = copy_rtx (temp_operands[4]); - mem_4 = copy_rtx (temp_operands[6]); + mem_2 = copy_rtx (temp_operands[4]); gcc_assert (code == UNKNOWN); } extract_base_offset_in_addr (mem_1, &base, &offset_1); - extract_base_offset_in_addr (mem_3, &base, &offset_3); + extract_base_offset_in_addr (mem_2, &base, &offset_3); gcc_assert (base != NULL_RTX && offset_1 != NULL_RTX && offset_3 != NULL_RTX); @@ -27097,63 +27133,48 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load, replace_equiv_address_nv (mem_1, plus_constant (Pmode, operands[8], new_off_1), true); replace_equiv_address_nv (mem_2, plus_constant (Pmode, operands[8], - new_off_1 + msize), true); - replace_equiv_address_nv (mem_3, plus_constant (Pmode, operands[8], new_off_3), true); - replace_equiv_address_nv (mem_4, plus_constant (Pmode, operands[8], - new_off_3 + msize), true); if (!aarch64_mem_pair_operand (mem_1, mode) - || !aarch64_mem_pair_operand (mem_3, mode)) + || !aarch64_mem_pair_operand (mem_2, mode)) return false; - if (code == ZERO_EXTEND) - { - mem_1 = gen_rtx_ZERO_EXTEND (DImode, mem_1); - mem_2 = gen_rtx_ZERO_EXTEND (DImode, mem_2); - mem_3 = gen_rtx_ZERO_EXTEND (DImode, mem_3); - mem_4 = gen_rtx_ZERO_EXTEND (DImode, mem_4); - } - else if (code == SIGN_EXTEND) - { - mem_1 = gen_rtx_SIGN_EXTEND (DImode, mem_1); - mem_2 = gen_rtx_SIGN_EXTEND (DImode, mem_2); - mem_3 = gen_rtx_SIGN_EXTEND (DImode, mem_3); - mem_4 = gen_rtx_SIGN_EXTEND (DImode, mem_4); - } - if (load) { operands[0] = temp_operands[0]; operands[1] = mem_1; operands[2] = temp_operands[2]; - operands[3] = mem_2; operands[4] = temp_operands[4]; - operands[5] = mem_3; + operands[5] = mem_2; operands[6] = temp_operands[6]; - operands[7] = mem_4; } else { operands[0] = mem_1; operands[1] = temp_operands[1]; - operands[2] = mem_2; operands[3] = temp_operands[3]; - operands[4] = mem_3; + operands[4] = mem_2; operands[5] = temp_operands[5]; - operands[6] = mem_4; operands[7] = temp_operands[7]; } /* Emit adjusting instruction. */ emit_insn (gen_rtx_SET (operands[8], plus_constant (DImode, base, base_off))); /* Emit ldp/stp instructions. */ - t1 = gen_rtx_SET (operands[0], operands[1]); - t2 = gen_rtx_SET (operands[2], operands[3]); - emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, t1, t2))); - t1 = gen_rtx_SET (operands[4], operands[5]); - t2 = gen_rtx_SET (operands[6], operands[7]); - emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, t1, t2))); + if (load) + { + emit_insn (aarch64_gen_load_pair (operands[0], operands[2], + operands[1], code)); + emit_insn (aarch64_gen_load_pair (operands[4], operands[6], + operands[5], code)); + } + else + { + emit_insn (aarch64_gen_store_pair (operands[0], operands[1], + operands[3])); + emit_insn (aarch64_gen_store_pair (operands[4], operands[5], + operands[7])); + } return true; } diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c92a51690c5..ffb6b0ba749 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -175,6 +175,9 @@ (define_c_enum "unspec" [ UNSPEC_GOTSMALLTLS UNSPEC_GOTTINYPIC UNSPEC_GOTTINYTLS + UNSPEC_STP + UNSPEC_LDP_FST + UNSPEC_LDP_SND UNSPEC_LD1 UNSPEC_LD2 UNSPEC_LD2_DREG @@ -453,6 +456,11 @@ (define_attr "predicated" "yes,no" (const_string "no")) ;; may chose to hold the tracking state encoded in SP. (define_attr "speculation_barrier" "true,false" (const_string "false")) +;; Attribute use to identify load pair and store pair instructions. +;; Currently the attribute is only applied to the non-writeback ldp/stp +;; patterns. +(define_attr "ldpstp" "ldp,stp,none" (const_string "none")) + ;; ------------------------------------------------------------------- ;; Pipeline descriptions and scheduling ;; ------------------------------------------------------------------- @@ -1735,100 +1743,62 @@ (define_expand "setmemdi" FAIL; }) -;; Operands 1 and 3 are tied together by the final condition; so we allow -;; fairly lax checking on the second memory operation. -(define_insn "load_pair_sw_" - [(set (match_operand:SX 0 "register_operand") - (match_operand:SX 1 "aarch64_mem_pair_operand")) - (set (match_operand:SX2 2 "register_operand") - (match_operand:SX2 3 "memory_operand"))] - "rtx_equal_p (XEXP (operands[3], 0), - plus_constant (Pmode, - XEXP (operands[1], 0), - GET_MODE_SIZE (mode)))" - {@ [ cons: =0 , 1 , =2 , 3 ; attrs: type , arch ] - [ r , Ump , r , m ; load_8 , * ] ldp\t%w0, %w2, %z1 - [ w , Ump , w , m ; neon_load1_2reg , fp ] ldp\t%s0, %s2, %z1 - } -) - -;; Storing different modes that can still be merged -(define_insn "load_pair_dw_" - [(set (match_operand:DX 0 "register_operand") - (match_operand:DX 1 "aarch64_mem_pair_operand")) - (set (match_operand:DX2 2 "register_operand") - (match_operand:DX2 3 "memory_operand"))] - "rtx_equal_p (XEXP (operands[3], 0), - plus_constant (Pmode, - XEXP (operands[1], 0), - GET_MODE_SIZE (mode)))" - {@ [ cons: =0 , 1 , =2 , 3 ; attrs: type , arch ] - [ r , Ump , r , m ; load_16 , * ] ldp\t%x0, %x2, %z1 - [ w , Ump , w , m ; neon_load1_2reg , fp ] ldp\t%d0, %d2, %z1 - } -) - -(define_insn "load_pair_dw_" - [(set (match_operand:TX 0 "register_operand" "=w") - (match_operand:TX 1 "aarch64_mem_pair_operand" "Ump")) - (set (match_operand:TX2 2 "register_operand" "=w") - (match_operand:TX2 3 "memory_operand" "m"))] - "TARGET_SIMD - && rtx_equal_p (XEXP (operands[3], 0), - plus_constant (Pmode, - XEXP (operands[1], 0), - GET_MODE_SIZE (mode)))" - "ldp\\t%q0, %q2, %z1" +(define_insn "*load_pair_" + [(set (match_operand:GPI 0 "aarch64_ldp_reg_operand") + (unspec [ + (match_operand: 1 "aarch64_mem_pair_lanes_operand") + ] UNSPEC_LDP_FST)) + (set (match_operand:GPI 2 "aarch64_ldp_reg_operand") + (unspec [ + (match_dup 1) + ] UNSPEC_LDP_SND))] + "" + {@ [cons: =0, 1, =2; attrs: type, arch] + [ r, Umn, r; load_, * ] ldp\t%0, %2, %y1 + [ w, Umn, w; neon_load1_2reg, fp ] ldp\t%0, %2, %y1 + } + [(set_attr "ldpstp" "ldp")] +) + +(define_insn "*load_pair_16" + [(set (match_operand:TI 0 "aarch64_ldp_reg_operand" "=w") + (unspec [ + (match_operand:V2x16QI 1 "aarch64_mem_pair_lanes_operand" "Umn") + ] UNSPEC_LDP_FST)) + (set (match_operand:TI 2 "aarch64_ldp_reg_operand" "=w") + (unspec [ + (match_dup 1) + ] UNSPEC_LDP_SND))] + "TARGET_FLOAT" + "ldp\\t%q0, %q2, %y1" [(set_attr "type" "neon_ldp_q") - (set_attr "fp" "yes")] -) - -;; Operands 0 and 2 are tied together by the final condition; so we allow -;; fairly lax checking on the second memory operation. -(define_insn "store_pair_sw_" - [(set (match_operand:SX 0 "aarch64_mem_pair_operand") - (match_operand:SX 1 "aarch64_reg_zero_or_fp_zero")) - (set (match_operand:SX2 2 "memory_operand") - (match_operand:SX2 3 "aarch64_reg_zero_or_fp_zero"))] - "rtx_equal_p (XEXP (operands[2], 0), - plus_constant (Pmode, - XEXP (operands[0], 0), - GET_MODE_SIZE (mode)))" - {@ [ cons: =0 , 1 , =2 , 3 ; attrs: type , arch ] - [ Ump , rYZ , m , rYZ ; store_8 , * ] stp\t%w1, %w3, %z0 - [ Ump , w , m , w ; neon_store1_2reg , fp ] stp\t%s1, %s3, %z0 - } -) - -;; Storing different modes that can still be merged -(define_insn "store_pair_dw_" - [(set (match_operand:DX 0 "aarch64_mem_pair_operand") - (match_operand:DX 1 "aarch64_reg_zero_or_fp_zero")) - (set (match_operand:DX2 2 "memory_operand") - (match_operand:DX2 3 "aarch64_reg_zero_or_fp_zero"))] - "rtx_equal_p (XEXP (operands[2], 0), - plus_constant (Pmode, - XEXP (operands[0], 0), - GET_MODE_SIZE (mode)))" - {@ [ cons: =0 , 1 , =2 , 3 ; attrs: type , arch ] - [ Ump , rYZ , m , rYZ ; store_16 , * ] stp\t%x1, %x3, %z0 - [ Ump , w , m , w ; neon_store1_2reg , fp ] stp\t%d1, %d3, %z0 - } -) - -(define_insn "store_pair_dw_" - [(set (match_operand:TX 0 "aarch64_mem_pair_operand" "=Ump") - (match_operand:TX 1 "register_operand" "w")) - (set (match_operand:TX2 2 "memory_operand" "=m") - (match_operand:TX2 3 "register_operand" "w"))] - "TARGET_SIMD && - rtx_equal_p (XEXP (operands[2], 0), - plus_constant (Pmode, - XEXP (operands[0], 0), - GET_MODE_SIZE (TFmode)))" - "stp\\t%q1, %q3, %z0" + (set_attr "fp" "yes") + (set_attr "ldpstp" "ldp")] +) + +(define_insn "*store_pair_" + [(set (match_operand: 0 "aarch64_mem_pair_lanes_operand") + (unspec: + [(match_operand:GPI 1 "aarch64_stp_reg_operand") + (match_operand:GPI 2 "aarch64_stp_reg_operand")] UNSPEC_STP))] + "" + {@ [cons: =0, 1, 2; attrs: type , arch] + [ Umn, rYZ, rYZ; store_, * ] stp\t%1, %2, %y0 + [ Umn, w, w; neon_store1_2reg , fp ] stp\t%1, %2, %y0 + } + [(set_attr "ldpstp" "stp")] +) + +(define_insn "*store_pair_16" + [(set (match_operand:V2x16QI 0 "aarch64_mem_pair_lanes_operand" "=Umn") + (unspec:V2x16QI + [(match_operand:TI 1 "aarch64_ldp_reg_operand" "w") + (match_operand:TI 2 "aarch64_ldp_reg_operand" "w")] UNSPEC_STP))] + "TARGET_FLOAT" + "stp\t%q1, %q2, %y0" [(set_attr "type" "neon_stp_q") - (set_attr "fp" "yes")] + (set_attr "fp" "yes") + (set_attr "ldpstp" "stp")] ) ;; Writeback load/store pair patterns. @@ -2074,14 +2044,15 @@ (define_insn "*extendsidi2_aarch64" (define_insn "*load_pair_extendsidi2_aarch64" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI (match_operand:SI 1 "aarch64_mem_pair_operand" "Ump"))) + (sign_extend:DI (unspec:SI [ + (match_operand:V2x4QI 1 "aarch64_mem_pair_lanes_operand" "Umn") + ] UNSPEC_LDP_FST))) (set (match_operand:DI 2 "register_operand" "=r") - (sign_extend:DI (match_operand:SI 3 "memory_operand" "m")))] - "rtx_equal_p (XEXP (operands[3], 0), - plus_constant (Pmode, - XEXP (operands[1], 0), - GET_MODE_SIZE (SImode)))" - "ldpsw\\t%0, %2, %z1" + (sign_extend:DI (unspec:SI [ + (match_dup 1) + ] UNSPEC_LDP_SND)))] + "" + "ldpsw\\t%0, %2, %y1" [(set_attr "type" "load_8")] ) @@ -2101,16 +2072,17 @@ (define_insn "*zero_extendsidi2_aarch64" (define_insn "*load_pair_zero_extendsidi2_aarch64" [(set (match_operand:DI 0 "register_operand") - (zero_extend:DI (match_operand:SI 1 "aarch64_mem_pair_operand"))) + (zero_extend:DI (unspec:SI [ + (match_operand:V2x4QI 1 "aarch64_mem_pair_lanes_operand") + ] UNSPEC_LDP_FST))) (set (match_operand:DI 2 "register_operand") - (zero_extend:DI (match_operand:SI 3 "memory_operand")))] - "rtx_equal_p (XEXP (operands[3], 0), - plus_constant (Pmode, - XEXP (operands[1], 0), - GET_MODE_SIZE (SImode)))" - {@ [ cons: =0 , 1 , =2 , 3 ; attrs: type , arch ] - [ r , Ump , r , m ; load_8 , * ] ldp\t%w0, %w2, %z1 - [ w , Ump , w , m ; neon_load1_2reg , fp ] ldp\t%s0, %s2, %z1 + (zero_extend:DI (unspec:SI [ + (match_dup 1) + ] UNSPEC_LDP_SND)))] + "" + {@ [ cons: =0 , 1 , =2; attrs: type , arch] + [ r , Umn , r ; load_8 , * ] ldp\t%w0, %w2, %y1 + [ w , Umn , w ; neon_load1_2reg, fp ] ldp\t%s0, %s2, %y1 } ) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index a920de99ffc..fd8dd6db349 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1435,6 +1435,9 @@ (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") (SI "V2SI") (SF "V2SF") (DI "V2DI") (DF "V2DF")]) +;; Load/store pair mode. +(define_mode_attr VPAIR [(SI "V2x4QI") (DI "V2x8QI")]) + ;; Register suffix for double-length mode. (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")]) diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index b647e5af7c6..80f2e03d8de 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -266,10 +266,12 @@ (define_special_predicate "aarch64_mem_pair_operator" (match_test "known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (GET_MODE (op)))")))) -(define_predicate "aarch64_mem_pair_operand" - (and (match_code "mem") - (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), false, - ADDR_QUERY_LDP_STP)"))) +;; Like aarch64_mem_pair_operator, but additionally check the +;; address is suitable. +(define_special_predicate "aarch64_mem_pair_operand" + (and (match_operand 0 "aarch64_mem_pair_operator") + (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), + false, ADDR_QUERY_LDP_STP)"))) (define_predicate "pmode_plus_operator" (and (match_code "plus") From patchwork Thu Nov 16 18:11:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Coplan X-Patchwork-Id: 165917 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6359:6513:b0:164:83eb:24d7 with SMTP id sk19csp45248rwb; Thu, 16 Nov 2023 10:12:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IHrlEAqjn2+ytyls0qpI4eDH4Wn2YoeLR0pXPobPUnk4/uBTeYXp4Dd9C4OCIBcQycs02Hp X-Received: by 2002:a05:6870:c107:b0:1c3:91b9:e1e7 with SMTP id f7-20020a056870c10700b001c391b9e1e7mr21517474oad.21.1700158353451; Thu, 16 Nov 2023 10:12:33 -0800 (PST) ARC-Seal: i=4; a=rsa-sha256; t=1700158353; cv=pass; d=google.com; s=arc-20160816; b=OLkKS2jRQhBYf+F6J0a7SLaHjRPMKvyWHTAgNPVpisBEx1VM5KWe6SQUS5AsGne9Wz YuElh9dEYnMk73zjk3d0TxGKCpZd4xM5XWiNlJdAg+DzgOLRxfKmJ3zzFqkBd50ZeVBz 5AYl4cwH0YXMGwyPHNSGucPtFTzTm+UcSG/rgxwFLv7xvZoH84kTFn+afv/qSzXo2HMc E1aAvPc65H07ZAJWnUFC+2lIGiFJsyG6lWS3cB9JCKSqZfaX+cH83IZG82sI6EYfVGr+ 7qaiYYSB679MiDqUdSZrntpsD2xhmobsN+zgxzIxED21J8Cl3QY24Qt5EUU8Tr59n5B+ 1Ufw== ARC-Message-Signature: i=4; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:original-authentication-results :nodisclaimer:mime-version:content-transfer-encoding :content-disposition:message-id:subject:cc:to:from:date :authentication-results-original:dkim-signature:dkim-signature :arc-filter:dmarc-filter:delivered-to; bh=+7mceBoXarMyScg/yo+X3cj9n/dy8O2Mwso4vCwnpLY=; fh=oBREkWEOK+vBJwK/8m3Xyoxxy+JRDn9wOQNt/tlZ9u8=; b=n9xjeteBROTP+xVPGlBoeVHGF5AovKB0I0HFnoMJxs+SJ72JfnnrYJNoAMLeZESNok RpCmkUNjqQL5tPksS/VHznsmbL9tWqXB/87M91rWGl/zBwZTLLQN601X4hGbl2b4LZSg ZZiylmBmgIvFAuPBAii9yuml50cd/ZEZimcLTrViaCWRS8Q4x/rZk/V53xBJObmqbJxO d5E2GjpnktLEQDVr42yp5jd3q/9M6uRTNRp8Dsz3TC0Wqwh4EHGCzVsYr3tzCViW8RzS ZsWLxe2cf7TgqSUJLwEtOa6niP2jwtRAyuyiwhPkf+Ux+MVRLC+mcvHY5Pw/HMHOK4++ LhwA== ARC-Authentication-Results: i=4; mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=uzigqxuY; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=uzigqxuY; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id o8-20020a05622a044800b004195ad3b40dsi12121617qtx.229.2023.11.16.10.12.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Nov 2023 10:12:33 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=uzigqxuY; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=uzigqxuY; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 31A8E387689C for ; Thu, 16 Nov 2023 18:12:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2042.outbound.protection.outlook.com [40.107.21.42]) by sourceware.org (Postfix) with ESMTPS id 9F890387544A for ; Thu, 16 Nov 2023 18:12:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9F890387544A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9F890387544A Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.21.42 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1700158329; cv=pass; b=wMzEOu9uo9xgeXOvZVvb4ScMLdiuSk7pa0QtRFKOv3jy11bPL1A4mYVp4iDcpWfiZwNqNbupH+2G99JJJeFGoAIWST2zN3JXE9MUdrpocOGCs3N9xGlz+DkxBwUyBNSkhT2ad46rLbtYavvF4MTwyrGD4VNgakevBT0y5QtsJMM= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1700158329; c=relaxed/simple; bh=HLABBGti7nTiqjeeVGM4qBzjAcPZiej64JYrD+gAO/A=; h=DKIM-Signature:DKIM-Signature:Date:From:To:Subject:Message-ID: MIME-Version; b=AzlLB90hZcTzklxvlyAuFy7o7hG5BQiXrGrEpMHqCYa9O8I/lpl1pfqq2bdMK4X4pvkNapXUMc1D5e2eOZSlcMcwkIm4ESXgXNhyy0xNFNXKdRiA9phW386bF691F1gLvD+jHiL42/+V3G6sAGNqzKhAH/k5Nb46ySYKSySV7QM= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=gMYkjWRS6WpJ9dP+P0Xbm18G3pCqpzJSzPxfZjMYQoHNfpcbJ9UvuLWCeVeJZ4Tm/TwC7zXWiyMGx1/LhmDoAFYEpk/xicS02wHo/61+QYx5gExxXUiJbCElZPBuHKvC7XxJj5t5537WWzWZTZ0V40iUmgB4EtONxg2pocfKwlEwMee/q0L3WfFQSrj4b9ssNRbE61as2YkIubsMehaUhEX7yf4c/DyZQvf/oik7ulFXJuEPZgc9+JkRH+jO4t4q5wfKAeCm/Htgbv7FBOaglnN3+uuwOMxS74FPL/9EpWiMaIfya61CZ2nLINY9xItzv6k9/bU/drzpyk4FVCwTew== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+7mceBoXarMyScg/yo+X3cj9n/dy8O2Mwso4vCwnpLY=; b=W4sBAaJ/P0Ki2MK6IP/Vq5rg8Ru8SZ1VchU6d7Mfx+ZnT2jC7i8reJrtLDlLxN+FQmJb6A7n8kwGRP5xHUCBagsP2ydSjoxxgE8t8WbNHLNmbnuTzSkrd/qzbuvEk0eaufn9BdtpZd470QljMROpvk1hQcoLicRG0PyUs2koyUpskMyyMdUw56uVkEPHqhRM6mz3fAvGOuOkiApstTLUHG1j+UP+OdHwIOTDNXWREiR7GMvq3dhVpJURF3RGSTgDP354Ku8PoGgDMafIobfBELlAOihkoPNcpTnl/CcwnD6wlNVsDA0r5wafRa8GQW2Ea/sotcrk/Bcqtyl0T1pWqg== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+7mceBoXarMyScg/yo+X3cj9n/dy8O2Mwso4vCwnpLY=; b=uzigqxuYKguq8XIsSi4SkRL1aZASXTHZFN+Z00sWDdImx70RqdfLIBtIZfvP1RefGP5m0w9SzbSCN2bFZW1EZQtj/NmwZTbJkmm4kqrTzwjko1BC6blLP7hLXlmFl1hC65QStTN/13g4uDuy5nCEYQajrKmvyR4b1BP3FKtNhBA= Received: from DU6P191CA0024.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:540::14) by DB9PR08MB9948.eurprd08.prod.outlook.com (2603:10a6:10:3d0::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.21; Thu, 16 Nov 2023 18:12:03 +0000 Received: from DB5PEPF00014B9D.eurprd02.prod.outlook.com (2603:10a6:10:540:cafe::c8) by DU6P191CA0024.outlook.office365.com (2603:10a6:10:540::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.23 via Frontend Transport; Thu, 16 Nov 2023 18:12:03 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DB5PEPF00014B9D.mail.protection.outlook.com (10.167.8.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.20 via Frontend Transport; Thu, 16 Nov 2023 18:12:03 +0000 Received: ("Tessian outbound 20615a7e7970:v228"); Thu, 16 Nov 2023 18:12:03 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 78f2a8bd7b9ed5c8 X-CR-MTA-TID: 64aa7808 Received: from fec4e5b43316.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 429A6E3D-4E34-48CF-8DA2-E0E9FA38047C.1; Thu, 16 Nov 2023 18:11:52 +0000 Received: from EUR04-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id fec4e5b43316.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 16 Nov 2023 18:11:52 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Gn2j45s0cOkVEgF9oB9VEZoftmwSmBIiPtdoRcpFU4kKguWevJ54GR0yzu9rhqptXP8kXVo1VROj5AYwqVcNpYKhRsEeKGOii2mQXLz4q+n0Us6P0D7deIbmBzTWsBj/FFLRzOK1/hUQvwae6bJPa/zClxMBaxTmTbvtwY3wCuNN1uBW96gv4xrS1RrX+OvGumCT8WtEeBlF374LRC7DpqVvTl3udwhWPxwM/xI5hrZxGZb3QAh3dZR+gg01Q6gJ1rn/N3ktIuuBOLv52oOc83n0tBIpQLAVvIPew+cxJOFfmbea1YxoNE53bd7DhnUvOv17A3oEf7QbT6FjBM2N4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+7mceBoXarMyScg/yo+X3cj9n/dy8O2Mwso4vCwnpLY=; b=EUBVbC+ETXcwmJKhiIrJ4z7wf76mNf1LylBgjVmmUCDGUPLMjyYVbddF4RoDEIhkDPZhFYLTk+Mt87GUx6F3h3jSDsSyBWhNX4/74UHb2nOCPDqYZnVhtWzQGnAT8ER3ktDLUKhSCX6lCDCGyDulgALi3gAlnPbT0IhivgXPcio8/Sz2p3PL6CF3JVhpfnHs9XFIUf7EfkWxNq4kKGWLWH/VB5KRusnaFaf+wZXTrZJmisyk9satIPLmQ2jgFQ+abzFr5A3DXxnajvuonLxqMeo8EQXxGhqNh2W2u2nq7+dG2h2b/hm7dBlc5cD9R2WXV49swBwyhRwnQP7m2Hot8g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+7mceBoXarMyScg/yo+X3cj9n/dy8O2Mwso4vCwnpLY=; b=uzigqxuYKguq8XIsSi4SkRL1aZASXTHZFN+Z00sWDdImx70RqdfLIBtIZfvP1RefGP5m0w9SzbSCN2bFZW1EZQtj/NmwZTbJkmm4kqrTzwjko1BC6blLP7hLXlmFl1hC65QStTN/13g4uDuy5nCEYQajrKmvyR4b1BP3FKtNhBA= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from PAWPR08MB8958.eurprd08.prod.outlook.com (2603:10a6:102:33e::15) by GV1PR08MB10424.eurprd08.prod.outlook.com (2603:10a6:150:15e::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6977.31; Thu, 16 Nov 2023 18:11:49 +0000 Received: from PAWPR08MB8958.eurprd08.prod.outlook.com ([fe80::8512:cc10:24d4:1919]) by PAWPR08MB8958.eurprd08.prod.outlook.com ([fe80::8512:cc10:24d4:1919%5]) with mapi id 15.20.6977.029; Thu, 16 Nov 2023 18:11:49 +0000 Date: Thu, 16 Nov 2023 18:11:46 +0000 From: Alex Coplan To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford , Kyrylo Tkachov Subject: [PATCH 11/11] aarch64: Use individual loads/stores for mem{cpy,set} expansion Message-ID: Content-Disposition: inline X-ClientProxiedBy: LO4P123CA0602.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:295::16) To PAWPR08MB8958.eurprd08.prod.outlook.com (2603:10a6:102:33e::15) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: PAWPR08MB8958:EE_|GV1PR08MB10424:EE_|DB5PEPF00014B9D:EE_|DB9PR08MB9948:EE_ X-MS-Office365-Filtering-Correlation-Id: ba73c5e0-4375-4db3-1b89-08dbe6cf88fd x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: H1R/vuaCgKdRuipxIqFsPb4r56tblKDgIKfi9a11PCHA71ZTcyvcbsGmjB7xSJceSoOSbgIQfujVnGNjIGAmO7zlKq14XPht18euxWMahKr/Z7tVc3uuc1UV5REYpPCcfGsIYqxXHQFmlBQ4RXhA3OzBTK0OYDeio9+am8X1jYqkfH8Ha6Hdgulz7BIOROfjwxMMjCh4YwTwbVxBLLXLhd/hVsD4lSfiYMzAO6wuMjCroDKGI0lonYVAfo7YBRI+3hy/K3IP79jWFFCeapbozyq+5ubUURewuO6jm2Nqnt/sUnQr5dZ54u6+LB1qw4Gt7Xy+nORlO3+hMMyw0PEPKxw6UYH3ouKG6CQrTtOfOZw2S35+auUlPKFWQ2/jVZtl3eV/Qo9QUJdWRpujdNounUEC6amDEki2SMh8SJ2I85eRdsMxmiEo8q+H4BWs9qlehJfeNEEq91y7vNxtgUz29wO6CtCG5TwBvLySaz88rvOXZfAg0KPecpu4ThyC5x+8ilWxzehNTGgMfAkZeo784v0ETC6Ly4lmDxty+mpnWvG07shjLiL8v8i+cRY6aSi6vSX02JuL2Qg3KMaNBOkI3ry6YSg+s0nbri6phzr5ozrP64Wc3SX1I8aRv69sanch X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PAWPR08MB8958.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(376002)(366004)(396003)(39860400002)(346002)(136003)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(2906002)(66556008)(478600001)(38100700002)(41300700001)(66476007)(66946007)(36756003)(86362001)(54906003)(6916009)(6486002)(316002)(2616005)(235185007)(5660300002)(6512007)(44144004)(26005)(6506007)(33964004)(6666004)(44832011)(4326008)(8936002)(83380400001)(8676002)(2700100001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB10424 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5PEPF00014B9D.eurprd02.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 629403fc-0ae7-4b08-13aa-08dbe6cf8066 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: b7eSbxf8yyKHhJPHWT1hUCTKz70YBq1jm7QClrrTNFMlGtg4PJRu/rLrPLLV/zFXEjHN+wTBFhC0GIuC7znTotHFAqu76eanIn9rxTVnl3rwj6eDgu7Kjrzp43YKZrZnrNu4nxvfDuAb1OmSaJgZurgtubDSvzSPEysEfeNoEEkyxJWirpObSCSpEbhGLsEeqXDAlAbtxkvt7b160Q3LUjV4BLyhru0/XzXMG1h2R0mjppspSNvQpxVfoOhptSHhmoBjer79KdA3UDn4B+e0J2nMljtYqE5q9DhwZKY9lOFwFq185E/qAAshqdEX69jcoimB9vGc2IPWsTWKWR7eNMa8qzsDQ1p8fLk0eST3/GmUi4oOh35sMmmYZZShWTCT+Nqvmo0Mc53f5BT8cgqV5ooi50qLR1foT8sl+gB8lmcnioV4bh2FjHvXGfeRyvqEJ+ZZ3ac+i4sqDig/yq2Iyd2IHaqqI2/7IwbS3I/26sB4rvKPFL8bDmhOmFOYHFpgurTE7urJnhnQSIPYRyywbvH0qHtBpN3lTRLfHD3qZNttxEpnMLRcQdmPaDZaGVYy6CdS+hCEYcJbHkBfL1aoQkqLfupYaefozclLsSQY9l6xxrpudTwnQlUYlNMGbTXvg/pHxIo+ck2SC/2dO4HVqhSt9zqdnXaQ+6vEm/a1/eWReIdtGFsEQUgDv/5LsLzTv5P1E5g2v6Ss71kO7k+5RBmjrglNWB9QbvEa6ggkLLtybJn1GZDgRECURgOvzF+cvKGi5XULszR1/PKbaFYIdA== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(136003)(396003)(346002)(376002)(39860400002)(230922051799003)(451199024)(82310400011)(186009)(64100799003)(1800799009)(46966006)(40470700004)(36840700001)(40460700003)(26005)(336012)(33964004)(6506007)(44144004)(6666004)(2616005)(6512007)(36860700001)(83380400001)(44832011)(235185007)(47076005)(8676002)(5660300002)(8936002)(41300700001)(4326008)(2906002)(478600001)(6486002)(316002)(6916009)(54906003)(70206006)(70586007)(36756003)(86362001)(82740400003)(81166007)(356005)(40480700001)(2700100001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2023 18:12:03.3964 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba73c5e0-4375-4db3-1b89-08dbe6cf88fd X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B9D.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB9948 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782745245823033617 X-GMAIL-MSGID: 1782745245823033617 This patch adjusts the mem{cpy,set} expansion in the aarch64 backend to use individual loads/stores instead of ldp/stp at expand time. The idea is to rely on the ldp fusion pass to fuse the accesses together later in the RTL pipeline. The earlier parts of the RTL pipeline should be able to do a better job with the individual (non-paired) accesses, especially given that an earlier patch in this series moves the pair representation to use unspecs. Bootstrapped/regtested as a series on aarch64-linux-gnu, OK for trunk? Thanks, Alex gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_copy_one_block_and_progress_pointers): Emit individual accesses instead of load/store pairs. (aarch64_set_one_block_and_progress_pointer): Likewise. --- gcc/config/aarch64/aarch64.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 1f6094bf1bc..315ba7119c0 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -25457,9 +25457,12 @@ aarch64_copy_one_block_and_progress_pointers (rtx *src, rtx *dst, /* "Cast" the pointers to the correct mode. */ *src = adjust_address (*src, mode, 0); *dst = adjust_address (*dst, mode, 0); - /* Emit the memcpy. */ - emit_insn (aarch64_gen_load_pair (reg1, reg2, *src)); - emit_insn (aarch64_gen_store_pair (*dst, reg1, reg2)); + /* Emit the memcpy. The load/store pair pass should form + a load/store pair from these moves. */ + emit_move_insn (reg1, *src); + emit_move_insn (reg2, aarch64_progress_pointer (*src)); + emit_move_insn (*dst, reg1); + emit_move_insn (aarch64_progress_pointer (*dst), reg2); /* Move the pointers forward. */ *src = aarch64_move_pointer (*src, 32); *dst = aarch64_move_pointer (*dst, 32); @@ -25638,7 +25641,8 @@ aarch64_set_one_block_and_progress_pointer (rtx src, rtx *dst, /* "Cast" the *dst to the correct mode. */ *dst = adjust_address (*dst, mode, 0); /* Emit the memset. */ - emit_insn (aarch64_gen_store_pair (*dst, src, src)); + emit_move_insn (*dst, src); + emit_move_insn (aarch64_progress_pointer (*dst), src); /* Move the pointers forward. */ *dst = aarch64_move_pointer (*dst, 32);